1 /* pci.c: UltraSparc PCI controller support.
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/capability.h>
16 #include <linux/errno.h>
17 #include <linux/msi.h>
18 #include <linux/irq.h>
19 #include <linux/init.h>
21 #include <asm/uaccess.h>
23 #include <asm/pgtable.h>
32 unsigned long pci_memspace_mask
= 0xffffffffUL
;
35 /* A "nop" PCI implementation. */
36 asmlinkage
int sys_pciconfig_read(unsigned long bus
, unsigned long dfn
,
37 unsigned long off
, unsigned long len
,
42 asmlinkage
int sys_pciconfig_write(unsigned long bus
, unsigned long dfn
,
43 unsigned long off
, unsigned long len
,
50 /* List of all PCI controllers found in the system. */
51 struct pci_pbm_info
*pci_pbm_root
= NULL
;
53 /* Each PBM found gets a unique index. */
56 volatile int pci_poke_in_progress
;
57 volatile int pci_poke_cpu
= -1;
58 volatile int pci_poke_faulted
;
60 static DEFINE_SPINLOCK(pci_poke_lock
);
62 void pci_config_read8(u8
*addr
, u8
*ret
)
67 spin_lock_irqsave(&pci_poke_lock
, flags
);
68 pci_poke_cpu
= smp_processor_id();
69 pci_poke_in_progress
= 1;
71 __asm__
__volatile__("membar #Sync\n\t"
72 "lduba [%1] %2, %0\n\t"
75 : "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
77 pci_poke_in_progress
= 0;
79 if (!pci_poke_faulted
)
81 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
84 void pci_config_read16(u16
*addr
, u16
*ret
)
89 spin_lock_irqsave(&pci_poke_lock
, flags
);
90 pci_poke_cpu
= smp_processor_id();
91 pci_poke_in_progress
= 1;
93 __asm__
__volatile__("membar #Sync\n\t"
94 "lduha [%1] %2, %0\n\t"
97 : "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
99 pci_poke_in_progress
= 0;
101 if (!pci_poke_faulted
)
103 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
106 void pci_config_read32(u32
*addr
, u32
*ret
)
111 spin_lock_irqsave(&pci_poke_lock
, flags
);
112 pci_poke_cpu
= smp_processor_id();
113 pci_poke_in_progress
= 1;
114 pci_poke_faulted
= 0;
115 __asm__
__volatile__("membar #Sync\n\t"
116 "lduwa [%1] %2, %0\n\t"
119 : "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
121 pci_poke_in_progress
= 0;
123 if (!pci_poke_faulted
)
125 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
128 void pci_config_write8(u8
*addr
, u8 val
)
132 spin_lock_irqsave(&pci_poke_lock
, flags
);
133 pci_poke_cpu
= smp_processor_id();
134 pci_poke_in_progress
= 1;
135 pci_poke_faulted
= 0;
136 __asm__
__volatile__("membar #Sync\n\t"
137 "stba %0, [%1] %2\n\t"
140 : "r" (val
), "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
142 pci_poke_in_progress
= 0;
144 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
147 void pci_config_write16(u16
*addr
, u16 val
)
151 spin_lock_irqsave(&pci_poke_lock
, flags
);
152 pci_poke_cpu
= smp_processor_id();
153 pci_poke_in_progress
= 1;
154 pci_poke_faulted
= 0;
155 __asm__
__volatile__("membar #Sync\n\t"
156 "stha %0, [%1] %2\n\t"
159 : "r" (val
), "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
161 pci_poke_in_progress
= 0;
163 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
166 void pci_config_write32(u32
*addr
, u32 val
)
170 spin_lock_irqsave(&pci_poke_lock
, flags
);
171 pci_poke_cpu
= smp_processor_id();
172 pci_poke_in_progress
= 1;
173 pci_poke_faulted
= 0;
174 __asm__
__volatile__("membar #Sync\n\t"
175 "stwa %0, [%1] %2\n\t"
178 : "r" (val
), "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
180 pci_poke_in_progress
= 0;
182 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
185 /* Probe for all PCI controllers in the system. */
186 extern void sabre_init(struct device_node
*, const char *);
187 extern void psycho_init(struct device_node
*, const char *);
188 extern void schizo_init(struct device_node
*, const char *);
189 extern void schizo_plus_init(struct device_node
*, const char *);
190 extern void tomatillo_init(struct device_node
*, const char *);
191 extern void sun4v_pci_init(struct device_node
*, const char *);
192 extern void fire_pci_init(struct device_node
*, const char *);
196 void (*init
)(struct device_node
*, const char *);
197 } pci_controller_table
[] __initdata
= {
198 { "SUNW,sabre", sabre_init
},
199 { "pci108e,a000", sabre_init
},
200 { "pci108e,a001", sabre_init
},
201 { "SUNW,psycho", psycho_init
},
202 { "pci108e,8000", psycho_init
},
203 { "SUNW,schizo", schizo_init
},
204 { "pci108e,8001", schizo_init
},
205 { "SUNW,schizo+", schizo_plus_init
},
206 { "pci108e,8002", schizo_plus_init
},
207 { "SUNW,tomatillo", tomatillo_init
},
208 { "pci108e,a801", tomatillo_init
},
209 { "SUNW,sun4v-pci", sun4v_pci_init
},
210 { "pciex108e,80f0", fire_pci_init
},
212 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
213 sizeof(pci_controller_table[0]))
215 static int __init
pci_controller_init(const char *model_name
, int namelen
, struct device_node
*dp
)
219 for (i
= 0; i
< PCI_NUM_CONTROLLER_TYPES
; i
++) {
220 if (!strncmp(model_name
,
221 pci_controller_table
[i
].model_name
,
223 pci_controller_table
[i
].init(dp
, model_name
);
231 static int __init
pci_is_controller(const char *model_name
, int namelen
, struct device_node
*dp
)
235 for (i
= 0; i
< PCI_NUM_CONTROLLER_TYPES
; i
++) {
236 if (!strncmp(model_name
,
237 pci_controller_table
[i
].model_name
,
245 static int __init
pci_controller_scan(int (*handler
)(const char *, int, struct device_node
*))
247 struct device_node
*dp
;
250 for_each_node_by_name(dp
, "pci") {
251 struct property
*prop
;
254 prop
= of_find_property(dp
, "model", &len
);
256 prop
= of_find_property(dp
, "compatible", &len
);
259 const char *model
= prop
->value
;
262 /* Our value may be a multi-valued string in the
263 * case of some compatible properties. For sanity,
264 * only try the first one.
266 while (model
[item_len
] && len
) {
271 if (handler(model
, item_len
, dp
))
280 /* Is there some PCI controller in the system? */
281 int __init
pcic_present(void)
283 return pci_controller_scan(pci_is_controller
);
286 const struct pci_iommu_ops
*pci_iommu_ops
;
287 EXPORT_SYMBOL(pci_iommu_ops
);
289 extern const struct pci_iommu_ops pci_sun4u_iommu_ops
,
292 /* Find each controller in the system, attach and initialize
293 * software state structure for each and link into the
294 * pci_pbm_root. Setup the controller enough such
295 * that bus scanning can be done.
297 static void __init
pci_controller_probe(void)
299 if (tlb_type
== hypervisor
)
300 pci_iommu_ops
= &pci_sun4v_iommu_ops
;
302 pci_iommu_ops
= &pci_sun4u_iommu_ops
;
304 printk("PCI: Probing for controllers.\n");
306 pci_controller_scan(pci_controller_init
);
309 static unsigned long pci_parse_of_flags(u32 addr0
)
311 unsigned long flags
= 0;
313 if (addr0
& 0x02000000) {
314 flags
= IORESOURCE_MEM
| PCI_BASE_ADDRESS_SPACE_MEMORY
;
315 flags
|= (addr0
>> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64
;
316 flags
|= (addr0
>> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M
;
317 if (addr0
& 0x40000000)
318 flags
|= IORESOURCE_PREFETCH
319 | PCI_BASE_ADDRESS_MEM_PREFETCH
;
320 } else if (addr0
& 0x01000000)
321 flags
= IORESOURCE_IO
| PCI_BASE_ADDRESS_SPACE_IO
;
325 /* The of_device layer has translated all of the assigned-address properties
326 * into physical address resources, we only have to figure out the register
329 static void pci_parse_of_addrs(struct of_device
*op
,
330 struct device_node
*node
,
333 struct resource
*op_res
;
337 addrs
= of_get_property(node
, "assigned-addresses", &proplen
);
340 printk(" parse addresses (%d bytes) @ %p\n", proplen
, addrs
);
341 op_res
= &op
->resource
[0];
342 for (; proplen
>= 20; proplen
-= 20, addrs
+= 5, op_res
++) {
343 struct resource
*res
;
347 flags
= pci_parse_of_flags(addrs
[0]);
351 printk(" start: %lx, end: %lx, i: %x\n",
352 op_res
->start
, op_res
->end
, i
);
354 if (PCI_BASE_ADDRESS_0
<= i
&& i
<= PCI_BASE_ADDRESS_5
) {
355 res
= &dev
->resource
[(i
- PCI_BASE_ADDRESS_0
) >> 2];
356 } else if (i
== dev
->rom_base_reg
) {
357 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
358 flags
|= IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
360 printk(KERN_ERR
"PCI: bad cfg reg num 0x%x\n", i
);
363 res
->start
= op_res
->start
;
364 res
->end
= op_res
->end
;
366 res
->name
= pci_name(dev
);
370 struct pci_dev
*of_create_pci_dev(struct pci_pbm_info
*pbm
,
371 struct device_node
*node
,
372 struct pci_bus
*bus
, int devfn
,
375 struct dev_archdata
*sd
;
380 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
384 sd
= &dev
->dev
.archdata
;
385 sd
->iommu
= pbm
->iommu
;
387 sd
->host_controller
= pbm
;
388 sd
->prom_node
= node
;
389 sd
->op
= of_find_device_by_node(node
);
390 sd
->msi_num
= 0xffffffff;
392 type
= of_get_property(node
, "device_type", NULL
);
396 printk(" create device, devfn: %x, type: %s hostcontroller(%d)\n",
397 devfn
, type
, host_controller
);
401 dev
->dev
.parent
= bus
->bridge
;
402 dev
->dev
.bus
= &pci_bus_type
;
404 dev
->multifunction
= 0; /* maybe a lie? */
406 if (host_controller
) {
407 dev
->vendor
= 0x108e;
408 dev
->device
= 0x8000;
409 dev
->subsystem_vendor
= 0x0000;
410 dev
->subsystem_device
= 0x0000;
412 dev
->class = PCI_CLASS_BRIDGE_HOST
<< 8;
413 sprintf(pci_name(dev
), "%04x:%02x:%02x.%d", pci_domain_nr(bus
),
414 0x00, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
416 dev
->vendor
= of_getintprop_default(node
, "vendor-id", 0xffff);
417 dev
->device
= of_getintprop_default(node
, "device-id", 0xffff);
418 dev
->subsystem_vendor
=
419 of_getintprop_default(node
, "subsystem-vendor-id", 0);
420 dev
->subsystem_device
=
421 of_getintprop_default(node
, "subsystem-id", 0);
423 dev
->cfg_size
= pci_cfg_space_size(dev
);
425 /* We can't actually use the firmware value, we have
426 * to read what is in the register right now. One
427 * reason is that in the case of IDE interfaces the
428 * firmware can sample the value before the the IDE
429 * interface is programmed into native mode.
431 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
432 dev
->class = class >> 8;
434 sprintf(pci_name(dev
), "%04x:%02x:%02x.%d", pci_domain_nr(bus
),
435 dev
->bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
437 printk(" class: 0x%x device name: %s\n",
438 dev
->class, pci_name(dev
));
440 /* I have seen IDE devices which will not respond to
441 * the bmdma simplex check reads if bus mastering is
444 if ((dev
->class >> 8) == PCI_CLASS_STORAGE_IDE
)
447 dev
->current_state
= 4; /* unknown power state */
448 dev
->error_state
= pci_channel_io_normal
;
450 if (host_controller
) {
451 dev
->hdr_type
= PCI_HEADER_TYPE_BRIDGE
;
452 dev
->rom_base_reg
= PCI_ROM_ADDRESS1
;
453 dev
->irq
= PCI_IRQ_NONE
;
455 if (!strcmp(type
, "pci") || !strcmp(type
, "pciex")) {
456 /* a PCI-PCI bridge */
457 dev
->hdr_type
= PCI_HEADER_TYPE_BRIDGE
;
458 dev
->rom_base_reg
= PCI_ROM_ADDRESS1
;
459 } else if (!strcmp(type
, "cardbus")) {
460 dev
->hdr_type
= PCI_HEADER_TYPE_CARDBUS
;
462 dev
->hdr_type
= PCI_HEADER_TYPE_NORMAL
;
463 dev
->rom_base_reg
= PCI_ROM_ADDRESS
;
465 dev
->irq
= sd
->op
->irqs
[0];
466 if (dev
->irq
== 0xffffffff)
467 dev
->irq
= PCI_IRQ_NONE
;
470 pci_parse_of_addrs(sd
->op
, node
, dev
);
472 printk(" adding to system ...\n");
474 pci_device_add(dev
, bus
);
479 static void __devinit
apb_calc_first_last(u8 map
, u32
*first_p
, u32
*last_p
)
481 u32 idx
, first
, last
;
485 for (idx
= 0; idx
< 8; idx
++) {
486 if ((map
& (1 << idx
)) != 0) {
498 static void __init
pci_resource_adjust(struct resource
*res
,
499 struct resource
*root
)
501 res
->start
+= root
->start
;
502 res
->end
+= root
->start
;
505 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
506 * a proper 'ranges' property.
508 static void __devinit
apb_fake_ranges(struct pci_dev
*dev
,
510 struct pci_pbm_info
*pbm
)
512 struct resource
*res
;
516 pci_read_config_byte(dev
, APB_IO_ADDRESS_MAP
, &map
);
517 apb_calc_first_last(map
, &first
, &last
);
518 res
= bus
->resource
[0];
519 res
->start
= (first
<< 21);
520 res
->end
= (last
<< 21) + ((1 << 21) - 1);
521 res
->flags
= IORESOURCE_IO
;
522 pci_resource_adjust(res
, &pbm
->io_space
);
524 pci_read_config_byte(dev
, APB_MEM_ADDRESS_MAP
, &map
);
525 apb_calc_first_last(map
, &first
, &last
);
526 res
= bus
->resource
[1];
527 res
->start
= (first
<< 21);
528 res
->end
= (last
<< 21) + ((1 << 21) - 1);
529 res
->flags
= IORESOURCE_MEM
;
530 pci_resource_adjust(res
, &pbm
->mem_space
);
533 static void __devinit
pci_of_scan_bus(struct pci_pbm_info
*pbm
,
534 struct device_node
*node
,
535 struct pci_bus
*bus
);
537 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
539 static void __devinit
of_scan_pci_bridge(struct pci_pbm_info
*pbm
,
540 struct device_node
*node
,
544 const u32
*busrange
, *ranges
;
546 struct resource
*res
;
550 printk("of_scan_pci_bridge(%s)\n", node
->full_name
);
552 /* parse bus-range property */
553 busrange
= of_get_property(node
, "bus-range", &len
);
554 if (busrange
== NULL
|| len
!= 8) {
555 printk(KERN_DEBUG
"Can't get bus-range for PCI-PCI bridge %s\n",
559 ranges
= of_get_property(node
, "ranges", &len
);
561 if (ranges
== NULL
) {
562 const char *model
= of_get_property(node
, "model", NULL
);
563 if (model
&& !strcmp(model
, "SUNW,simba")) {
566 printk(KERN_DEBUG
"Can't get ranges for PCI-PCI bridge %s\n",
572 bus
= pci_add_new_bus(dev
->bus
, dev
, busrange
[0]);
574 printk(KERN_ERR
"Failed to create pci bus for %s\n",
579 bus
->primary
= dev
->bus
->number
;
580 bus
->subordinate
= busrange
[1];
583 /* parse ranges property, or cook one up by hand for Simba */
584 /* PCI #address-cells == 3 and #size-cells == 2 always */
585 res
= &dev
->resource
[PCI_BRIDGE_RESOURCES
];
586 for (i
= 0; i
< PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
; ++i
) {
588 bus
->resource
[i
] = res
;
592 apb_fake_ranges(dev
, bus
, pbm
);
596 for (; len
>= 32; len
-= 32, ranges
+= 8) {
597 struct resource
*root
;
599 flags
= pci_parse_of_flags(ranges
[0]);
600 size
= GET_64BIT(ranges
, 6);
601 if (flags
== 0 || size
== 0)
603 if (flags
& IORESOURCE_IO
) {
604 res
= bus
->resource
[0];
606 printk(KERN_ERR
"PCI: ignoring extra I/O range"
607 " for bridge %s\n", node
->full_name
);
610 root
= &pbm
->io_space
;
612 if (i
>= PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
) {
613 printk(KERN_ERR
"PCI: too many memory ranges"
614 " for bridge %s\n", node
->full_name
);
617 res
= bus
->resource
[i
];
619 root
= &pbm
->mem_space
;
622 res
->start
= GET_64BIT(ranges
, 1);
623 res
->end
= res
->start
+ size
- 1;
626 /* Another way to implement this would be to add an of_device
627 * layer routine that can calculate a resource for a given
628 * range property value in a PCI device.
630 pci_resource_adjust(res
, root
);
633 sprintf(bus
->name
, "PCI Bus %04x:%02x", pci_domain_nr(bus
),
635 printk(" bus name: %s\n", bus
->name
);
637 pci_of_scan_bus(pbm
, node
, bus
);
640 static void __devinit
pci_of_scan_bus(struct pci_pbm_info
*pbm
,
641 struct device_node
*node
,
644 struct device_node
*child
;
649 printk("PCI: scan_bus[%s] bus no %d\n",
650 node
->full_name
, bus
->number
);
653 while ((child
= of_get_next_child(node
, child
)) != NULL
) {
654 printk(" * %s\n", child
->full_name
);
655 reg
= of_get_property(child
, "reg", ®len
);
656 if (reg
== NULL
|| reglen
< 20)
658 devfn
= (reg
[0] >> 8) & 0xff;
660 /* create a new pci_dev for this device */
661 dev
= of_create_pci_dev(pbm
, child
, bus
, devfn
, 0);
664 printk("PCI: dev header type: %x\n", dev
->hdr_type
);
666 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
667 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
668 of_scan_pci_bridge(pbm
, child
, dev
);
673 show_pciobppath_attr(struct device
* dev
, struct device_attribute
* attr
, char * buf
)
675 struct pci_dev
*pdev
;
676 struct device_node
*dp
;
678 pdev
= to_pci_dev(dev
);
679 dp
= pdev
->dev
.archdata
.prom_node
;
681 return snprintf (buf
, PAGE_SIZE
, "%s\n", dp
->full_name
);
684 static DEVICE_ATTR(obppath
, S_IRUSR
| S_IRGRP
| S_IROTH
, show_pciobppath_attr
, NULL
);
686 static void __devinit
pci_bus_register_of_sysfs(struct pci_bus
*bus
)
689 struct pci_bus
*child_bus
;
692 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
693 /* we don't really care if we can create this file or
694 * not, but we need to assign the result of the call
695 * or the world will fall under alien invasion and
696 * everybody will be frozen on a spaceship ready to be
697 * eaten on alpha centauri by some green and jelly
700 err
= sysfs_create_file(&dev
->dev
.kobj
, &dev_attr_obppath
.attr
);
702 list_for_each_entry(child_bus
, &bus
->children
, node
)
703 pci_bus_register_of_sysfs(child_bus
);
706 int pci_host_bridge_read_pci_cfg(struct pci_bus
*bus_dev
,
711 static u8 fake_pci_config
[] = {
712 0x8e, 0x10, /* Vendor: 0x108e (Sun) */
713 0x00, 0x80, /* Device: 0x8000 (PBM) */
714 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
715 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
716 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
717 0x00, /* Cacheline: 0x00 */
718 0x40, /* Latency: 0x40 */
719 0x00, /* Header-Type: 0x00 normal */
723 if (where
>= 0 && where
< sizeof(fake_pci_config
) &&
724 (where
+ size
) >= 0 &&
725 (where
+ size
) < sizeof(fake_pci_config
) &&
726 size
<= sizeof(u32
)) {
729 *value
|= fake_pci_config
[where
+ size
];
733 return PCIBIOS_SUCCESSFUL
;
736 int pci_host_bridge_write_pci_cfg(struct pci_bus
*bus_dev
,
741 return PCIBIOS_SUCCESSFUL
;
744 struct pci_bus
* __devinit
pci_scan_one_pbm(struct pci_pbm_info
*pbm
)
746 struct device_node
*node
= pbm
->prom_node
;
747 struct pci_dev
*host_pdev
;
750 printk("PCI: Scanning PBM %s\n", node
->full_name
);
752 /* XXX parent device? XXX */
753 bus
= pci_create_bus(NULL
, pbm
->pci_first_busno
, pbm
->pci_ops
, pbm
);
755 printk(KERN_ERR
"Failed to create bus for %s\n",
759 bus
->secondary
= pbm
->pci_first_busno
;
760 bus
->subordinate
= pbm
->pci_last_busno
;
762 bus
->resource
[0] = &pbm
->io_space
;
763 bus
->resource
[1] = &pbm
->mem_space
;
765 /* Create the dummy host bridge and link it in. */
766 host_pdev
= of_create_pci_dev(pbm
, node
, bus
, 0x00, 1);
767 bus
->self
= host_pdev
;
769 pci_of_scan_bus(pbm
, node
, bus
);
770 pci_bus_add_devices(bus
);
771 pci_bus_register_of_sysfs(bus
);
776 static void __init
pci_scan_each_controller_bus(void)
778 struct pci_pbm_info
*pbm
;
780 for (pbm
= pci_pbm_root
; pbm
; pbm
= pbm
->next
)
784 extern void power_init(void);
786 static int __init
pcibios_init(void)
788 pci_controller_probe();
789 if (pci_pbm_root
== NULL
)
792 pci_scan_each_controller_bus();
801 subsys_initcall(pcibios_init
);
803 void __devinit
pcibios_fixup_bus(struct pci_bus
*pbus
)
805 struct pci_pbm_info
*pbm
= pbus
->sysdata
;
807 /* Generic PCI bus probing sets these to point at
808 * &io{port,mem}_resouce which is wrong for us.
810 pbus
->resource
[0] = &pbm
->io_space
;
811 pbus
->resource
[1] = &pbm
->mem_space
;
814 struct resource
*pcibios_select_root(struct pci_dev
*pdev
, struct resource
*r
)
816 struct pci_pbm_info
*pbm
= pdev
->bus
->sysdata
;
817 struct resource
*root
= NULL
;
819 if (r
->flags
& IORESOURCE_IO
)
820 root
= &pbm
->io_space
;
821 if (r
->flags
& IORESOURCE_MEM
)
822 root
= &pbm
->mem_space
;
827 void pcibios_update_irq(struct pci_dev
*pdev
, int irq
)
831 void pcibios_align_resource(void *data
, struct resource
*res
,
832 resource_size_t size
, resource_size_t align
)
836 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
841 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
844 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
845 struct resource
*res
= &dev
->resource
[i
];
847 /* Only set up the requested stuff */
848 if (!(mask
& (1<<i
)))
851 if (res
->flags
& IORESOURCE_IO
)
852 cmd
|= PCI_COMMAND_IO
;
853 if (res
->flags
& IORESOURCE_MEM
)
854 cmd
|= PCI_COMMAND_MEMORY
;
858 printk(KERN_DEBUG
"PCI: Enabling device: (%s), cmd %x\n",
860 /* Enable the appropriate bits in the PCI command register. */
861 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
866 void pcibios_resource_to_bus(struct pci_dev
*pdev
, struct pci_bus_region
*region
,
867 struct resource
*res
)
869 struct pci_pbm_info
*pbm
= pdev
->bus
->sysdata
;
870 struct resource zero_res
, *root
;
874 zero_res
.flags
= res
->flags
;
876 if (res
->flags
& IORESOURCE_IO
)
877 root
= &pbm
->io_space
;
879 root
= &pbm
->mem_space
;
881 pci_resource_adjust(&zero_res
, root
);
883 region
->start
= res
->start
- zero_res
.start
;
884 region
->end
= res
->end
- zero_res
.start
;
886 EXPORT_SYMBOL(pcibios_resource_to_bus
);
888 void pcibios_bus_to_resource(struct pci_dev
*pdev
, struct resource
*res
,
889 struct pci_bus_region
*region
)
891 struct pci_pbm_info
*pbm
= pdev
->bus
->sysdata
;
892 struct resource
*root
;
894 res
->start
= region
->start
;
895 res
->end
= region
->end
;
897 if (res
->flags
& IORESOURCE_IO
)
898 root
= &pbm
->io_space
;
900 root
= &pbm
->mem_space
;
902 pci_resource_adjust(res
, root
);
904 EXPORT_SYMBOL(pcibios_bus_to_resource
);
906 char * __devinit
pcibios_setup(char *str
)
911 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
913 /* If the user uses a host-bridge as the PCI device, he may use
914 * this to perform a raw mmap() of the I/O or MEM space behind
917 * This can be useful for execution of x86 PCI bios initialization code
918 * on a PCI card, like the xfree86 int10 stuff does.
920 static int __pci_mmap_make_offset_bus(struct pci_dev
*pdev
, struct vm_area_struct
*vma
,
921 enum pci_mmap_state mmap_state
)
923 struct pci_pbm_info
*pbm
= pdev
->dev
.archdata
.host_controller
;
924 unsigned long space_size
, user_offset
, user_size
;
926 if (mmap_state
== pci_mmap_io
) {
927 space_size
= (pbm
->io_space
.end
-
928 pbm
->io_space
.start
) + 1;
930 space_size
= (pbm
->mem_space
.end
-
931 pbm
->mem_space
.start
) + 1;
934 /* Make sure the request is in range. */
935 user_offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
936 user_size
= vma
->vm_end
- vma
->vm_start
;
938 if (user_offset
>= space_size
||
939 (user_offset
+ user_size
) > space_size
)
942 if (mmap_state
== pci_mmap_io
) {
943 vma
->vm_pgoff
= (pbm
->io_space
.start
+
944 user_offset
) >> PAGE_SHIFT
;
946 vma
->vm_pgoff
= (pbm
->mem_space
.start
+
947 user_offset
) >> PAGE_SHIFT
;
953 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
954 * to the 32-bit pci bus offset for DEV requested by the user.
956 * Basically, the user finds the base address for his device which he wishes
957 * to mmap. They read the 32-bit value from the config space base register,
958 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
959 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
961 * Returns negative error code on failure, zero on success.
963 static int __pci_mmap_make_offset(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
964 enum pci_mmap_state mmap_state
)
966 unsigned long user_offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
967 unsigned long user32
= user_offset
& pci_memspace_mask
;
968 unsigned long largest_base
, this_base
, addr32
;
971 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
)
972 return __pci_mmap_make_offset_bus(dev
, vma
, mmap_state
);
974 /* Figure out which base address this is for. */
976 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
977 struct resource
*rp
= &dev
->resource
[i
];
984 if (i
== PCI_ROM_RESOURCE
) {
985 if (mmap_state
!= pci_mmap_mem
)
988 if ((mmap_state
== pci_mmap_io
&&
989 (rp
->flags
& IORESOURCE_IO
) == 0) ||
990 (mmap_state
== pci_mmap_mem
&&
991 (rp
->flags
& IORESOURCE_MEM
) == 0))
995 this_base
= rp
->start
;
997 addr32
= (this_base
& PAGE_MASK
) & pci_memspace_mask
;
999 if (mmap_state
== pci_mmap_io
)
1002 if (addr32
<= user32
&& this_base
> largest_base
)
1003 largest_base
= this_base
;
1006 if (largest_base
== 0UL)
1009 /* Now construct the final physical address. */
1010 if (mmap_state
== pci_mmap_io
)
1011 vma
->vm_pgoff
= (((largest_base
& ~0xffffffUL
) | user32
) >> PAGE_SHIFT
);
1013 vma
->vm_pgoff
= (((largest_base
& ~(pci_memspace_mask
)) | user32
) >> PAGE_SHIFT
);
1018 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1021 static void __pci_mmap_set_flags(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
1022 enum pci_mmap_state mmap_state
)
1024 vma
->vm_flags
|= (VM_IO
| VM_RESERVED
);
1027 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1030 static void __pci_mmap_set_pgprot(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
1031 enum pci_mmap_state mmap_state
)
1033 /* Our io_remap_pfn_range takes care of this, do nothing. */
1036 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1037 * for this architecture. The region in the process to map is described by vm_start
1038 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1039 * The pci device structure is provided so that architectures may make mapping
1040 * decisions on a per-device or per-bus basis.
1042 * Returns a negative error code on failure, zero on success.
1044 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
1045 enum pci_mmap_state mmap_state
,
1050 ret
= __pci_mmap_make_offset(dev
, vma
, mmap_state
);
1054 __pci_mmap_set_flags(dev
, vma
, mmap_state
);
1055 __pci_mmap_set_pgprot(dev
, vma
, mmap_state
);
1057 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
1058 ret
= io_remap_pfn_range(vma
, vma
->vm_start
,
1060 vma
->vm_end
- vma
->vm_start
,
1068 /* Return the domain nuber for this pci bus */
1070 int pci_domain_nr(struct pci_bus
*pbus
)
1072 struct pci_pbm_info
*pbm
= pbus
->sysdata
;
1075 if (pbm
== NULL
|| pbm
->parent
== NULL
) {
1083 EXPORT_SYMBOL(pci_domain_nr
);
1085 #ifdef CONFIG_PCI_MSI
1086 int arch_setup_msi_irq(struct pci_dev
*pdev
, struct msi_desc
*desc
)
1088 struct pci_pbm_info
*pbm
= pdev
->dev
.archdata
.host_controller
;
1091 if (!pbm
->setup_msi_irq
)
1094 return pbm
->setup_msi_irq(&virt_irq
, pdev
, desc
);
1097 void arch_teardown_msi_irq(unsigned int virt_irq
)
1099 struct msi_desc
*entry
= get_irq_msi(virt_irq
);
1100 struct pci_dev
*pdev
= entry
->dev
;
1101 struct pci_pbm_info
*pbm
= pdev
->dev
.archdata
.host_controller
;
1103 if (!pbm
->teardown_msi_irq
)
1106 return pbm
->teardown_msi_irq(virt_irq
, pdev
);
1108 #endif /* !(CONFIG_PCI_MSI) */
1110 struct device_node
*pci_device_to_OF_node(struct pci_dev
*pdev
)
1112 return pdev
->dev
.archdata
.prom_node
;
1114 EXPORT_SYMBOL(pci_device_to_OF_node
);
1116 #endif /* !(CONFIG_PCI) */