drivers/net/ixgb/ixgb_hw.h

   1 /*******************************************************************************
   2
   3
   4   Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms of the GNU General Public License as published by the Free
   8   Software Foundation; either version 2 of the License, or (at your option)
   9   any later version.
  10
  11   This program is distributed in the hope that it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc., 59
  18   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  19
  20   The full GNU General Public License is included in this distribution in the
  21   file called LICENSE.
  22
  23   Contact Information:
  24   Linux NICS <linux.nics@intel.com>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _IXGB_HW_H_
  30 #define _IXGB_HW_H_
  31
  32 #include "ixgb_osdep.h"
  33
  34 /* Enums */
  35 typedef enum {
  36         ixgb_mac_unknown = 0,
  37         ixgb_82597,
  38         ixgb_num_macs
  39 } ixgb_mac_type;
  40
  41 /* Types of physical layer modules */
  42 typedef enum {
  43         ixgb_phy_type_unknown = 0,
  44         ixgb_phy_type_g6005,    /* 850nm, MM fiber, XPAK transceiver */
  45         ixgb_phy_type_g6104,    /* 1310nm, SM fiber, XPAK transceiver */
  46         ixgb_phy_type_txn17201, /* 850nm, MM fiber, XPAK transceiver */
  47         ixgb_phy_type_txn17401  /* 1310nm, SM fiber, XENPAK transceiver */
  48 } ixgb_phy_type;
  49
  50 /* XPAK transceiver vendors, for the SR adapters */
  51 typedef enum {
  52         ixgb_xpak_vendor_intel,
  53         ixgb_xpak_vendor_infineon
  54 } ixgb_xpak_vendor;
  55
  56 /* Media Types */
  57 typedef enum {
  58         ixgb_media_type_unknown = 0,
  59         ixgb_media_type_fiber = 1,
  60         ixgb_media_type_copper = 2,
  61         ixgb_num_media_types
  62 } ixgb_media_type;
  63
  64 /* Flow Control Settings */
  65 typedef enum {
  66         ixgb_fc_none = 0,
  67         ixgb_fc_rx_pause = 1,
  68         ixgb_fc_tx_pause = 2,
  69         ixgb_fc_full = 3,
  70         ixgb_fc_default = 0xFF
  71 } ixgb_fc_type;
  72
  73 /* PCI bus types */
  74 typedef enum {
  75         ixgb_bus_type_unknown = 0,
  76         ixgb_bus_type_pci,
  77         ixgb_bus_type_pcix
  78 } ixgb_bus_type;
  79
  80 /* PCI bus speeds */
  81 typedef enum {
  82         ixgb_bus_speed_unknown = 0,
  83         ixgb_bus_speed_33,
  84         ixgb_bus_speed_66,
  85         ixgb_bus_speed_100,
  86         ixgb_bus_speed_133,
  87         ixgb_bus_speed_reserved
  88 } ixgb_bus_speed;
  89
  90 /* PCI bus widths */
  91 typedef enum {
  92         ixgb_bus_width_unknown = 0,
  93         ixgb_bus_width_32,
  94         ixgb_bus_width_64
  95 } ixgb_bus_width;
  96
  97 #define IXGB_ETH_LENGTH_OF_ADDRESS   6
  98
  99 #define IXGB_EEPROM_SIZE    64  /* Size in words */
 100
 101 #define SPEED_10000  10000
 102 #define FULL_DUPLEX  2
 103
 104 #define MIN_NUMBER_OF_DESCRIPTORS       8
 105 #define MAX_NUMBER_OF_DESCRIPTORS  0xFFF8       /* 13 bits in RDLEN/TDLEN, 128B aligned     */
 106
 107 #define IXGB_DELAY_BEFORE_RESET        10       /* allow 10ms after idling rx/tx units      */
 108 #define IXGB_DELAY_AFTER_RESET          1       /* allow 1ms after the reset                */
 109 #define IXGB_DELAY_AFTER_EE_RESET      10       /* allow 10ms after the EEPROM reset        */
 110
 111 #define IXGB_DELAY_USECS_AFTER_LINK_RESET    13 /* allow 13 microseconds after the reset    */
 112                                            /* NOTE: this is MICROSECONDS               */
 113 #define MAX_RESET_ITERATIONS            8       /* number of iterations to get things right */
 114
 115 /* General Registers */
 116 #define IXGB_CTRL0   0x00000    /* Device Control Register 0 - RW */
 117 #define IXGB_CTRL1   0x00008    /* Device Control Register 1 - RW */
 118 #define IXGB_STATUS  0x00010    /* Device Status Register - RO */
 119 #define IXGB_EECD    0x00018    /* EEPROM/Flash Control/Data Register - RW */
 120 #define IXGB_MFS     0x00020    /* Maximum Frame Size - RW */
 121
 122 /* Interrupt */
 123 #define IXGB_ICR     0x00080    /* Interrupt Cause Read - R/clr */
 124 #define IXGB_ICS     0x00088    /* Interrupt Cause Set - RW */
 125 #define IXGB_IMS     0x00090    /* Interrupt Mask Set/Read - RW */
 126 #define IXGB_IMC     0x00098    /* Interrupt Mask Clear - WO */
 127
 128 /* Receive */
 129 #define IXGB_RCTL    0x00100    /* RX Control - RW */
 130 #define IXGB_FCRTL   0x00108    /* Flow Control Receive Threshold Low - RW */
 131 #define IXGB_FCRTH   0x00110    /* Flow Control Receive Threshold High - RW */
 132 #define IXGB_RDBAL   0x00118    /* RX Descriptor Base Low - RW */
 133 #define IXGB_RDBAH   0x0011C    /* RX Descriptor Base High - RW */
 134 #define IXGB_RDLEN   0x00120    /* RX Descriptor Length - RW */
 135 #define IXGB_RDH     0x00128    /* RX Descriptor Head - RW */
 136 #define IXGB_RDT     0x00130    /* RX Descriptor Tail - RW */
 137 #define IXGB_RDTR    0x00138    /* RX Delay Timer Ring - RW */
 138 #define IXGB_RXDCTL  0x00140    /* Receive Descriptor Control - RW */
 139 #define IXGB_RAIDC   0x00148    /* Receive Adaptive Interrupt Delay Control - RW */
 140 #define IXGB_RXCSUM  0x00158    /* Receive Checksum Control - RW */
 141 #define IXGB_RA      0x00180    /* Receive Address Array Base - RW */
 142 #define IXGB_RAL     0x00180    /* Receive Address Low [0:15] - RW */
 143 #define IXGB_RAH     0x00184    /* Receive Address High [0:15] - RW */
 144 #define IXGB_MTA     0x00200    /* Multicast Table Array [0:127] - RW */
 145 #define IXGB_VFTA    0x00400    /* VLAN Filter Table Array [0:127] - RW */
 146 #define IXGB_REQ_RX_DESCRIPTOR_MULTIPLE 8
 147
 148 /* Transmit */
 149 #define IXGB_TCTL    0x00600    /* TX Control - RW */
 150 #define IXGB_TDBAL   0x00608    /* TX Descriptor Base Low - RW */
 151 #define IXGB_TDBAH   0x0060C    /* TX Descriptor Base High - RW */
 152 #define IXGB_TDLEN   0x00610    /* TX Descriptor Length - RW */
 153 #define IXGB_TDH     0x00618    /* TX Descriptor Head - RW */
 154 #define IXGB_TDT     0x00620    /* TX Descriptor Tail - RW */
 155 #define IXGB_TIDV    0x00628    /* TX Interrupt Delay Value - RW */
 156 #define IXGB_TXDCTL  0x00630    /* Transmit Descriptor Control - RW */
 157 #define IXGB_TSPMT   0x00638    /* TCP Segmentation PAD & Min Threshold - RW */
 158 #define IXGB_PAP     0x00640    /* Pause and Pace - RW */
 159 #define IXGB_REQ_TX_DESCRIPTOR_MULTIPLE 8
 160
 161 /* Physical */
 162 #define IXGB_PCSC1   0x00700    /* PCS Control 1 - RW */
 163 #define IXGB_PCSC2   0x00708    /* PCS Control 2 - RW */
 164 #define IXGB_PCSS1   0x00710    /* PCS Status 1 - RO */
 165 #define IXGB_PCSS2   0x00718    /* PCS Status 2 - RO */
 166 #define IXGB_XPCSS   0x00720    /* 10GBASE-X PCS Status (or XGXS Lane Status) - RO */
 167 #define IXGB_UCCR    0x00728    /* Unilink Circuit Control Register */
 168 #define IXGB_XPCSTC  0x00730    /* 10GBASE-X PCS Test Control */
 169 #define IXGB_MACA    0x00738    /* MDI Autoscan Command and Address - RW */
 170 #define IXGB_APAE    0x00740    /* Autoscan PHY Address Enable - RW */
 171 #define IXGB_ARD     0x00748    /* Autoscan Read Data - RO */
 172 #define IXGB_AIS     0x00750    /* Autoscan Interrupt Status - RO */
 173 #define IXGB_MSCA    0x00758    /* MDI Single Command and Address - RW */
 174 #define IXGB_MSRWD   0x00760    /* MDI Single Read and Write Data - RW, RO */
 175
 176 /* Wake-up */
 177 #define IXGB_WUFC    0x00808    /* Wake Up Filter Control - RW */
 178 #define IXGB_WUS     0x00810    /* Wake Up Status - RO */
 179 #define IXGB_FFLT    0x01000    /* Flexible Filter Length Table - RW */
 180 #define IXGB_FFMT    0x01020    /* Flexible Filter Mask Table - RW */
 181 #define IXGB_FTVT    0x01420    /* Flexible Filter Value Table - RW */
 182
 183 /* Statistics */
 184 #define IXGB_TPRL    0x02000    /* Total Packets Received (Low) */
 185 #define IXGB_TPRH    0x02004    /* Total Packets Received (High) */
 186 #define IXGB_GPRCL   0x02008    /* Good Packets Received Count (Low) */
 187 #define IXGB_GPRCH   0x0200C    /* Good Packets Received Count (High) */
 188 #define IXGB_BPRCL   0x02010    /* Broadcast Packets Received Count (Low) */
 189 #define IXGB_BPRCH   0x02014    /* Broadcast Packets Received Count (High) */
 190 #define IXGB_MPRCL   0x02018    /* Multicast Packets Received Count (Low) */
 191 #define IXGB_MPRCH   0x0201C    /* Multicast Packets Received Count (High) */
 192 #define IXGB_UPRCL   0x02020    /* Unicast Packets Received Count (Low) */
 193 #define IXGB_UPRCH   0x02024    /* Unicast Packets Received Count (High) */
 194 #define IXGB_VPRCL   0x02028    /* VLAN Packets Received Count (Low) */
 195 #define IXGB_VPRCH   0x0202C    /* VLAN Packets Received Count (High) */
 196 #define IXGB_JPRCL   0x02030    /* Jumbo Packets Received Count (Low) */
 197 #define IXGB_JPRCH   0x02034    /* Jumbo Packets Received Count (High) */
 198 #define IXGB_GORCL   0x02038    /* Good Octets Received Count (Low) */
 199 #define IXGB_GORCH   0x0203C    /* Good Octets Received Count (High) */
 200 #define IXGB_TORL    0x02040    /* Total Octets Received (Low) */
 201 #define IXGB_TORH    0x02044    /* Total Octets Received (High) */
 202 #define IXGB_RNBC    0x02048    /* Receive No Buffers Count */
 203 #define IXGB_RUC     0x02050    /* Receive Undersize Count */
 204 #define IXGB_ROC     0x02058    /* Receive Oversize Count */
 205 #define IXGB_RLEC    0x02060    /* Receive Length Error Count */
 206 #define IXGB_CRCERRS 0x02068    /* CRC Error Count */
 207 #define IXGB_ICBC    0x02070    /* Illegal control byte in mid-packet Count */
 208 #define IXGB_ECBC    0x02078    /* Error Control byte in mid-packet Count */
 209 #define IXGB_MPC     0x02080    /* Missed Packets Count */
 210 #define IXGB_TPTL    0x02100    /* Total Packets Transmitted (Low) */
 211 #define IXGB_TPTH    0x02104    /* Total Packets Transmitted (High) */
 212 #define IXGB_GPTCL   0x02108    /* Good Packets Transmitted Count (Low) */
 213 #define IXGB_GPTCH   0x0210C    /* Good Packets Transmitted Count (High) */
 214 #define IXGB_BPTCL   0x02110    /* Broadcast Packets Transmitted Count (Low) */
 215 #define IXGB_BPTCH   0x02114    /* Broadcast Packets Transmitted Count (High) */
 216 #define IXGB_MPTCL   0x02118    /* Multicast Packets Transmitted Count (Low) */
 217 #define IXGB_MPTCH   0x0211C    /* Multicast Packets Transmitted Count (High) */
 218 #define IXGB_UPTCL   0x02120    /* Unicast Packets Transmitted Count (Low) */
 219 #define IXGB_UPTCH   0x02124    /* Unicast Packets Transmitted Count (High) */
 220 #define IXGB_VPTCL   0x02128    /* VLAN Packets Transmitted Count (Low) */
 221 #define IXGB_VPTCH   0x0212C    /* VLAN Packets Transmitted Count (High) */
 222 #define IXGB_JPTCL   0x02130    /* Jumbo Packets Transmitted Count (Low) */
 223 #define IXGB_JPTCH   0x02134    /* Jumbo Packets Transmitted Count (High) */
 224 #define IXGB_GOTCL   0x02138    /* Good Octets Transmitted Count (Low) */
 225 #define IXGB_GOTCH   0x0213C    /* Good Octets Transmitted Count (High) */
 226 #define IXGB_TOTL    0x02140    /* Total Octets Transmitted Count (Low) */
 227 #define IXGB_TOTH    0x02144    /* Total Octets Transmitted Count (High) */
 228 #define IXGB_DC      0x02148    /* Defer Count */
 229 #define IXGB_PLT64C  0x02150    /* Packet Transmitted was less than 64 bytes Count */
 230 #define IXGB_TSCTC   0x02170    /* TCP Segmentation Context Transmitted Count */
 231 #define IXGB_TSCTFC  0x02178    /* TCP Segmentation Context Tx Fail Count */
 232 #define IXGB_IBIC    0x02180    /* Illegal byte during Idle stream count */
 233 #define IXGB_RFC     0x02188    /* Remote Fault Count */
 234 #define IXGB_LFC     0x02190    /* Local Fault Count */
 235 #define IXGB_PFRC    0x02198    /* Pause Frame Receive Count */
 236 #define IXGB_PFTC    0x021A0    /* Pause Frame Transmit Count */
 237 #define IXGB_MCFRC   0x021A8    /* MAC Control Frames (non-Pause) Received Count */
 238 #define IXGB_MCFTC   0x021B0    /* MAC Control Frames (non-Pause) Transmitted Count */
 239 #define IXGB_XONRXC  0x021B8    /* XON Received Count */
 240 #define IXGB_XONTXC  0x021C0    /* XON Transmitted Count */
 241 #define IXGB_XOFFRXC 0x021C8    /* XOFF Received Count */
 242 #define IXGB_XOFFTXC 0x021D0    /* XOFF Transmitted Count */
 243 #define IXGB_RJC     0x021D8    /* Receive Jabber Count */
 244
 245 /* CTRL0 Bit Masks */
 246 #define IXGB_CTRL0_LRST     0x00000008
 247 #define IXGB_CTRL0_JFE      0x00000010
 248 #define IXGB_CTRL0_XLE      0x00000020
 249 #define IXGB_CTRL0_MDCS     0x00000040
 250 #define IXGB_CTRL0_CMDC     0x00000080
 251 #define IXGB_CTRL0_SDP0     0x00040000
 252 #define IXGB_CTRL0_SDP1     0x00080000
 253 #define IXGB_CTRL0_SDP2     0x00100000
 254 #define IXGB_CTRL0_SDP3     0x00200000
 255 #define IXGB_CTRL0_SDP0_DIR 0x00400000
 256 #define IXGB_CTRL0_SDP1_DIR 0x00800000
 257 #define IXGB_CTRL0_SDP2_DIR 0x01000000
 258 #define IXGB_CTRL0_SDP3_DIR 0x02000000
 259 #define IXGB_CTRL0_RST      0x04000000
 260 #define IXGB_CTRL0_RPE      0x08000000
 261 #define IXGB_CTRL0_TPE      0x10000000
 262 #define IXGB_CTRL0_VME      0x40000000
 263
 264 /* CTRL1 Bit Masks */
 265 #define IXGB_CTRL1_GPI0_EN     0x00000001
 266 #define IXGB_CTRL1_GPI1_EN     0x00000002
 267 #define IXGB_CTRL1_GPI2_EN     0x00000004
 268 #define IXGB_CTRL1_GPI3_EN     0x00000008
 269 #define IXGB_CTRL1_SDP4        0x00000010
 270 #define IXGB_CTRL1_SDP5        0x00000020
 271 #define IXGB_CTRL1_SDP6        0x00000040
 272 #define IXGB_CTRL1_SDP7        0x00000080
 273 #define IXGB_CTRL1_SDP4_DIR    0x00000100
 274 #define IXGB_CTRL1_SDP5_DIR    0x00000200
 275 #define IXGB_CTRL1_SDP6_DIR    0x00000400
 276 #define IXGB_CTRL1_SDP7_DIR    0x00000800
 277 #define IXGB_CTRL1_EE_RST      0x00002000
 278 #define IXGB_CTRL1_RO_DIS      0x00020000
 279 #define IXGB_CTRL1_PCIXHM_MASK 0x00C00000
 280 #define IXGB_CTRL1_PCIXHM_1_2  0x00000000
 281 #define IXGB_CTRL1_PCIXHM_5_8  0x00400000
 282 #define IXGB_CTRL1_PCIXHM_3_4  0x00800000
 283 #define IXGB_CTRL1_PCIXHM_7_8  0x00C00000
 284
 285 /* STATUS Bit Masks */
 286 #define IXGB_STATUS_LU            0x00000002
 287 #define IXGB_STATUS_AIP           0x00000004
 288 #define IXGB_STATUS_TXOFF         0x00000010
 289 #define IXGB_STATUS_XAUIME        0x00000020
 290 #define IXGB_STATUS_RES           0x00000040
 291 #define IXGB_STATUS_RIS           0x00000080
 292 #define IXGB_STATUS_RIE           0x00000100
 293 #define IXGB_STATUS_RLF           0x00000200
 294 #define IXGB_STATUS_RRF           0x00000400
 295 #define IXGB_STATUS_PCI_SPD       0x00000800
 296 #define IXGB_STATUS_BUS64         0x00001000
 297 #define IXGB_STATUS_PCIX_MODE     0x00002000
 298 #define IXGB_STATUS_PCIX_SPD_MASK 0x0000C000
 299 #define IXGB_STATUS_PCIX_SPD_66   0x00000000
 300 #define IXGB_STATUS_PCIX_SPD_100  0x00004000
 301 #define IXGB_STATUS_PCIX_SPD_133  0x00008000
 302 #define IXGB_STATUS_REV_ID_MASK   0x000F0000
 303 #define IXGB_STATUS_REV_ID_SHIFT  16
 304
 305 /* EECD Bit Masks */
 306 #define IXGB_EECD_SK       0x00000001
 307 #define IXGB_EECD_CS       0x00000002
 308 #define IXGB_EECD_DI       0x00000004
 309 #define IXGB_EECD_DO       0x00000008
 310 #define IXGB_EECD_FWE_MASK 0x00000030
 311 #define IXGB_EECD_FWE_DIS  0x00000010
 312 #define IXGB_EECD_FWE_EN   0x00000020
 313
 314 /* MFS */
 315 #define IXGB_MFS_SHIFT 16
 316
 317 /* Interrupt Register Bit Masks (used for ICR, ICS, IMS, and IMC) */
 318 #define IXGB_INT_TXDW     0x00000001
 319 #define IXGB_INT_TXQE     0x00000002
 320 #define IXGB_INT_LSC      0x00000004
 321 #define IXGB_INT_RXSEQ    0x00000008
 322 #define IXGB_INT_RXDMT0   0x00000010
 323 #define IXGB_INT_RXO      0x00000040
 324 #define IXGB_INT_RXT0     0x00000080
 325 #define IXGB_INT_AUTOSCAN 0x00000200
 326 #define IXGB_INT_GPI0     0x00000800
 327 #define IXGB_INT_GPI1     0x00001000
 328 #define IXGB_INT_GPI2     0x00002000
 329 #define IXGB_INT_GPI3     0x00004000
 330
 331 /* RCTL Bit Masks */
 332 #define IXGB_RCTL_RXEN        0x00000002
 333 #define IXGB_RCTL_SBP         0x00000004
 334 #define IXGB_RCTL_UPE         0x00000008
 335 #define IXGB_RCTL_MPE         0x00000010
 336 #define IXGB_RCTL_RDMTS_MASK  0x00000300
 337 #define IXGB_RCTL_RDMTS_1_2   0x00000000
 338 #define IXGB_RCTL_RDMTS_1_4   0x00000100
 339 #define IXGB_RCTL_RDMTS_1_8   0x00000200
 340 #define IXGB_RCTL_MO_MASK     0x00003000
 341 #define IXGB_RCTL_MO_47_36    0x00000000
 342 #define IXGB_RCTL_MO_46_35    0x00001000
 343 #define IXGB_RCTL_MO_45_34    0x00002000
 344 #define IXGB_RCTL_MO_43_32    0x00003000
 345 #define IXGB_RCTL_MO_SHIFT    12
 346 #define IXGB_RCTL_BAM         0x00008000
 347 #define IXGB_RCTL_BSIZE_MASK  0x00030000
 348 #define IXGB_RCTL_BSIZE_2048  0x00000000
 349 #define IXGB_RCTL_BSIZE_4096  0x00010000
 350 #define IXGB_RCTL_BSIZE_8192  0x00020000
 351 #define IXGB_RCTL_BSIZE_16384 0x00030000
 352 #define IXGB_RCTL_VFE         0x00040000
 353 #define IXGB_RCTL_CFIEN       0x00080000
 354 #define IXGB_RCTL_CFI         0x00100000
 355 #define IXGB_RCTL_RPDA_MASK   0x00600000
 356 #define IXGB_RCTL_RPDA_MC_MAC 0x00000000
 357 #define IXGB_RCTL_MC_ONLY     0x00400000
 358 #define IXGB_RCTL_CFF         0x00800000
 359 #define IXGB_RCTL_SECRC       0x04000000
 360 #define IXGB_RDT_FPDB         0x80000000
 361
 362 #define IXGB_RCTL_IDLE_RX_UNIT 0
 363
 364 /* FCRTL Bit Masks */
 365 #define IXGB_FCRTL_XONE       0x80000000
 366
 367 /* RXDCTL Bit Masks */
 368 #define IXGB_RXDCTL_PTHRESH_MASK  0x000001FF
 369 #define IXGB_RXDCTL_PTHRESH_SHIFT 0
 370 #define IXGB_RXDCTL_HTHRESH_MASK  0x0003FE00
 371 #define IXGB_RXDCTL_HTHRESH_SHIFT 9
 372 #define IXGB_RXDCTL_WTHRESH_MASK  0x07FC0000
 373 #define IXGB_RXDCTL_WTHRESH_SHIFT 18
 374
 375 /* RAIDC Bit Masks */
 376 #define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F
 377 #define IXGB_RAIDC_DELAY_MASK    0x000FF800
 378 #define IXGB_RAIDC_DELAY_SHIFT   11
 379 #define IXGB_RAIDC_POLL_MASK     0x1FF00000
 380 #define IXGB_RAIDC_POLL_SHIFT    20
 381 #define IXGB_RAIDC_RXT_GATE      0x40000000
 382 #define IXGB_RAIDC_EN            0x80000000
 383
 384 #define IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND      1220
 385 #define IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND      244
 386 #define IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND     122
 387 #define IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND     61
 388
 389 /* RXCSUM Bit Masks */
 390 #define IXGB_RXCSUM_IPOFL 0x00000100
 391 #define IXGB_RXCSUM_TUOFL 0x00000200
 392
 393 /* RAH Bit Masks */
 394 #define IXGB_RAH_ASEL_MASK 0x00030000
 395 #define IXGB_RAH_ASEL_DEST 0x00000000
 396 #define IXGB_RAH_ASEL_SRC  0x00010000
 397 #define IXGB_RAH_AV        0x80000000
 398
 399 /* TCTL Bit Masks */
 400 #define IXGB_TCTL_TCE  0x00000001
 401 #define IXGB_TCTL_TXEN 0x00000002
 402 #define IXGB_TCTL_TPDE 0x00000004
 403
 404 #define IXGB_TCTL_IDLE_TX_UNIT  0
 405
 406 /* TXDCTL Bit Masks */
 407 #define IXGB_TXDCTL_PTHRESH_MASK  0x0000007F
 408 #define IXGB_TXDCTL_HTHRESH_MASK  0x00007F00
 409 #define IXGB_TXDCTL_HTHRESH_SHIFT 8
 410 #define IXGB_TXDCTL_WTHRESH_MASK  0x007F0000
 411 #define IXGB_TXDCTL_WTHRESH_SHIFT 16
 412
 413 /* TSPMT Bit Masks */
 414 #define IXGB_TSPMT_TSMT_MASK   0x0000FFFF
 415 #define IXGB_TSPMT_TSPBP_MASK  0xFFFF0000
 416 #define IXGB_TSPMT_TSPBP_SHIFT 16
 417
 418 /* PAP Bit Masks */
 419 #define IXGB_PAP_TXPC_MASK 0x0000FFFF
 420 #define IXGB_PAP_TXPV_MASK 0x000F0000
 421 #define IXGB_PAP_TXPV_10G  0x00000000
 422 #define IXGB_PAP_TXPV_1G   0x00010000
 423 #define IXGB_PAP_TXPV_2G   0x00020000
 424 #define IXGB_PAP_TXPV_3G   0x00030000
 425 #define IXGB_PAP_TXPV_4G   0x00040000
 426 #define IXGB_PAP_TXPV_5G   0x00050000
 427 #define IXGB_PAP_TXPV_6G   0x00060000
 428 #define IXGB_PAP_TXPV_7G   0x00070000
 429 #define IXGB_PAP_TXPV_8G   0x00080000
 430 #define IXGB_PAP_TXPV_9G   0x00090000
 431 #define IXGB_PAP_TXPV_WAN  0x000F0000
 432
 433 /* PCSC1 Bit Masks */
 434 #define IXGB_PCSC1_LOOPBACK 0x00004000
 435
 436 /* PCSC2 Bit Masks */
 437 #define IXGB_PCSC2_PCS_TYPE_MASK  0x00000003
 438 #define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001
 439
 440 /* PCSS1 Bit Masks */
 441 #define IXGB_PCSS1_LOCAL_FAULT    0x00000080
 442 #define IXGB_PCSS1_RX_LINK_STATUS 0x00000004
 443
 444 /* PCSS2 Bit Masks */
 445 #define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000
 446 #define IXGB_PCSS2_DEV_PRES      0x00004000
 447 #define IXGB_PCSS2_TX_LF         0x00000800
 448 #define IXGB_PCSS2_RX_LF         0x00000400
 449 #define IXGB_PCSS2_10GBW         0x00000004
 450 #define IXGB_PCSS2_10GBX         0x00000002
 451 #define IXGB_PCSS2_10GBR         0x00000001
 452
 453 /* XPCSS Bit Masks */
 454 #define IXGB_XPCSS_ALIGN_STATUS 0x00001000
 455 #define IXGB_XPCSS_PATTERN_TEST 0x00000800
 456 #define IXGB_XPCSS_LANE_3_SYNC  0x00000008
 457 #define IXGB_XPCSS_LANE_2_SYNC  0x00000004
 458 #define IXGB_XPCSS_LANE_1_SYNC  0x00000002
 459 #define IXGB_XPCSS_LANE_0_SYNC  0x00000001
 460
 461 /* XPCSTC Bit Masks */
 462 #define IXGB_XPCSTC_BERT_TRIG       0x00200000
 463 #define IXGB_XPCSTC_BERT_SST        0x00100000
 464 #define IXGB_XPCSTC_BERT_PSZ_MASK   0x000C0000
 465 #define IXGB_XPCSTC_BERT_PSZ_SHIFT  17
 466 #define IXGB_XPCSTC_BERT_PSZ_INF    0x00000003
 467 #define IXGB_XPCSTC_BERT_PSZ_68     0x00000001
 468 #define IXGB_XPCSTC_BERT_PSZ_1028   0x00000000
 469
 470 /* MSCA bit Masks */
 471 /* New Protocol Address */
 472 #define IXGB_MSCA_NP_ADDR_MASK      0x0000FFFF
 473 #define IXGB_MSCA_NP_ADDR_SHIFT     0
 474 /* Either Device Type or Register Address,depending on ST_CODE */
 475 #define IXGB_MSCA_DEV_TYPE_MASK     0x001F0000
 476 #define IXGB_MSCA_DEV_TYPE_SHIFT    16
 477 #define IXGB_MSCA_PHY_ADDR_MASK     0x03E00000
 478 #define IXGB_MSCA_PHY_ADDR_SHIFT    21
 479 #define IXGB_MSCA_OP_CODE_MASK      0x0C000000
 480 /* OP_CODE == 00, Address cycle, New Protocol           */
 481 /* OP_CODE == 01, Write operation                       */
 482 /* OP_CODE == 10, Read operation                        */
 483 /* OP_CODE == 11, Read, auto increment, New Protocol    */
 484 #define IXGB_MSCA_ADDR_CYCLE        0x00000000
 485 #define IXGB_MSCA_WRITE             0x04000000
 486 #define IXGB_MSCA_READ              0x08000000
 487 #define IXGB_MSCA_READ_AUTOINC      0x0C000000
 488 #define IXGB_MSCA_OP_CODE_SHIFT     26
 489 #define IXGB_MSCA_ST_CODE_MASK      0x30000000
 490 /* ST_CODE == 00, New Protocol  */
 491 /* ST_CODE == 01, Old Protocol  */
 492 #define IXGB_MSCA_NEW_PROTOCOL      0x00000000
 493 #define IXGB_MSCA_OLD_PROTOCOL      0x10000000
 494 #define IXGB_MSCA_ST_CODE_SHIFT     28
 495 /* Initiate command, self-clearing when command completes */
 496 #define IXGB_MSCA_MDI_COMMAND       0x40000000
 497 /*MDI In Progress Enable. */
 498 #define IXGB_MSCA_MDI_IN_PROG_EN    0x80000000
 499
 500 /* MSRWD bit masks */
 501 #define IXGB_MSRWD_WRITE_DATA_MASK  0x0000FFFF
 502 #define IXGB_MSRWD_WRITE_DATA_SHIFT 0
 503 #define IXGB_MSRWD_READ_DATA_MASK   0xFFFF0000
 504 #define IXGB_MSRWD_READ_DATA_SHIFT  16
 505
 506 /* Definitions for the optics devices on the MDIO bus. */
 507 #define IXGB_PHY_ADDRESS             0x0        /* Single PHY, multiple "Devices" */
 508
 509 /* Standard five-bit Device IDs.  See IEEE 802.3ae, clause 45 */
 510 #define MDIO_PMA_PMD_DID        0x01
 511 #define MDIO_WIS_DID            0x02
 512 #define MDIO_PCS_DID            0x03
 513 #define MDIO_XGXS_DID           0x04
 514
 515 /* Standard PMA/PMD registers and bit definitions. */
 516 /* Note: This is a very limited set of definitions,      */
 517 /* only implemented features are defined.                */
 518 #define MDIO_PMA_PMD_CR1        0x0000
 519 #define MDIO_PMA_PMD_CR1_RESET  0x8000
 520
 521 #define MDIO_PMA_PMD_XPAK_VENDOR_NAME       0x803A      /* XPAK/XENPAK devices only */
 522
 523 /* Vendor-specific MDIO registers */
 524 #define G6XXX_PMA_PMD_VS1                   0xC001      /* Vendor-specific register */
 525 #define G6XXX_XGXS_XAUI_VS2                 0x18        /* Vendor-specific register */
 526
 527 #define G6XXX_PMA_PMD_VS1_PLL_RESET         0x80
 528 #define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET  0x00
 529 #define G6XXX_XGXS_XAUI_VS2_INPUT_MASK      0x0F        /* XAUI lanes synchronized */
 530
 531 /* Layout of a single receive descriptor.  The controller assumes that this
 532  * structure is packed into 16 bytes, which is a safe assumption with most
 533  * compilers.  However, some compilers may insert padding between the fields,
 534  * in which case the structure must be packed in some compiler-specific
 535  * manner. */
 536 struct ixgb_rx_desc {
 537         uint64_t buff_addr;
 538         uint16_t length;
 539         uint16_t reserved;
 540         uint8_t status;
 541         uint8_t errors;
 542         uint16_t special;
 543 };
 544
 545 #define IXGB_RX_DESC_STATUS_DD    0x01
 546 #define IXGB_RX_DESC_STATUS_EOP   0x02
 547 #define IXGB_RX_DESC_STATUS_IXSM  0x04
 548 #define IXGB_RX_DESC_STATUS_VP    0x08
 549 #define IXGB_RX_DESC_STATUS_TCPCS 0x20
 550 #define IXGB_RX_DESC_STATUS_IPCS  0x40
 551 #define IXGB_RX_DESC_STATUS_PIF   0x80
 552
 553 #define IXGB_RX_DESC_ERRORS_CE   0x01
 554 #define IXGB_RX_DESC_ERRORS_SE   0x02
 555 #define IXGB_RX_DESC_ERRORS_P    0x08
 556 #define IXGB_RX_DESC_ERRORS_TCPE 0x20
 557 #define IXGB_RX_DESC_ERRORS_IPE  0x40
 558 #define IXGB_RX_DESC_ERRORS_RXE  0x80
 559
 560 #define IXGB_RX_DESC_SPECIAL_VLAN_MASK  0x0FFF  /* VLAN ID is in lower 12 bits */
 561 #define IXGB_RX_DESC_SPECIAL_PRI_MASK   0xE000  /* Priority is in upper 3 bits */
 562 #define IXGB_RX_DESC_SPECIAL_PRI_SHIFT  0x000D  /* Priority is in upper 3 of 16 */
 563
 564 /* Layout of a single transmit descriptor.  The controller assumes that this
 565  * structure is packed into 16 bytes, which is a safe assumption with most
 566  * compilers.  However, some compilers may insert padding between the fields,
 567  * in which case the structure must be packed in some compiler-specific
 568  * manner. */
 569 struct ixgb_tx_desc {
 570         uint64_t buff_addr;
 571         uint32_t cmd_type_len;
 572         uint8_t status;
 573         uint8_t popts;
 574         uint16_t vlan;
 575 };
 576
 577 #define IXGB_TX_DESC_LENGTH_MASK    0x000FFFFF
 578 #define IXGB_TX_DESC_TYPE_MASK      0x00F00000
 579 #define IXGB_TX_DESC_TYPE_SHIFT     20
 580 #define IXGB_TX_DESC_CMD_MASK       0xFF000000
 581 #define IXGB_TX_DESC_CMD_SHIFT      24
 582 #define IXGB_TX_DESC_CMD_EOP        0x01000000
 583 #define IXGB_TX_DESC_CMD_TSE        0x04000000
 584 #define IXGB_TX_DESC_CMD_RS         0x08000000
 585 #define IXGB_TX_DESC_CMD_VLE        0x40000000
 586 #define IXGB_TX_DESC_CMD_IDE        0x80000000
 587
 588 #define IXGB_TX_DESC_TYPE           0x00100000
 589
 590 #define IXGB_TX_DESC_STATUS_DD  0x01
 591
 592 #define IXGB_TX_DESC_POPTS_IXSM 0x01
 593 #define IXGB_TX_DESC_POPTS_TXSM 0x02
 594 #define IXGB_TX_DESC_SPECIAL_PRI_SHIFT  IXGB_RX_DESC_SPECIAL_PRI_SHIFT  /* Priority is in upper 3 of 16 */
 595
 596 struct ixgb_context_desc {
 597         uint8_t ipcss;
 598         uint8_t ipcso;
 599         uint16_t ipcse;
 600         uint8_t tucss;
 601         uint8_t tucso;
 602         uint16_t tucse;
 603         uint32_t cmd_type_len;
 604         uint8_t status;
 605         uint8_t hdr_len;
 606         uint16_t mss;
 607 };
 608
 609 #define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000
 610 #define IXGB_CONTEXT_DESC_CMD_IP  0x02000000
 611 #define IXGB_CONTEXT_DESC_CMD_TSE 0x04000000
 612 #define IXGB_CONTEXT_DESC_CMD_RS  0x08000000
 613 #define IXGB_CONTEXT_DESC_CMD_IDE 0x80000000
 614
 615 #define IXGB_CONTEXT_DESC_TYPE 0x00000000
 616
 617 #define IXGB_CONTEXT_DESC_STATUS_DD 0x01
 618
 619 /* Filters */
 620 #define IXGB_MC_TBL_SIZE          128   /* Multicast Filter Table (4096 bits) */
 621 #define IXGB_VLAN_FILTER_TBL_SIZE 128   /* VLAN Filter Table (4096 bits) */
 622 #define IXGB_RAR_ENTRIES                  3     /* Number of entries in Rx Address array */
 623
 624 #define IXGB_MEMORY_REGISTER_BASE_ADDRESS   0
 625 #define ENET_HEADER_SIZE                        14
 626 #define ENET_FCS_LENGTH                  4
 627 #define IXGB_MAX_NUM_MULTICAST_ADDRESSES        128
 628 #define IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS    60
 629 #define IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS    1514
 630 #define IXGB_MAX_JUMBO_FRAME_SIZE               0x3F00
 631
 632 /* Phy Addresses */
 633 #define IXGB_OPTICAL_PHY_ADDR 0x0       /* Optical Module phy address */
 634 #define IXGB_XAUII_PHY_ADDR   0x1       /* Xauii transceiver phy address */
 635 #define IXGB_DIAG_PHY_ADDR    0x1F      /* Diagnostic Device phy address */
 636
 637 /* This structure takes a 64k flash and maps it for identification commands */
 638 struct ixgb_flash_buffer {
 639         uint8_t manufacturer_id;
 640         uint8_t device_id;
 641         uint8_t filler1[0x2AA8];
 642         uint8_t cmd2;
 643         uint8_t filler2[0x2AAA];
 644         uint8_t cmd1;
 645         uint8_t filler3[0xAAAA];
 646 };
 647
 648 /*
 649  * This is a little-endian specific check.
 650  */
 651 #define IS_MULTICAST(Address) \
 652     (boolean_t)(((uint8_t *)(Address))[0] & ((uint8_t)0x01))
 653
 654 /*
 655  * Check whether an address is broadcast.
 656  */
 657 #define IS_BROADCAST(Address)               \
 658     ((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && (((uint8_t *)(Address))[1] == ((uint8_t)0xff)))
 659
 660 /* Flow control parameters */
 661 struct ixgb_fc {
 662         uint32_t high_water;    /* Flow Control High-water          */
 663         uint32_t low_water;     /* Flow Control Low-water           */
 664         uint16_t pause_time;    /* Flow Control Pause timer         */
 665         boolean_t send_xon;     /* Flow control send XON            */
 666         ixgb_fc_type type;      /* Type of flow control             */
 667 };
 668
 669 /* The historical defaults for the flow control values are given below. */
 670 #define FC_DEFAULT_HI_THRESH        (0x8000)    /* 32KB */
 671 #define FC_DEFAULT_LO_THRESH        (0x4000)    /* 16KB */
 672 #define FC_DEFAULT_TX_TIMER         (0x100)     /* ~130 us */
 673
 674 /* Phy definitions */
 675 #define IXGB_MAX_PHY_REG_ADDRESS    0xFFFF
 676 #define IXGB_MAX_PHY_ADDRESS        31
 677 #define IXGB_MAX_PHY_DEV_TYPE       31
 678
 679 /* Bus parameters */
 680 struct ixgb_bus {
 681         ixgb_bus_speed speed;
 682         ixgb_bus_width width;
 683         ixgb_bus_type type;
 684 };
 685
 686 struct ixgb_hw {
 687         uint8_t __iomem *hw_addr;/* Base Address of the hardware     */
 688         void *back;             /* Pointer to OS-dependent struct   */
 689         struct ixgb_fc fc;      /* Flow control parameters          */
 690         struct ixgb_bus bus;    /* Bus parameters                   */
 691         uint32_t phy_id;        /* Phy Identifier                   */
 692         uint32_t phy_addr;      /* XGMII address of Phy             */
 693         ixgb_mac_type mac_type; /* Identifier for MAC controller    */
 694         ixgb_phy_type phy_type; /* Transceiver/phy identifier       */
 695         uint32_t max_frame_size;        /* Maximum frame size supported     */
 696         uint32_t mc_filter_type;        /* Multicast filter hash type       */
 697         uint32_t num_mc_addrs;  /* Number of current Multicast addrs */
 698         uint8_t curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS];      /* Individual address currently programmed in MAC */
 699         uint32_t num_tx_desc;   /* Number of Transmit descriptors   */
 700         uint32_t num_rx_desc;   /* Number of Receive descriptors    */
 701         uint32_t rx_buffer_size;        /* Size of Receive buffer           */
 702         boolean_t link_up;      /* TRUE if link is valid            */
 703         boolean_t adapter_stopped;      /* State of adapter                 */
 704         uint16_t device_id;     /* device id from PCI configuration space */
 705         uint16_t vendor_id;     /* vendor id from PCI configuration space */
 706         uint8_t revision_id;    /* revision id from PCI configuration space */
 707         uint16_t subsystem_vendor_id;   /* subsystem vendor id from PCI configuration space */
 708         uint16_t subsystem_id;  /* subsystem id from PCI configuration space */
 709         uint32_t bar0;          /* Base Address registers           */
 710         uint32_t bar1;
 711         uint32_t bar2;
 712         uint32_t bar3;
 713         uint16_t pci_cmd_word;  /* PCI command register id from PCI configuration space */
 714         uint16_t eeprom[IXGB_EEPROM_SIZE];      /* EEPROM contents read at init time  */
 715         unsigned long io_base;  /* Our I/O mapped location */
 716         uint32_t lastLFC;
 717         uint32_t lastRFC;
 718 };
 719
 720 /* Statistics reported by the hardware */
 721 struct ixgb_hw_stats {
 722         uint64_t tprl;
 723         uint64_t tprh;
 724         uint64_t gprcl;
 725         uint64_t gprch;
 726         uint64_t bprcl;
 727         uint64_t bprch;
 728         uint64_t mprcl;
 729         uint64_t mprch;
 730         uint64_t uprcl;
 731         uint64_t uprch;
 732         uint64_t vprcl;
 733         uint64_t vprch;
 734         uint64_t jprcl;
 735         uint64_t jprch;
 736         uint64_t gorcl;
 737         uint64_t gorch;
 738         uint64_t torl;
 739         uint64_t torh;
 740         uint64_t rnbc;
 741         uint64_t ruc;
 742         uint64_t roc;
 743         uint64_t rlec;
 744         uint64_t crcerrs;
 745         uint64_t icbc;
 746         uint64_t ecbc;
 747         uint64_t mpc;
 748         uint64_t tptl;
 749         uint64_t tpth;
 750         uint64_t gptcl;
 751         uint64_t gptch;
 752         uint64_t bptcl;
 753         uint64_t bptch;
 754         uint64_t mptcl;
 755         uint64_t mptch;
 756         uint64_t uptcl;
 757         uint64_t uptch;
 758         uint64_t vptcl;
 759         uint64_t vptch;
 760         uint64_t jptcl;
 761         uint64_t jptch;
 762         uint64_t gotcl;
 763         uint64_t gotch;
 764         uint64_t totl;
 765         uint64_t toth;
 766         uint64_t dc;
 767         uint64_t plt64c;
 768         uint64_t tsctc;
 769         uint64_t tsctfc;
 770         uint64_t ibic;
 771         uint64_t rfc;
 772         uint64_t lfc;
 773         uint64_t pfrc;
 774         uint64_t pftc;
 775         uint64_t mcfrc;
 776         uint64_t mcftc;
 777         uint64_t xonrxc;
 778         uint64_t xontxc;
 779         uint64_t xoffrxc;
 780         uint64_t xofftxc;
 781         uint64_t rjc;
 782 };
 783
 784 /* Function Prototypes */
 785 extern boolean_t ixgb_adapter_stop(struct ixgb_hw *hw);
 786 extern boolean_t ixgb_init_hw(struct ixgb_hw *hw);
 787 extern boolean_t ixgb_adapter_start(struct ixgb_hw *hw);
 788 extern void ixgb_check_for_link(struct ixgb_hw *hw);
 789 extern boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw);
 790
 791 extern void ixgb_rar_set(struct ixgb_hw *hw,
 792                                 uint8_t *addr,
 793                                 uint32_t index);
 794
 795
 796 /* Filters (multicast, vlan, receive) */
 797 extern void ixgb_mc_addr_list_update(struct ixgb_hw *hw,
 798                                    uint8_t *mc_addr_list,
 799                                    uint32_t mc_addr_count,
 800                                    uint32_t pad);
 801
 802 /* Vfta functions */
 803 extern void ixgb_write_vfta(struct ixgb_hw *hw,
 804                                  uint32_t offset,
 805                                  uint32_t value);
 806
 807 /* Access functions to eeprom data */
 808 void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr);
 809 uint32_t ixgb_get_ee_pba_number(struct ixgb_hw *hw);
 810 uint16_t ixgb_get_ee_device_id(struct ixgb_hw *hw);
 811 boolean_t ixgb_get_eeprom_data(struct ixgb_hw *hw);
 812 uint16_t ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index);
 813
 814 /* Everything else */
 815 void ixgb_led_on(struct ixgb_hw *hw);
 816 void ixgb_led_off(struct ixgb_hw *hw);
 817 void ixgb_write_pci_cfg(struct ixgb_hw *hw,
 818                          uint32_t reg,
 819                          uint16_t * value);
 820
 821
 822 #endif /* _IXGB_HW_H_ */