drivers/char/mbcs.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (c) 2005 Silicon Graphics, Inc.  All rights reserved.
   7  */
   8
   9 /*
  10  *      MOATB Core Services driver.
  11  */
  12
  13 #include <linux/interrupt.h>
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/types.h>
  17 #include <linux/ioport.h>
  18 #include <linux/notifier.h>
  19 #include <linux/reboot.h>
  20 #include <linux/init.h>
  21 #include <linux/fs.h>
  22 #include <linux/delay.h>
  23 #include <linux/device.h>
  24 #include <linux/mm.h>
  25 #include <linux/uio.h>
  26 #include <asm/io.h>
  27 #include <asm/uaccess.h>
  28 #include <asm/system.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/sn/addrs.h>
  31 #include <asm/sn/intr.h>
  32 #include <asm/sn/tiocx.h>
  33 #include "mbcs.h"
  34
  35 #define MBCS_DEBUG 0
  36 #if MBCS_DEBUG
  37 #define DBG(fmt...)    printk(KERN_ALERT fmt)
  38 #else
  39 #define DBG(fmt...)
  40 #endif
  41 int mbcs_major;
  42
  43 LIST_HEAD(soft_list);
  44
  45 /*
  46  * file operations
  47  */
  48 struct file_operations mbcs_ops = {
  49         .open = mbcs_open,
  50         .llseek = mbcs_sram_llseek,
  51         .read = mbcs_sram_read,
  52         .write = mbcs_sram_write,
  53         .mmap = mbcs_gscr_mmap,
  54 };
  55
  56 struct mbcs_callback_arg {
  57         int minor;
  58         struct cx_dev *cx_dev;
  59 };
  60
  61 static inline void mbcs_getdma_init(struct getdma *gdma)
  62 {
  63         memset(gdma, 0, sizeof(struct getdma));
  64         gdma->DoneIntEnable = 1;
  65 }
  66
  67 static inline void mbcs_putdma_init(struct putdma *pdma)
  68 {
  69         memset(pdma, 0, sizeof(struct putdma));
  70         pdma->DoneIntEnable = 1;
  71 }
  72
  73 static inline void mbcs_algo_init(struct algoblock *algo_soft)
  74 {
  75         memset(algo_soft, 0, sizeof(struct algoblock));
  76 }
  77
  78 static inline void mbcs_getdma_set(void *mmr,
  79                        uint64_t hostAddr,
  80                        uint64_t localAddr,
  81                        uint64_t localRamSel,
  82                        uint64_t numPkts,
  83                        uint64_t amoEnable,
  84                        uint64_t intrEnable,
  85                        uint64_t peerIO,
  86                        uint64_t amoHostDest,
  87                        uint64_t amoModType, uint64_t intrHostDest,
  88                        uint64_t intrVector)
  89 {
  90         union dma_control rdma_control;
  91         union dma_amo_dest amo_dest;
  92         union intr_dest intr_dest;
  93         union dma_localaddr local_addr;
  94         union dma_hostaddr host_addr;
  95
  96         rdma_control.dma_control_reg = 0;
  97         amo_dest.dma_amo_dest_reg = 0;
  98         intr_dest.intr_dest_reg = 0;
  99         local_addr.dma_localaddr_reg = 0;
 100         host_addr.dma_hostaddr_reg = 0;
 101
 102         host_addr.dma_sys_addr = hostAddr;
 103         MBCS_MMR_SET(mmr, MBCS_RD_DMA_SYS_ADDR, host_addr.dma_hostaddr_reg);
 104
 105         local_addr.dma_ram_addr = localAddr;
 106         local_addr.dma_ram_sel = localRamSel;
 107         MBCS_MMR_SET(mmr, MBCS_RD_DMA_LOC_ADDR, local_addr.dma_localaddr_reg);
 108
 109         rdma_control.dma_op_length = numPkts;
 110         rdma_control.done_amo_en = amoEnable;
 111         rdma_control.done_int_en = intrEnable;
 112         rdma_control.pio_mem_n = peerIO;
 113         MBCS_MMR_SET(mmr, MBCS_RD_DMA_CTRL, rdma_control.dma_control_reg);
 114
 115         amo_dest.dma_amo_sys_addr = amoHostDest;
 116         amo_dest.dma_amo_mod_type = amoModType;
 117         MBCS_MMR_SET(mmr, MBCS_RD_DMA_AMO_DEST, amo_dest.dma_amo_dest_reg);
 118
 119         intr_dest.address = intrHostDest;
 120         intr_dest.int_vector = intrVector;
 121         MBCS_MMR_SET(mmr, MBCS_RD_DMA_INT_DEST, intr_dest.intr_dest_reg);
 122
 123 }
 124
 125 static inline void mbcs_putdma_set(void *mmr,
 126                        uint64_t hostAddr,
 127                        uint64_t localAddr,
 128                        uint64_t localRamSel,
 129                        uint64_t numPkts,
 130                        uint64_t amoEnable,
 131                        uint64_t intrEnable,
 132                        uint64_t peerIO,
 133                        uint64_t amoHostDest,
 134                        uint64_t amoModType,
 135                        uint64_t intrHostDest, uint64_t intrVector)
 136 {
 137         union dma_control wdma_control;
 138         union dma_amo_dest amo_dest;
 139         union intr_dest intr_dest;
 140         union dma_localaddr local_addr;
 141         union dma_hostaddr host_addr;
 142
 143         wdma_control.dma_control_reg = 0;
 144         amo_dest.dma_amo_dest_reg = 0;
 145         intr_dest.intr_dest_reg = 0;
 146         local_addr.dma_localaddr_reg = 0;
 147         host_addr.dma_hostaddr_reg = 0;
 148
 149         host_addr.dma_sys_addr = hostAddr;
 150         MBCS_MMR_SET(mmr, MBCS_WR_DMA_SYS_ADDR, host_addr.dma_hostaddr_reg);
 151
 152         local_addr.dma_ram_addr = localAddr;
 153         local_addr.dma_ram_sel = localRamSel;
 154         MBCS_MMR_SET(mmr, MBCS_WR_DMA_LOC_ADDR, local_addr.dma_localaddr_reg);
 155
 156         wdma_control.dma_op_length = numPkts;
 157         wdma_control.done_amo_en = amoEnable;
 158         wdma_control.done_int_en = intrEnable;
 159         wdma_control.pio_mem_n = peerIO;
 160         MBCS_MMR_SET(mmr, MBCS_WR_DMA_CTRL, wdma_control.dma_control_reg);
 161
 162         amo_dest.dma_amo_sys_addr = amoHostDest;
 163         amo_dest.dma_amo_mod_type = amoModType;
 164         MBCS_MMR_SET(mmr, MBCS_WR_DMA_AMO_DEST, amo_dest.dma_amo_dest_reg);
 165
 166         intr_dest.address = intrHostDest;
 167         intr_dest.int_vector = intrVector;
 168         MBCS_MMR_SET(mmr, MBCS_WR_DMA_INT_DEST, intr_dest.intr_dest_reg);
 169
 170 }
 171
 172 static inline void mbcs_algo_set(void *mmr,
 173                      uint64_t amoHostDest,
 174                      uint64_t amoModType,
 175                      uint64_t intrHostDest,
 176                      uint64_t intrVector, uint64_t algoStepCount)
 177 {
 178         union dma_amo_dest amo_dest;
 179         union intr_dest intr_dest;
 180         union algo_step step;
 181
 182         step.algo_step_reg = 0;
 183         intr_dest.intr_dest_reg = 0;
 184         amo_dest.dma_amo_dest_reg = 0;
 185
 186         amo_dest.dma_amo_sys_addr = amoHostDest;
 187         amo_dest.dma_amo_mod_type = amoModType;
 188         MBCS_MMR_SET(mmr, MBCS_ALG_AMO_DEST, amo_dest.dma_amo_dest_reg);
 189
 190         intr_dest.address = intrHostDest;
 191         intr_dest.int_vector = intrVector;
 192         MBCS_MMR_SET(mmr, MBCS_ALG_INT_DEST, intr_dest.intr_dest_reg);
 193
 194         step.alg_step_cnt = algoStepCount;
 195         MBCS_MMR_SET(mmr, MBCS_ALG_STEP, step.algo_step_reg);
 196 }
 197
 198 static inline int mbcs_getdma_start(struct mbcs_soft *soft)
 199 {
 200         void *mmr_base;
 201         struct getdma *gdma;
 202         uint64_t numPkts;
 203         union cm_control cm_control;
 204
 205         mmr_base = soft->mmr_base;
 206         gdma = &soft->getdma;
 207
 208         /* check that host address got setup */
 209         if (!gdma->hostAddr)
 210                 return -1;
 211
 212         numPkts =
 213             (gdma->bytes + (MBCS_CACHELINE_SIZE - 1)) / MBCS_CACHELINE_SIZE;
 214
 215         /* program engine */
 216         mbcs_getdma_set(mmr_base, tiocx_dma_addr(gdma->hostAddr),
 217                    gdma->localAddr,
 218                    (gdma->localAddr < MB2) ? 0 :
 219                    (gdma->localAddr < MB4) ? 1 :
 220                    (gdma->localAddr < MB6) ? 2 : 3,
 221                    numPkts,
 222                    gdma->DoneAmoEnable,
 223                    gdma->DoneIntEnable,
 224                    gdma->peerIO,
 225                    gdma->amoHostDest,
 226                    gdma->amoModType,
 227                    gdma->intrHostDest, gdma->intrVector);
 228
 229         /* start engine */
 230         cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
 231         cm_control.rd_dma_go = 1;
 232         MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
 233
 234         return 0;
 235
 236 }
 237
 238 static inline int mbcs_putdma_start(struct mbcs_soft *soft)
 239 {
 240         void *mmr_base;
 241         struct putdma *pdma;
 242         uint64_t numPkts;
 243         union cm_control cm_control;
 244
 245         mmr_base = soft->mmr_base;
 246         pdma = &soft->putdma;
 247
 248         /* check that host address got setup */
 249         if (!pdma->hostAddr)
 250                 return -1;
 251
 252         numPkts =
 253             (pdma->bytes + (MBCS_CACHELINE_SIZE - 1)) / MBCS_CACHELINE_SIZE;
 254
 255         /* program engine */
 256         mbcs_putdma_set(mmr_base, tiocx_dma_addr(pdma->hostAddr),
 257                    pdma->localAddr,
 258                    (pdma->localAddr < MB2) ? 0 :
 259                    (pdma->localAddr < MB4) ? 1 :
 260                    (pdma->localAddr < MB6) ? 2 : 3,
 261                    numPkts,
 262                    pdma->DoneAmoEnable,
 263                    pdma->DoneIntEnable,
 264                    pdma->peerIO,
 265                    pdma->amoHostDest,
 266                    pdma->amoModType,
 267                    pdma->intrHostDest, pdma->intrVector);
 268
 269         /* start engine */
 270         cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
 271         cm_control.wr_dma_go = 1;
 272         MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
 273
 274         return 0;
 275
 276 }
 277
 278 static inline int mbcs_algo_start(struct mbcs_soft *soft)
 279 {
 280         struct algoblock *algo_soft = &soft->algo;
 281         void *mmr_base = soft->mmr_base;
 282         union cm_control cm_control;
 283
 284         if (down_interruptible(&soft->algolock))
 285                 return -ERESTARTSYS;
 286
 287         atomic_set(&soft->algo_done, 0);
 288
 289         mbcs_algo_set(mmr_base,
 290                  algo_soft->amoHostDest,
 291                  algo_soft->amoModType,
 292                  algo_soft->intrHostDest,
 293                  algo_soft->intrVector, algo_soft->algoStepCount);
 294
 295         /* start algorithm */
 296         cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
 297         cm_control.alg_done_int_en = 1;
 298         cm_control.alg_go = 1;
 299         MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
 300
 301         up(&soft->algolock);
 302
 303         return 0;
 304 }
 305
 306 static inline ssize_t
 307 do_mbcs_sram_dmawrite(struct mbcs_soft *soft, uint64_t hostAddr,
 308                       size_t len, loff_t * off)
 309 {
 310         int rv = 0;
 311
 312         if (down_interruptible(&soft->dmawritelock))
 313                 return -ERESTARTSYS;
 314
 315         atomic_set(&soft->dmawrite_done, 0);
 316
 317         soft->putdma.hostAddr = hostAddr;
 318         soft->putdma.localAddr = *off;
 319         soft->putdma.bytes = len;
 320
 321         if (mbcs_putdma_start(soft) < 0) {
 322                 DBG(KERN_ALERT "do_mbcs_sram_dmawrite: "
 323                                         "mbcs_putdma_start failed\n");
 324                 rv = -EAGAIN;
 325                 goto dmawrite_exit;
 326         }
 327
 328         if (wait_event_interruptible(soft->dmawrite_queue,
 329                                         atomic_read(&soft->dmawrite_done))) {
 330                 rv = -ERESTARTSYS;
 331                 goto dmawrite_exit;
 332         }
 333
 334         rv = len;
 335         *off += len;
 336
 337 dmawrite_exit:
 338         up(&soft->dmawritelock);
 339
 340         return rv;
 341 }
 342
 343 static inline ssize_t
 344 do_mbcs_sram_dmaread(struct mbcs_soft *soft, uint64_t hostAddr,
 345                      size_t len, loff_t * off)
 346 {
 347         int rv = 0;
 348
 349         if (down_interruptible(&soft->dmareadlock))
 350                 return -ERESTARTSYS;
 351
 352         atomic_set(&soft->dmawrite_done, 0);
 353
 354         soft->getdma.hostAddr = hostAddr;
 355         soft->getdma.localAddr = *off;
 356         soft->getdma.bytes = len;
 357
 358         if (mbcs_getdma_start(soft) < 0) {
 359                 DBG(KERN_ALERT "mbcs_strategy: mbcs_getdma_start failed\n");
 360                 rv = -EAGAIN;
 361                 goto dmaread_exit;
 362         }
 363
 364         if (wait_event_interruptible(soft->dmaread_queue,
 365                                         atomic_read(&soft->dmaread_done))) {
 366                 rv = -ERESTARTSYS;
 367                 goto dmaread_exit;
 368         }
 369
 370         rv = len;
 371         *off += len;
 372
 373 dmaread_exit:
 374         up(&soft->dmareadlock);
 375
 376         return rv;
 377 }
 378
 379 int mbcs_open(struct inode *ip, struct file *fp)
 380 {
 381         struct mbcs_soft *soft;
 382         int minor;
 383
 384         minor = iminor(ip);
 385
 386         list_for_each_entry(soft, &soft_list, list) {
 387                 if (soft->nasid == minor) {
 388                         fp->private_data = soft->cxdev;
 389                         return 0;
 390                 }
 391         }
 392
 393         return -ENODEV;
 394 }
 395
 396 ssize_t mbcs_sram_read(struct file * fp, char __user *buf, size_t len, loff_t * off)
 397 {
 398         struct cx_dev *cx_dev = fp->private_data;
 399         struct mbcs_soft *soft = cx_dev->soft;
 400         uint64_t hostAddr;
 401         int rv = 0;
 402
 403         hostAddr = __get_dma_pages(GFP_KERNEL, get_order(len));
 404         if (hostAddr == 0)
 405                 return -ENOMEM;
 406
 407         rv = do_mbcs_sram_dmawrite(soft, hostAddr, len, off);
 408         if (rv < 0)
 409                 goto exit;
 410
 411         if (copy_to_user(buf, (void *)hostAddr, len))
 412                 rv = -EFAULT;
 413
 414       exit:
 415         free_pages(hostAddr, get_order(len));
 416
 417         return rv;
 418 }
 419
 420 ssize_t
 421 mbcs_sram_write(struct file * fp, const char __user *buf, size_t len, loff_t * off)
 422 {
 423         struct cx_dev *cx_dev = fp->private_data;
 424         struct mbcs_soft *soft = cx_dev->soft;
 425         uint64_t hostAddr;
 426         int rv = 0;
 427
 428         hostAddr = __get_dma_pages(GFP_KERNEL, get_order(len));
 429         if (hostAddr == 0)
 430                 return -ENOMEM;
 431
 432         if (copy_from_user((void *)hostAddr, buf, len)) {
 433                 rv = -EFAULT;
 434                 goto exit;
 435         }
 436
 437         rv = do_mbcs_sram_dmaread(soft, hostAddr, len, off);
 438
 439       exit:
 440         free_pages(hostAddr, get_order(len));
 441
 442         return rv;
 443 }
 444
 445 loff_t mbcs_sram_llseek(struct file * filp, loff_t off, int whence)
 446 {
 447         loff_t newpos;
 448
 449         switch (whence) {
 450         case 0:         /* SEEK_SET */
 451                 newpos = off;
 452                 break;
 453
 454         case 1:         /* SEEK_CUR */
 455                 newpos = filp->f_pos + off;
 456                 break;
 457
 458         case 2:         /* SEEK_END */
 459                 newpos = MBCS_SRAM_SIZE + off;
 460                 break;
 461
 462         default:                /* can't happen */
 463                 return -EINVAL;
 464         }
 465
 466         if (newpos < 0)
 467                 return -EINVAL;
 468
 469         filp->f_pos = newpos;
 470
 471         return newpos;
 472 }
 473
 474 static uint64_t mbcs_pioaddr(struct mbcs_soft *soft, uint64_t offset)
 475 {
 476         uint64_t mmr_base;
 477
 478         mmr_base = (uint64_t) (soft->mmr_base + offset);
 479
 480         return mmr_base;
 481 }
 482
 483 static void mbcs_debug_pioaddr_set(struct mbcs_soft *soft)
 484 {
 485         soft->debug_addr = mbcs_pioaddr(soft, MBCS_DEBUG_START);
 486 }
 487
 488 static void mbcs_gscr_pioaddr_set(struct mbcs_soft *soft)
 489 {
 490         soft->gscr_addr = mbcs_pioaddr(soft, MBCS_GSCR_START);
 491 }
 492
 493 int mbcs_gscr_mmap(struct file *fp, struct vm_area_struct *vma)
 494 {
 495         struct cx_dev *cx_dev = fp->private_data;
 496         struct mbcs_soft *soft = cx_dev->soft;
 497
 498         if (vma->vm_pgoff != 0)
 499                 return -EINVAL;
 500
 501         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 502
 503         /* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */
 504         if (remap_pfn_range(vma,
 505                             vma->vm_start,
 506                             __pa(soft->gscr_addr) >> PAGE_SHIFT,
 507                             PAGE_SIZE,
 508                             vma->vm_page_prot))
 509                 return -EAGAIN;
 510
 511         return 0;
 512 }
 513
 514 /**
 515  * mbcs_completion_intr_handler - Primary completion handler.
 516  * @irq: irq
 517  * @arg: soft struct for device
 518  * @ep: regs
 519  *
 520  */
 521 static irqreturn_t
 522 mbcs_completion_intr_handler(int irq, void *arg, struct pt_regs *ep)
 523 {
 524         struct mbcs_soft *soft = (struct mbcs_soft *)arg;
 525         void *mmr_base;
 526         union cm_status cm_status;
 527         union cm_control cm_control;
 528
 529         mmr_base = soft->mmr_base;
 530         cm_status.cm_status_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_STATUS);
 531
 532         if (cm_status.rd_dma_done) {
 533                 /* stop dma-read engine, clear status */
 534                 cm_control.cm_control_reg =
 535                     MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
 536                 cm_control.rd_dma_clr = 1;
 537                 MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
 538                              cm_control.cm_control_reg);
 539                 atomic_set(&soft->dmaread_done, 1);
 540                 wake_up(&soft->dmaread_queue);
 541         }
 542         if (cm_status.wr_dma_done) {
 543                 /* stop dma-write engine, clear status */
 544                 cm_control.cm_control_reg =
 545                     MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
 546                 cm_control.wr_dma_clr = 1;
 547                 MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
 548                              cm_control.cm_control_reg);
 549                 atomic_set(&soft->dmawrite_done, 1);
 550                 wake_up(&soft->dmawrite_queue);
 551         }
 552         if (cm_status.alg_done) {
 553                 /* clear status */
 554                 cm_control.cm_control_reg =
 555                     MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
 556                 cm_control.alg_done_clr = 1;
 557                 MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
 558                              cm_control.cm_control_reg);
 559                 atomic_set(&soft->algo_done, 1);
 560                 wake_up(&soft->algo_queue);
 561         }
 562
 563         return IRQ_HANDLED;
 564 }
 565
 566 /**
 567  * mbcs_intr_alloc - Allocate interrupts.
 568  * @dev: device pointer
 569  *
 570  */
 571 static int mbcs_intr_alloc(struct cx_dev *dev)
 572 {
 573         struct sn_irq_info *sn_irq;
 574         struct mbcs_soft *soft;
 575         struct getdma *getdma;
 576         struct putdma *putdma;
 577         struct algoblock *algo;
 578
 579         soft = dev->soft;
 580         getdma = &soft->getdma;
 581         putdma = &soft->putdma;
 582         algo = &soft->algo;
 583
 584         soft->get_sn_irq = NULL;
 585         soft->put_sn_irq = NULL;
 586         soft->algo_sn_irq = NULL;
 587
 588         sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1);
 589         if (sn_irq == NULL)
 590                 return -EAGAIN;
 591         soft->get_sn_irq = sn_irq;
 592         getdma->intrHostDest = sn_irq->irq_xtalkaddr;
 593         getdma->intrVector = sn_irq->irq_irq;
 594         if (request_irq(sn_irq->irq_irq,
 595                         (void *)mbcs_completion_intr_handler, IRQF_SHARED,
 596                         "MBCS get intr", (void *)soft)) {
 597                 tiocx_irq_free(soft->get_sn_irq);
 598                 return -EAGAIN;
 599         }
 600
 601         sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1);
 602         if (sn_irq == NULL) {
 603                 free_irq(soft->get_sn_irq->irq_irq, soft);
 604                 tiocx_irq_free(soft->get_sn_irq);
 605                 return -EAGAIN;
 606         }
 607         soft->put_sn_irq = sn_irq;
 608         putdma->intrHostDest = sn_irq->irq_xtalkaddr;
 609         putdma->intrVector = sn_irq->irq_irq;
 610         if (request_irq(sn_irq->irq_irq,
 611                         (void *)mbcs_completion_intr_handler, IRQF_SHARED,
 612                         "MBCS put intr", (void *)soft)) {
 613                 tiocx_irq_free(soft->put_sn_irq);
 614                 free_irq(soft->get_sn_irq->irq_irq, soft);
 615                 tiocx_irq_free(soft->get_sn_irq);
 616                 return -EAGAIN;
 617         }
 618
 619         sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1);
 620         if (sn_irq == NULL) {
 621                 free_irq(soft->put_sn_irq->irq_irq, soft);
 622                 tiocx_irq_free(soft->put_sn_irq);
 623                 free_irq(soft->get_sn_irq->irq_irq, soft);
 624                 tiocx_irq_free(soft->get_sn_irq);
 625                 return -EAGAIN;
 626         }
 627         soft->algo_sn_irq = sn_irq;
 628         algo->intrHostDest = sn_irq->irq_xtalkaddr;
 629         algo->intrVector = sn_irq->irq_irq;
 630         if (request_irq(sn_irq->irq_irq,
 631                         (void *)mbcs_completion_intr_handler, IRQF_SHARED,
 632                         "MBCS algo intr", (void *)soft)) {
 633                 tiocx_irq_free(soft->algo_sn_irq);
 634                 free_irq(soft->put_sn_irq->irq_irq, soft);
 635                 tiocx_irq_free(soft->put_sn_irq);
 636                 free_irq(soft->get_sn_irq->irq_irq, soft);
 637                 tiocx_irq_free(soft->get_sn_irq);
 638                 return -EAGAIN;
 639         }
 640
 641         return 0;
 642 }
 643
 644 /**
 645  * mbcs_intr_dealloc - Remove interrupts.
 646  * @dev: device pointer
 647  *
 648  */
 649 static void mbcs_intr_dealloc(struct cx_dev *dev)
 650 {
 651         struct mbcs_soft *soft;
 652
 653         soft = dev->soft;
 654
 655         free_irq(soft->get_sn_irq->irq_irq, soft);
 656         tiocx_irq_free(soft->get_sn_irq);
 657         free_irq(soft->put_sn_irq->irq_irq, soft);
 658         tiocx_irq_free(soft->put_sn_irq);
 659         free_irq(soft->algo_sn_irq->irq_irq, soft);
 660         tiocx_irq_free(soft->algo_sn_irq);
 661 }
 662
 663 static inline int mbcs_hw_init(struct mbcs_soft *soft)
 664 {
 665         void *mmr_base = soft->mmr_base;
 666         union cm_control cm_control;
 667         union cm_req_timeout cm_req_timeout;
 668         uint64_t err_stat;
 669
 670         cm_req_timeout.cm_req_timeout_reg =
 671             MBCS_MMR_GET(mmr_base, MBCS_CM_REQ_TOUT);
 672
 673         cm_req_timeout.time_out = MBCS_CM_CONTROL_REQ_TOUT_MASK;
 674         MBCS_MMR_SET(mmr_base, MBCS_CM_REQ_TOUT,
 675                      cm_req_timeout.cm_req_timeout_reg);
 676
 677         mbcs_gscr_pioaddr_set(soft);
 678         mbcs_debug_pioaddr_set(soft);
 679
 680         /* clear errors */
 681         err_stat = MBCS_MMR_GET(mmr_base, MBCS_CM_ERR_STAT);
 682         MBCS_MMR_SET(mmr_base, MBCS_CM_CLR_ERR_STAT, err_stat);
 683         MBCS_MMR_ZERO(mmr_base, MBCS_CM_ERROR_DETAIL1);
 684
 685         /* enable interrupts */
 686         /* turn off 2^23 (INT_EN_PIO_REQ_ADDR_INV) */
 687         MBCS_MMR_SET(mmr_base, MBCS_CM_ERR_INT_EN, 0x3ffffff7e00ffUL);
 688
 689         /* arm status regs and clear engines */
 690         cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
 691         cm_control.rearm_stat_regs = 1;
 692         cm_control.alg_clr = 1;
 693         cm_control.wr_dma_clr = 1;
 694         cm_control.rd_dma_clr = 1;
 695
 696         MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
 697
 698         return 0;
 699 }
 700
 701 static ssize_t show_algo(struct device *dev, struct device_attribute *attr, char *buf)
 702 {
 703         struct cx_dev *cx_dev = to_cx_dev(dev);
 704         struct mbcs_soft *soft = cx_dev->soft;
 705         uint64_t debug0;
 706
 707         /*
 708          * By convention, the first debug register contains the
 709          * algorithm number and revision.
 710          */
 711         debug0 = *(uint64_t *) soft->debug_addr;
 712
 713         return sprintf(buf, "0x%lx 0x%lx\n",
 714                        (debug0 >> 32), (debug0 & 0xffffffff));
 715 }
 716
 717 static ssize_t store_algo(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
 718 {
 719         int n;
 720         struct cx_dev *cx_dev = to_cx_dev(dev);
 721         struct mbcs_soft *soft = cx_dev->soft;
 722
 723         if (count <= 0)
 724                 return 0;
 725
 726         n = simple_strtoul(buf, NULL, 0);
 727
 728         if (n == 1) {
 729                 mbcs_algo_start(soft);
 730                 if (wait_event_interruptible(soft->algo_queue,
 731                                         atomic_read(&soft->algo_done)))
 732                         return -ERESTARTSYS;
 733         }
 734
 735         return count;
 736 }
 737
 738 DEVICE_ATTR(algo, 0644, show_algo, store_algo);
 739
 740 /**
 741  * mbcs_probe - Initialize for device
 742  * @dev: device pointer
 743  * @device_id: id table pointer
 744  *
 745  */
 746 static int mbcs_probe(struct cx_dev *dev, const struct cx_device_id *id)
 747 {
 748         struct mbcs_soft *soft;
 749
 750         dev->soft = NULL;
 751
 752         soft = kzalloc(sizeof(struct mbcs_soft), GFP_KERNEL);
 753         if (soft == NULL)
 754                 return -ENOMEM;
 755
 756         soft->nasid = dev->cx_id.nasid;
 757         list_add(&soft->list, &soft_list);
 758         soft->mmr_base = (void *)tiocx_swin_base(dev->cx_id.nasid);
 759         dev->soft = soft;
 760         soft->cxdev = dev;
 761
 762         init_waitqueue_head(&soft->dmawrite_queue);
 763         init_waitqueue_head(&soft->dmaread_queue);
 764         init_waitqueue_head(&soft->algo_queue);
 765
 766         init_MUTEX(&soft->dmawritelock);
 767         init_MUTEX(&soft->dmareadlock);
 768         init_MUTEX(&soft->algolock);
 769
 770         mbcs_getdma_init(&soft->getdma);
 771         mbcs_putdma_init(&soft->putdma);
 772         mbcs_algo_init(&soft->algo);
 773
 774         mbcs_hw_init(soft);
 775
 776         /* Allocate interrupts */
 777         mbcs_intr_alloc(dev);
 778
 779         device_create_file(&dev->dev, &dev_attr_algo);
 780
 781         return 0;
 782 }
 783
 784 static int mbcs_remove(struct cx_dev *dev)
 785 {
 786         if (dev->soft) {
 787                 mbcs_intr_dealloc(dev);
 788                 kfree(dev->soft);
 789         }
 790
 791         device_remove_file(&dev->dev, &dev_attr_algo);
 792
 793         return 0;
 794 }
 795
 796 const struct cx_device_id __devinitdata mbcs_id_table[] = {
 797         {
 798          .part_num = MBCS_PART_NUM,
 799          .mfg_num = MBCS_MFG_NUM,
 800          },
 801         {
 802          .part_num = MBCS_PART_NUM_ALG0,
 803          .mfg_num = MBCS_MFG_NUM,
 804          },
 805         {0, 0}
 806 };
 807
 808 MODULE_DEVICE_TABLE(cx, mbcs_id_table);
 809
 810 struct cx_drv mbcs_driver = {
 811         .name = DEVICE_NAME,
 812         .id_table = mbcs_id_table,
 813         .probe = mbcs_probe,
 814         .remove = mbcs_remove,
 815 };
 816
 817 static void __exit mbcs_exit(void)
 818 {
 819         int rv;
 820
 821         rv = unregister_chrdev(mbcs_major, DEVICE_NAME);
 822         if (rv < 0)
 823                 DBG(KERN_ALERT "Error in unregister_chrdev: %d\n", rv);
 824
 825         cx_driver_unregister(&mbcs_driver);
 826 }
 827
 828 static int __init mbcs_init(void)
 829 {
 830         int rv;
 831
 832         if (!ia64_platform_is("sn2"))
 833                 return -ENODEV;
 834
 835         // Put driver into chrdevs[].  Get major number.
 836         rv = register_chrdev(mbcs_major, DEVICE_NAME, &mbcs_ops);
 837         if (rv < 0) {
 838                 DBG(KERN_ALERT "mbcs_init: can't get major number. %d\n", rv);
 839                 return rv;
 840         }
 841         mbcs_major = rv;
 842
 843         return cx_driver_register(&mbcs_driver);
 844 }
 845
 846 module_init(mbcs_init);
 847 module_exit(mbcs_exit);
 848
 849 MODULE_AUTHOR("Bruce Losure <blosure@sgi.com>");
 850 MODULE_DESCRIPTION("Driver for MOATB Core Services");
 851 MODULE_LICENSE("GPL");