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[PATCH] mem driver: fix conditional on isa i/o support
[linux-2.6.22.y-op.git] / drivers / char / drm / radeon_drv.h
blobe5a256f5429c81c504d1ec15086caea2489c67cb
1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
33
34 /* General customization:
35 */
36
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20060524"
42
43 /* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading).
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
98 */
99 #define DRIVER_MAJOR 1
100 #define DRIVER_MINOR 25
101 #define DRIVER_PATCHLEVEL 0
102
103 /*
104 * Radeon chip families
105 */
106 enum radeon_family {
107 CHIP_R100,
108 CHIP_RV100,
109 CHIP_RS100,
110 CHIP_RV200,
111 CHIP_RS200,
112 CHIP_R200,
113 CHIP_RV250,
114 CHIP_RS300,
115 CHIP_RV280,
116 CHIP_R300,
117 CHIP_R350,
118 CHIP_RV350,
119 CHIP_RV380,
120 CHIP_R420,
121 CHIP_RV410,
122 CHIP_RS400,
123 CHIP_LAST,
124 };
125
126 enum radeon_cp_microcode_version {
127 UCODE_R100,
128 UCODE_R200,
129 UCODE_R300,
130 };
131
132 /*
133 * Chip flags
134 */
135 enum radeon_chip_flags {
136 CHIP_FAMILY_MASK = 0x0000ffffUL,
137 CHIP_FLAGS_MASK = 0xffff0000UL,
138 CHIP_IS_MOBILITY = 0x00010000UL,
139 CHIP_IS_IGP = 0x00020000UL,
140 CHIP_SINGLE_CRTC = 0x00040000UL,
141 CHIP_IS_AGP = 0x00080000UL,
142 CHIP_HAS_HIERZ = 0x00100000UL,
143 CHIP_IS_PCIE = 0x00200000UL,
144 CHIP_NEW_MEMMAP = 0x00400000UL,
145 };
146
147 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
148 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
149 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
150
151 typedef struct drm_radeon_freelist {
152 unsigned int age;
153 drm_buf_t *buf;
154 struct drm_radeon_freelist *next;
155 struct drm_radeon_freelist *prev;
156 } drm_radeon_freelist_t;
157
158 typedef struct drm_radeon_ring_buffer {
159 u32 *start;
160 u32 *end;
161 int size;
162 int size_l2qw;
163
164 u32 tail;
165 u32 tail_mask;
166 int space;
167
168 int high_mark;
169 } drm_radeon_ring_buffer_t;
170
171 typedef struct drm_radeon_depth_clear_t {
172 u32 rb3d_cntl;
173 u32 rb3d_zstencilcntl;
174 u32 se_cntl;
175 } drm_radeon_depth_clear_t;
176
177 struct drm_radeon_driver_file_fields {
178 int64_t radeon_fb_delta;
179 };
180
181 struct mem_block {
182 struct mem_block *next;
183 struct mem_block *prev;
184 int start;
185 int size;
186 DRMFILE filp; /* 0: free, -1: heap, other: real files */
187 };
188
189 struct radeon_surface {
190 int refcount;
191 u32 lower;
192 u32 upper;
193 u32 flags;
194 };
195
196 struct radeon_virt_surface {
197 int surface_index;
198 u32 lower;
199 u32 upper;
200 u32 flags;
201 DRMFILE filp;
202 };
203
204 typedef struct drm_radeon_private {
205 drm_radeon_ring_buffer_t ring;
206 drm_radeon_sarea_t *sarea_priv;
207
208 u32 fb_location;
209 u32 fb_size;
210 int new_memmap;
211
212 int gart_size;
213 u32 gart_vm_start;
214 unsigned long gart_buffers_offset;
215
216 int cp_mode;
217 int cp_running;
218
219 drm_radeon_freelist_t *head;
220 drm_radeon_freelist_t *tail;
221 int last_buf;
222 volatile u32 *scratch;
223 int writeback_works;
224
225 int usec_timeout;
226
227 int microcode_version;
228
229 struct {
230 u32 boxes;
231 int freelist_timeouts;
232 int freelist_loops;
233 int requested_bufs;
234 int last_frame_reads;
235 int last_clear_reads;
236 int clears;
237 int texture_uploads;
238 } stats;
239
240 int do_boxes;
241 int page_flipping;
242 int current_page;
243
244 u32 color_fmt;
245 unsigned int front_offset;
246 unsigned int front_pitch;
247 unsigned int back_offset;
248 unsigned int back_pitch;
249
250 u32 depth_fmt;
251 unsigned int depth_offset;
252 unsigned int depth_pitch;
253
254 u32 front_pitch_offset;
255 u32 back_pitch_offset;
256 u32 depth_pitch_offset;
257
258 drm_radeon_depth_clear_t depth_clear;
259
260 unsigned long ring_offset;
261 unsigned long ring_rptr_offset;
262 unsigned long buffers_offset;
263 unsigned long gart_textures_offset;
264
265 drm_local_map_t *sarea;
266 drm_local_map_t *mmio;
267 drm_local_map_t *cp_ring;
268 drm_local_map_t *ring_rptr;
269 drm_local_map_t *gart_textures;
270
271 struct mem_block *gart_heap;
272 struct mem_block *fb_heap;
273
274 /* SW interrupt */
275 wait_queue_head_t swi_queue;
276 atomic_t swi_emitted;
277
278 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
279 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
280
281 unsigned long pcigart_offset;
282 drm_ati_pcigart_info gart_info;
283
284 u32 scratch_ages[5];
285
286 /* starting from here on, data is preserved accross an open */
287 uint32_t flags; /* see radeon_chip_flags */
288 } drm_radeon_private_t;
289
290 typedef struct drm_radeon_buf_priv {
291 u32 age;
292 } drm_radeon_buf_priv_t;
293
294 typedef struct drm_radeon_kcmd_buffer {
295 int bufsz;
296 char *buf;
297 int nbox;
298 drm_clip_rect_t __user *boxes;
299 } drm_radeon_kcmd_buffer_t;
300
301 extern int radeon_no_wb;
302 extern drm_ioctl_desc_t radeon_ioctls[];
303 extern int radeon_max_ioctl;
304
305 /* radeon_cp.c */
306 extern int radeon_cp_init(DRM_IOCTL_ARGS);
307 extern int radeon_cp_start(DRM_IOCTL_ARGS);
308 extern int radeon_cp_stop(DRM_IOCTL_ARGS);
309 extern int radeon_cp_reset(DRM_IOCTL_ARGS);
310 extern int radeon_cp_idle(DRM_IOCTL_ARGS);
311 extern int radeon_cp_resume(DRM_IOCTL_ARGS);
312 extern int radeon_engine_reset(DRM_IOCTL_ARGS);
313 extern int radeon_fullscreen(DRM_IOCTL_ARGS);
314 extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
315
316 extern void radeon_freelist_reset(drm_device_t * dev);
317 extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
318
319 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
320
321 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
322
323 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
324 extern int radeon_presetup(struct drm_device *dev);
325 extern int radeon_driver_postcleanup(struct drm_device *dev);
326
327 extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
328 extern int radeon_mem_free(DRM_IOCTL_ARGS);
329 extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
330 extern void radeon_mem_takedown(struct mem_block **heap);
331 extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap);
332
333 /* radeon_irq.c */
334 extern int radeon_irq_emit(DRM_IOCTL_ARGS);
335 extern int radeon_irq_wait(DRM_IOCTL_ARGS);
336
337 extern void radeon_do_release(drm_device_t * dev);
338 extern int radeon_driver_vblank_wait(drm_device_t * dev,
339 unsigned int *sequence);
340 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
341 extern void radeon_driver_irq_preinstall(drm_device_t * dev);
342 extern void radeon_driver_irq_postinstall(drm_device_t * dev);
343 extern void radeon_driver_irq_uninstall(drm_device_t * dev);
344
345 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
346 extern int radeon_driver_unload(struct drm_device *dev);
347 extern int radeon_driver_firstopen(struct drm_device *dev);
348 extern void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp);
349 extern void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp);
350 extern void radeon_driver_lastclose(drm_device_t * dev);
351 extern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv);
352 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
353 unsigned long arg);
354
355 /* r300_cmdbuf.c */
356 extern void r300_init_reg_flags(void);
357
358 extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
359 drm_file_t * filp_priv,
360 drm_radeon_kcmd_buffer_t * cmdbuf);
361
362 /* Flags for stats.boxes
363 */
364 #define RADEON_BOX_DMA_IDLE 0x1
365 #define RADEON_BOX_RING_FULL 0x2
366 #define RADEON_BOX_FLIP 0x4
367 #define RADEON_BOX_WAIT_IDLE 0x8
368 #define RADEON_BOX_TEXTURE_LOAD 0x10
369
370 /* Register definitions, register access macros and drmAddMap constants
371 * for Radeon kernel driver.
372 */
373
374 #define RADEON_AGP_COMMAND 0x0f60
375 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
376 # define RADEON_AGP_ENABLE (1<<8)
377 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
378 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
379 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
380 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
381 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
382 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
383 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
384
385 #define RADEON_BUS_CNTL 0x0030
386 # define RADEON_BUS_MASTER_DIS (1 << 6)
387
388 #define RADEON_CLOCK_CNTL_DATA 0x000c
389 # define RADEON_PLL_WR_EN (1 << 7)
390 #define RADEON_CLOCK_CNTL_INDEX 0x0008
391 #define RADEON_CONFIG_APER_SIZE 0x0108
392 #define RADEON_CONFIG_MEMSIZE 0x00f8
393 #define RADEON_CRTC_OFFSET 0x0224
394 #define RADEON_CRTC_OFFSET_CNTL 0x0228
395 # define RADEON_CRTC_TILE_EN (1 << 15)
396 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
397 #define RADEON_CRTC2_OFFSET 0x0324
398 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
399
400 #define RADEON_PCIE_INDEX 0x0030
401 #define RADEON_PCIE_DATA 0x0034
402 #define RADEON_PCIE_TX_GART_CNTL 0x10
403 # define RADEON_PCIE_TX_GART_EN (1 << 0)
404 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
405 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
406 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
407 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
408 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
409 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
410 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
411 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
412 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
413 #define RADEON_PCIE_TX_GART_BASE 0x13
414 #define RADEON_PCIE_TX_GART_START_LO 0x14
415 #define RADEON_PCIE_TX_GART_START_HI 0x15
416 #define RADEON_PCIE_TX_GART_END_LO 0x16
417 #define RADEON_PCIE_TX_GART_END_HI 0x17
418
419 #define RADEON_MPP_TB_CONFIG 0x01c0
420 #define RADEON_MEM_CNTL 0x0140
421 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
422 #define RADEON_AGP_BASE 0x0170
423
424 #define RADEON_RB3D_COLOROFFSET 0x1c40
425 #define RADEON_RB3D_COLORPITCH 0x1c48
426
427 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
428 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
429 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
430 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
431 # define RADEON_GMC_BRUSH_NONE (15 << 4)
432 # define RADEON_GMC_DST_16BPP (4 << 8)
433 # define RADEON_GMC_DST_24BPP (5 << 8)
434 # define RADEON_GMC_DST_32BPP (6 << 8)
435 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
436 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
437 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
438 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
439 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
440 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
441 # define RADEON_ROP3_S 0x00cc0000
442 # define RADEON_ROP3_P 0x00f00000
443 #define RADEON_DP_WRITE_MASK 0x16cc
444 #define RADEON_DST_PITCH_OFFSET 0x142c
445 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
446 # define RADEON_DST_TILE_LINEAR (0 << 30)
447 # define RADEON_DST_TILE_MACRO (1 << 30)
448 # define RADEON_DST_TILE_MICRO (2 << 30)
449 # define RADEON_DST_TILE_BOTH (3 << 30)
450
451 #define RADEON_SCRATCH_REG0 0x15e0
452 #define RADEON_SCRATCH_REG1 0x15e4
453 #define RADEON_SCRATCH_REG2 0x15e8
454 #define RADEON_SCRATCH_REG3 0x15ec
455 #define RADEON_SCRATCH_REG4 0x15f0
456 #define RADEON_SCRATCH_REG5 0x15f4
457 #define RADEON_SCRATCH_UMSK 0x0770
458 #define RADEON_SCRATCH_ADDR 0x0774
459
460 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
461
462 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
463 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
464 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
465
466 #define RADEON_GEN_INT_CNTL 0x0040
467 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
468 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
469 # define RADEON_SW_INT_ENABLE (1 << 25)
470
471 #define RADEON_GEN_INT_STATUS 0x0044
472 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
473 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
474 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
475 # define RADEON_SW_INT_TEST (1 << 25)
476 # define RADEON_SW_INT_TEST_ACK (1 << 25)
477 # define RADEON_SW_INT_FIRE (1 << 26)
478
479 #define RADEON_HOST_PATH_CNTL 0x0130
480 # define RADEON_HDP_SOFT_RESET (1 << 26)
481 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
482 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
483
484 #define RADEON_ISYNC_CNTL 0x1724
485 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
486 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
487 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
488 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
489 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
490 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
491
492 #define RADEON_RBBM_GUICNTL 0x172c
493 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
494 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
495 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
496 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
497
498 #define RADEON_MC_AGP_LOCATION 0x014c
499 #define RADEON_MC_FB_LOCATION 0x0148
500 #define RADEON_MCLK_CNTL 0x0012
501 # define RADEON_FORCEON_MCLKA (1 << 16)
502 # define RADEON_FORCEON_MCLKB (1 << 17)
503 # define RADEON_FORCEON_YCLKA (1 << 18)
504 # define RADEON_FORCEON_YCLKB (1 << 19)
505 # define RADEON_FORCEON_MC (1 << 20)
506 # define RADEON_FORCEON_AIC (1 << 21)
507
508 #define RADEON_PP_BORDER_COLOR_0 0x1d40
509 #define RADEON_PP_BORDER_COLOR_1 0x1d44
510 #define RADEON_PP_BORDER_COLOR_2 0x1d48
511 #define RADEON_PP_CNTL 0x1c38
512 # define RADEON_SCISSOR_ENABLE (1 << 1)
513 #define RADEON_PP_LUM_MATRIX 0x1d00
514 #define RADEON_PP_MISC 0x1c14
515 #define RADEON_PP_ROT_MATRIX_0 0x1d58
516 #define RADEON_PP_TXFILTER_0 0x1c54
517 #define RADEON_PP_TXOFFSET_0 0x1c5c
518 #define RADEON_PP_TXFILTER_1 0x1c6c
519 #define RADEON_PP_TXFILTER_2 0x1c84
520
521 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
522 # define RADEON_RB2D_DC_FLUSH (3 << 0)
523 # define RADEON_RB2D_DC_FREE (3 << 2)
524 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
525 # define RADEON_RB2D_DC_BUSY (1 << 31)
526 #define RADEON_RB3D_CNTL 0x1c3c
527 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
528 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
529 # define RADEON_DITHER_ENABLE (1 << 2)
530 # define RADEON_ROUND_ENABLE (1 << 3)
531 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
532 # define RADEON_DITHER_INIT (1 << 5)
533 # define RADEON_ROP_ENABLE (1 << 6)
534 # define RADEON_STENCIL_ENABLE (1 << 7)
535 # define RADEON_Z_ENABLE (1 << 8)
536 # define RADEON_ZBLOCK16 (1 << 15)
537 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
538 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
539 #define RADEON_RB3D_DEPTHPITCH 0x1c28
540 #define RADEON_RB3D_PLANEMASK 0x1d84
541 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
542 #define RADEON_RB3D_ZCACHE_MODE 0x3250
543 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
544 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
545 # define RADEON_RB3D_ZC_FREE (1 << 2)
546 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
547 # define RADEON_RB3D_ZC_BUSY (1 << 31)
548 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
549 # define RADEON_Z_TEST_MASK (7 << 4)
550 # define RADEON_Z_TEST_ALWAYS (7 << 4)
551 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
552 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
553 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
554 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
555 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
556 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
557 # define RADEON_FORCE_Z_DIRTY (1 << 29)
558 # define RADEON_Z_WRITE_ENABLE (1 << 30)
559 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
560 #define RADEON_RBBM_SOFT_RESET 0x00f0
561 # define RADEON_SOFT_RESET_CP (1 << 0)
562 # define RADEON_SOFT_RESET_HI (1 << 1)
563 # define RADEON_SOFT_RESET_SE (1 << 2)
564 # define RADEON_SOFT_RESET_RE (1 << 3)
565 # define RADEON_SOFT_RESET_PP (1 << 4)
566 # define RADEON_SOFT_RESET_E2 (1 << 5)
567 # define RADEON_SOFT_RESET_RB (1 << 6)
568 # define RADEON_SOFT_RESET_HDP (1 << 7)
569 #define RADEON_RBBM_STATUS 0x0e40
570 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
571 # define RADEON_RBBM_ACTIVE (1 << 31)
572 #define RADEON_RE_LINE_PATTERN 0x1cd0
573 #define RADEON_RE_MISC 0x26c4
574 #define RADEON_RE_TOP_LEFT 0x26c0
575 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
576 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
577 #define RADEON_RE_STIPPLE_DATA 0x1ccc
578
579 #define RADEON_SCISSOR_TL_0 0x1cd8
580 #define RADEON_SCISSOR_BR_0 0x1cdc
581 #define RADEON_SCISSOR_TL_1 0x1ce0
582 #define RADEON_SCISSOR_BR_1 0x1ce4
583 #define RADEON_SCISSOR_TL_2 0x1ce8
584 #define RADEON_SCISSOR_BR_2 0x1cec
585 #define RADEON_SE_COORD_FMT 0x1c50
586 #define RADEON_SE_CNTL 0x1c4c
587 # define RADEON_FFACE_CULL_CW (0 << 0)
588 # define RADEON_BFACE_SOLID (3 << 1)
589 # define RADEON_FFACE_SOLID (3 << 3)
590 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
591 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
592 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
593 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
594 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
595 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
596 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
597 # define RADEON_FOG_SHADE_FLAT (1 << 14)
598 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
599 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
600 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
601 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
602 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
603 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
604 #define RADEON_SE_CNTL_STATUS 0x2140
605 #define RADEON_SE_LINE_WIDTH 0x1db8
606 #define RADEON_SE_VPORT_XSCALE 0x1d98
607 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
608 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
609 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
610 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
611 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
612 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
613 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
614 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
615 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
616 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
617 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
618 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
619 #define RADEON_SURFACE_CNTL 0x0b00
620 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
621 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
622 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
623 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
624 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
625 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
626 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
627 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
628 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
629 #define RADEON_SURFACE0_INFO 0x0b0c
630 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
631 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
632 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
633 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
634 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
635 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
636 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
637 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
638 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
639 #define RADEON_SURFACE1_INFO 0x0b1c
640 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
641 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
642 #define RADEON_SURFACE2_INFO 0x0b2c
643 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
644 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
645 #define RADEON_SURFACE3_INFO 0x0b3c
646 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
647 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
648 #define RADEON_SURFACE4_INFO 0x0b4c
649 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
650 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
651 #define RADEON_SURFACE5_INFO 0x0b5c
652 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
653 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
654 #define RADEON_SURFACE6_INFO 0x0b6c
655 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
656 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
657 #define RADEON_SURFACE7_INFO 0x0b7c
658 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
659 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
660 #define RADEON_SW_SEMAPHORE 0x013c
661
662 #define RADEON_WAIT_UNTIL 0x1720
663 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
664 # define RADEON_WAIT_2D_IDLE (1 << 14)
665 # define RADEON_WAIT_3D_IDLE (1 << 15)
666 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
667 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
668 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
669
670 #define RADEON_RB3D_ZMASKOFFSET 0x3234
671 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
672 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
673 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
674
675 /* CP registers */
676 #define RADEON_CP_ME_RAM_ADDR 0x07d4
677 #define RADEON_CP_ME_RAM_RADDR 0x07d8
678 #define RADEON_CP_ME_RAM_DATAH 0x07dc
679 #define RADEON_CP_ME_RAM_DATAL 0x07e0
680
681 #define RADEON_CP_RB_BASE 0x0700
682 #define RADEON_CP_RB_CNTL 0x0704
683 # define RADEON_BUF_SWAP_32BIT (2 << 16)
684 #define RADEON_CP_RB_RPTR_ADDR 0x070c
685 #define RADEON_CP_RB_RPTR 0x0710
686 #define RADEON_CP_RB_WPTR 0x0714
687
688 #define RADEON_CP_RB_WPTR_DELAY 0x0718
689 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
690 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
691
692 #define RADEON_CP_IB_BASE 0x0738
693
694 #define RADEON_CP_CSQ_CNTL 0x0740
695 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
696 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
697 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
698 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
699 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
700 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
701 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
702
703 #define RADEON_AIC_CNTL 0x01d0
704 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
705 #define RADEON_AIC_STAT 0x01d4
706 #define RADEON_AIC_PT_BASE 0x01d8
707 #define RADEON_AIC_LO_ADDR 0x01dc
708 #define RADEON_AIC_HI_ADDR 0x01e0
709 #define RADEON_AIC_TLB_ADDR 0x01e4
710 #define RADEON_AIC_TLB_DATA 0x01e8
711
712 /* CP command packets */
713 #define RADEON_CP_PACKET0 0x00000000
714 # define RADEON_ONE_REG_WR (1 << 15)
715 #define RADEON_CP_PACKET1 0x40000000
716 #define RADEON_CP_PACKET2 0x80000000
717 #define RADEON_CP_PACKET3 0xC0000000
718 # define RADEON_CP_NOP 0x00001000
719 # define RADEON_CP_NEXT_CHAR 0x00001900
720 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
721 # define RADEON_CP_SET_SCISSORS 0x00001E00
722 /* GEN_INDX_PRIM is unsupported starting with R300 */
723 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
724 # define RADEON_WAIT_FOR_IDLE 0x00002600
725 # define RADEON_3D_DRAW_VBUF 0x00002800
726 # define RADEON_3D_DRAW_IMMD 0x00002900
727 # define RADEON_3D_DRAW_INDX 0x00002A00
728 # define RADEON_CP_LOAD_PALETTE 0x00002C00
729 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
730 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
731 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
732 # define RADEON_3D_CLEAR_ZMASK 0x00003200
733 # define RADEON_CP_INDX_BUFFER 0x00003300
734 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
735 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
736 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
737 # define RADEON_3D_CLEAR_HIZ 0x00003700
738 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
739 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
740 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
741 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
742 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
743
744 #define RADEON_CP_PACKET_MASK 0xC0000000
745 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
746 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
747 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
748 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
749
750 #define RADEON_VTX_Z_PRESENT (1 << 31)
751 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
752
753 #define RADEON_PRIM_TYPE_NONE (0 << 0)
754 #define RADEON_PRIM_TYPE_POINT (1 << 0)
755 #define RADEON_PRIM_TYPE_LINE (2 << 0)
756 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
757 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
758 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
759 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
760 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
761 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
762 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
763 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
764 #define RADEON_PRIM_TYPE_MASK 0xf
765 #define RADEON_PRIM_WALK_IND (1 << 4)
766 #define RADEON_PRIM_WALK_LIST (2 << 4)
767 #define RADEON_PRIM_WALK_RING (3 << 4)
768 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
769 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
770 #define RADEON_MAOS_ENABLE (1 << 7)
771 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
772 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
773 #define RADEON_NUM_VERTICES_SHIFT 16
774
775 #define RADEON_COLOR_FORMAT_CI8 2
776 #define RADEON_COLOR_FORMAT_ARGB1555 3
777 #define RADEON_COLOR_FORMAT_RGB565 4
778 #define RADEON_COLOR_FORMAT_ARGB8888 6
779 #define RADEON_COLOR_FORMAT_RGB332 7
780 #define RADEON_COLOR_FORMAT_RGB8 9
781 #define RADEON_COLOR_FORMAT_ARGB4444 15
782
783 #define RADEON_TXFORMAT_I8 0
784 #define RADEON_TXFORMAT_AI88 1
785 #define RADEON_TXFORMAT_RGB332 2
786 #define RADEON_TXFORMAT_ARGB1555 3
787 #define RADEON_TXFORMAT_RGB565 4
788 #define RADEON_TXFORMAT_ARGB4444 5
789 #define RADEON_TXFORMAT_ARGB8888 6
790 #define RADEON_TXFORMAT_RGBA8888 7
791 #define RADEON_TXFORMAT_Y8 8
792 #define RADEON_TXFORMAT_VYUY422 10
793 #define RADEON_TXFORMAT_YVYU422 11
794 #define RADEON_TXFORMAT_DXT1 12
795 #define RADEON_TXFORMAT_DXT23 14
796 #define RADEON_TXFORMAT_DXT45 15
797
798 #define R200_PP_TXCBLEND_0 0x2f00
799 #define R200_PP_TXCBLEND_1 0x2f10
800 #define R200_PP_TXCBLEND_2 0x2f20
801 #define R200_PP_TXCBLEND_3 0x2f30
802 #define R200_PP_TXCBLEND_4 0x2f40
803 #define R200_PP_TXCBLEND_5 0x2f50
804 #define R200_PP_TXCBLEND_6 0x2f60
805 #define R200_PP_TXCBLEND_7 0x2f70
806 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
807 #define R200_PP_TFACTOR_0 0x2ee0
808 #define R200_SE_VTX_FMT_0 0x2088
809 #define R200_SE_VAP_CNTL 0x2080
810 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
811 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
812 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
813 #define R200_PP_TXFILTER_5 0x2ca0
814 #define R200_PP_TXFILTER_4 0x2c80
815 #define R200_PP_TXFILTER_3 0x2c60
816 #define R200_PP_TXFILTER_2 0x2c40
817 #define R200_PP_TXFILTER_1 0x2c20
818 #define R200_PP_TXFILTER_0 0x2c00
819 #define R200_PP_TXOFFSET_5 0x2d78
820 #define R200_PP_TXOFFSET_4 0x2d60
821 #define R200_PP_TXOFFSET_3 0x2d48
822 #define R200_PP_TXOFFSET_2 0x2d30
823 #define R200_PP_TXOFFSET_1 0x2d18
824 #define R200_PP_TXOFFSET_0 0x2d00
825
826 #define R200_PP_CUBIC_FACES_0 0x2c18
827 #define R200_PP_CUBIC_FACES_1 0x2c38
828 #define R200_PP_CUBIC_FACES_2 0x2c58
829 #define R200_PP_CUBIC_FACES_3 0x2c78
830 #define R200_PP_CUBIC_FACES_4 0x2c98
831 #define R200_PP_CUBIC_FACES_5 0x2cb8
832 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
833 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
834 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
835 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
836 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
837 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
838 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
839 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
840 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
841 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
842 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
843 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
844 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
845 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
846 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
847 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
848 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
849 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
850 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
851 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
852 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
853 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
854 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
855 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
856 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
857 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
858 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
859 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
860 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
861 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
862
863 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
864 #define R200_SE_VTE_CNTL 0x20b0
865 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
866 #define R200_PP_TAM_DEBUG3 0x2d9c
867 #define R200_PP_CNTL_X 0x2cc4
868 #define R200_SE_VAP_CNTL_STATUS 0x2140
869 #define R200_RE_SCISSOR_TL_0 0x1cd8
870 #define R200_RE_SCISSOR_TL_1 0x1ce0
871 #define R200_RE_SCISSOR_TL_2 0x1ce8
872 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
873 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
874 #define R200_SE_VTX_STATE_CNTL 0x2180
875 #define R200_RE_POINTSIZE 0x2648
876 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
877
878 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
879 #define RADEON_PP_TEX_SIZE_1 0x1d0c
880 #define RADEON_PP_TEX_SIZE_2 0x1d14
881
882 #define RADEON_PP_CUBIC_FACES_0 0x1d24
883 #define RADEON_PP_CUBIC_FACES_1 0x1d28
884 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
885 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
886 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
887 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
888
889 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
890
891 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
892 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
893 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
894 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
895 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
896 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
897 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
898 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
899 #define R200_3D_DRAW_IMMD_2 0xC0003500
900 #define R200_SE_VTX_FMT_1 0x208c
901 #define R200_RE_CNTL 0x1c50
902
903 #define R200_RB3D_BLENDCOLOR 0x3218
904
905 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
906
907 #define R200_PP_TRI_PERF 0x2cf8
908
909 #define R200_PP_AFS_0 0x2f80
910 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
911
912 #define R200_VAP_PVS_CNTL_1 0x22D0
913
914 /* Constants */
915 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
916
917 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
918 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
919 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
920 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
921 #define RADEON_LAST_DISPATCH 1
922
923 #define RADEON_MAX_VB_AGE 0x7fffffff
924 #define RADEON_MAX_VB_VERTS (0xffff)
925
926 #define RADEON_RING_HIGH_MARK 128
927
928 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
929
930 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
931 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
932 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
933 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
934
935 #define RADEON_WRITE_PLL( addr, val ) \
936 do { \
937 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
938 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
939 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
940 } while (0)
941
942 #define RADEON_WRITE_PCIE( addr, val ) \
943 do { \
944 RADEON_WRITE8( RADEON_PCIE_INDEX, \
945 ((addr) & 0xff)); \
946 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
947 } while (0)
948
949 #define CP_PACKET0( reg, n ) \
950 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
951 #define CP_PACKET0_TABLE( reg, n ) \
952 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
953 #define CP_PACKET1( reg0, reg1 ) \
954 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
955 #define CP_PACKET2() \
956 (RADEON_CP_PACKET2)
957 #define CP_PACKET3( pkt, n ) \
958 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
959
960 /* ================================================================
961 * Engine control helper macros
962 */
963
964 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
965 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
966 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
967 RADEON_WAIT_HOST_IDLECLEAN) ); \
968 } while (0)
969
970 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
971 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
972 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
973 RADEON_WAIT_HOST_IDLECLEAN) ); \
974 } while (0)
975
976 #define RADEON_WAIT_UNTIL_IDLE() do { \
977 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
978 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
979 RADEON_WAIT_3D_IDLECLEAN | \
980 RADEON_WAIT_HOST_IDLECLEAN) ); \
981 } while (0)
982
983 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
984 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
985 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
986 } while (0)
987
988 #define RADEON_FLUSH_CACHE() do { \
989 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
990 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
991 } while (0)
992
993 #define RADEON_PURGE_CACHE() do { \
994 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
995 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
996 } while (0)
997
998 #define RADEON_FLUSH_ZCACHE() do { \
999 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1000 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
1001 } while (0)
1002
1003 #define RADEON_PURGE_ZCACHE() do { \
1004 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1005 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
1006 } while (0)
1007
1008 /* ================================================================
1009 * Misc helper macros
1010 */
1011
1012 /* Perfbox functionality only.
1013 */
1014 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1015 do { \
1016 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1017 u32 head = GET_RING_HEAD( dev_priv ); \
1018 if (head == dev_priv->ring.tail) \
1019 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1020 } \
1021 } while (0)
1022
1023 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1024 do { \
1025 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1026 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1027 int __ret = radeon_do_cp_idle( dev_priv ); \
1028 if ( __ret ) return __ret; \
1029 sarea_priv->last_dispatch = 0; \
1030 radeon_freelist_reset( dev ); \
1031 } \
1032 } while (0)
1033
1034 #define RADEON_DISPATCH_AGE( age ) do { \
1035 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1036 OUT_RING( age ); \
1037 } while (0)
1038
1039 #define RADEON_FRAME_AGE( age ) do { \
1040 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1041 OUT_RING( age ); \
1042 } while (0)
1043
1044 #define RADEON_CLEAR_AGE( age ) do { \
1045 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1046 OUT_RING( age ); \
1047 } while (0)
1048
1049 /* ================================================================
1050 * Ring control
1051 */
1052
1053 #define RADEON_VERBOSE 0
1054
1055 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1056
1057 #define BEGIN_RING( n ) do { \
1058 if ( RADEON_VERBOSE ) { \
1059 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
1060 n, __FUNCTION__ ); \
1061 } \
1062 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1063 COMMIT_RING(); \
1064 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1065 } \
1066 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1067 ring = dev_priv->ring.start; \
1068 write = dev_priv->ring.tail; \
1069 mask = dev_priv->ring.tail_mask; \
1070 } while (0)
1071
1072 #define ADVANCE_RING() do { \
1073 if ( RADEON_VERBOSE ) { \
1074 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1075 write, dev_priv->ring.tail ); \
1076 } \
1077 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1078 DRM_ERROR( \
1079 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1080 ((dev_priv->ring.tail + _nr) & mask), \
1081 write, __LINE__); \
1082 } else \
1083 dev_priv->ring.tail = write; \
1084 } while (0)
1085
1086 #define COMMIT_RING() do { \
1087 /* Flush writes to ring */ \
1088 DRM_MEMORYBARRIER(); \
1089 GET_RING_HEAD( dev_priv ); \
1090 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1091 /* read from PCI bus to ensure correct posting */ \
1092 RADEON_READ( RADEON_CP_RB_RPTR ); \
1093 } while (0)
1094
1095 #define OUT_RING( x ) do { \
1096 if ( RADEON_VERBOSE ) { \
1097 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1098 (unsigned int)(x), write ); \
1099 } \
1100 ring[write++] = (x); \
1101 write &= mask; \
1102 } while (0)
1103
1104 #define OUT_RING_REG( reg, val ) do { \
1105 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1106 OUT_RING( val ); \
1107 } while (0)
1108
1109 #define OUT_RING_TABLE( tab, sz ) do { \
1110 int _size = (sz); \
1111 int *_tab = (int *)(tab); \
1112 \
1113 if (write + _size > mask) { \
1114 int _i = (mask+1) - write; \
1115 _size -= _i; \
1116 while (_i > 0 ) { \
1117 *(int *)(ring + write) = *_tab++; \
1118 write++; \
1119 _i--; \
1120 } \
1121 write = 0; \
1122 _tab += _i; \
1123 } \
1124 while (_size > 0) { \
1125 *(ring + write) = *_tab++; \
1126 write++; \
1127 _size--; \
1128 } \
1129 write &= mask; \
1130 } while (0)
1131
1132 #endif /* __RADEON_DRV_H__ */
linux v2.6.22.y-op