2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
25 #include <asm/processor.h>
28 #include <asm/pci-bridge.h>
29 #include <asm/byteorder.h>
31 #include <asm/machdep.h>
32 #include <asm/ppc-pci.h>
36 #define DBG(fmt...) printk(fmt)
41 unsigned long pci_probe_only
= 1;
42 int pci_assign_all_buses
= 0;
44 #ifdef CONFIG_PPC_MULTIPLATFORM
45 static void fixup_resource(struct resource
*res
, struct pci_dev
*dev
);
46 static void do_bus_setup(struct pci_bus
*bus
);
47 static void phbs_remap_io(void);
50 /* pci_io_base -- the base address from which io bars are offsets.
51 * This is the lowest I/O base address (so bar values are always positive),
52 * and it *must* be the start of ISA space if an ISA bus exists because
53 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
54 * page is mapped and isa_io_limit prevents access to it.
56 unsigned long isa_io_base
; /* NULL if no ISA bus */
57 EXPORT_SYMBOL(isa_io_base
);
58 unsigned long pci_io_base
;
59 EXPORT_SYMBOL(pci_io_base
);
61 void iSeries_pcibios_init(void);
65 struct dma_mapping_ops pci_dma_ops
;
66 EXPORT_SYMBOL(pci_dma_ops
);
68 int global_phb_number
; /* Global phb counter */
70 /* Cached ISA bridge dev. */
71 struct pci_dev
*ppc64_isabridge_dev
= NULL
;
72 EXPORT_SYMBOL_GPL(ppc64_isabridge_dev
);
74 static void fixup_broken_pcnet32(struct pci_dev
* dev
)
76 if ((dev
->class>>8 == PCI_CLASS_NETWORK_ETHERNET
)) {
77 dev
->vendor
= PCI_VENDOR_ID_AMD
;
78 pci_write_config_word(dev
, PCI_VENDOR_ID
, PCI_VENDOR_ID_AMD
);
81 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT
, PCI_ANY_ID
, fixup_broken_pcnet32
);
83 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
86 unsigned long offset
= 0;
87 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
92 if (res
->flags
& IORESOURCE_IO
)
93 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
95 if (res
->flags
& IORESOURCE_MEM
)
96 offset
= hose
->pci_mem_offset
;
98 region
->start
= res
->start
- offset
;
99 region
->end
= res
->end
- offset
;
102 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
103 struct pci_bus_region
*region
)
105 unsigned long offset
= 0;
106 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
111 if (res
->flags
& IORESOURCE_IO
)
112 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
114 if (res
->flags
& IORESOURCE_MEM
)
115 offset
= hose
->pci_mem_offset
;
117 res
->start
= region
->start
+ offset
;
118 res
->end
= region
->end
+ offset
;
121 #ifdef CONFIG_HOTPLUG
122 EXPORT_SYMBOL(pcibios_resource_to_bus
);
123 EXPORT_SYMBOL(pcibios_bus_to_resource
);
127 * We need to avoid collisions with `mirrored' VGA ports
128 * and other strange ISA hardware, so we always want the
129 * addresses to be allocated in the 0x000-0x0ff region
132 * Why? Because some silly external IO cards only decode
133 * the low 10 bits of the IO address. The 0x00-0xff region
134 * is reserved for motherboard devices that decode all 16
135 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
136 * but we want to try to avoid allocating at 0x2900-0x2bff
137 * which might have be mirrored at 0x0100-0x03ff..
139 void pcibios_align_resource(void *data
, struct resource
*res
,
140 resource_size_t size
, resource_size_t align
)
142 struct pci_dev
*dev
= data
;
143 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
144 resource_size_t start
= res
->start
;
145 unsigned long alignto
;
147 if (res
->flags
& IORESOURCE_IO
) {
148 unsigned long offset
= (unsigned long)hose
->io_base_virt
-
150 /* Make sure we start at our min on all hoses */
151 if (start
- offset
< PCIBIOS_MIN_IO
)
152 start
= PCIBIOS_MIN_IO
+ offset
;
155 * Put everything into 0x00-0xff region modulo 0x400
158 start
= (start
+ 0x3ff) & ~0x3ff;
160 } else if (res
->flags
& IORESOURCE_MEM
) {
161 /* Make sure we start at our min on all hoses */
162 if (start
- hose
->pci_mem_offset
< PCIBIOS_MIN_MEM
)
163 start
= PCIBIOS_MIN_MEM
+ hose
->pci_mem_offset
;
165 /* Align to multiple of size of minimum base. */
166 alignto
= max(0x1000UL
, align
);
167 start
= ALIGN(start
, alignto
);
173 static DEFINE_SPINLOCK(hose_spinlock
);
176 * pci_controller(phb) initialized common variables.
178 static void __devinit
pci_setup_pci_controller(struct pci_controller
*hose
)
180 memset(hose
, 0, sizeof(struct pci_controller
));
182 spin_lock(&hose_spinlock
);
183 hose
->global_number
= global_phb_number
++;
184 list_add_tail(&hose
->list_node
, &hose_list
);
185 spin_unlock(&hose_spinlock
);
188 static void add_linux_pci_domain(struct device_node
*dev
,
189 struct pci_controller
*phb
)
191 struct property
*of_prop
;
194 of_prop
= (struct property
*)
195 get_property(dev
, "linux,pci-domain", &size
);
198 WARN_ON(of_prop
&& size
< sizeof(int));
199 if (of_prop
&& size
< sizeof(int))
201 size
= sizeof(struct property
) + sizeof(int);
202 if (of_prop
== NULL
) {
204 of_prop
= kmalloc(size
, GFP_KERNEL
);
206 of_prop
= alloc_bootmem(size
);
208 memset(of_prop
, 0, sizeof(struct property
));
209 of_prop
->name
= "linux,pci-domain";
210 of_prop
->length
= sizeof(int);
211 of_prop
->value
= (unsigned char *)&of_prop
[1];
212 *((int *)of_prop
->value
) = phb
->global_number
;
213 prom_add_property(dev
, of_prop
);
216 struct pci_controller
* pcibios_alloc_controller(struct device_node
*dev
)
218 struct pci_controller
*phb
;
221 phb
= kmalloc(sizeof(struct pci_controller
), GFP_KERNEL
);
223 phb
= alloc_bootmem(sizeof (struct pci_controller
));
226 pci_setup_pci_controller(phb
);
227 phb
->arch_data
= dev
;
228 phb
->is_dynamic
= mem_init_done
;
230 PHB_SET_NODE(phb
, of_node_to_nid(dev
));
231 add_linux_pci_domain(dev
, phb
);
236 void pcibios_free_controller(struct pci_controller
*phb
)
238 if (phb
->arch_data
) {
239 struct device_node
*np
= phb
->arch_data
;
240 int *domain
= (int *)get_property(np
,
241 "linux,pci-domain", NULL
);
249 #ifndef CONFIG_PPC_ISERIES
250 void __devinit
pcibios_claim_one_bus(struct pci_bus
*b
)
253 struct pci_bus
*child_bus
;
255 list_for_each_entry(dev
, &b
->devices
, bus_list
) {
258 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
259 struct resource
*r
= &dev
->resource
[i
];
261 if (r
->parent
|| !r
->start
|| !r
->flags
)
263 pci_claim_resource(dev
, i
);
267 list_for_each_entry(child_bus
, &b
->children
, node
)
268 pcibios_claim_one_bus(child_bus
);
270 #ifdef CONFIG_HOTPLUG
271 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
274 static void __init
pcibios_claim_of_setup(void)
278 list_for_each_entry(b
, &pci_root_buses
, node
)
279 pcibios_claim_one_bus(b
);
283 #ifdef CONFIG_PPC_MULTIPLATFORM
284 static u32
get_int_prop(struct device_node
*np
, const char *name
, u32 def
)
289 prop
= (u32
*) get_property(np
, name
, &len
);
290 if (prop
&& len
>= 4)
295 static unsigned int pci_parse_of_flags(u32 addr0
)
297 unsigned int flags
= 0;
299 if (addr0
& 0x02000000) {
300 flags
= IORESOURCE_MEM
| PCI_BASE_ADDRESS_SPACE_MEMORY
;
301 flags
|= (addr0
>> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64
;
302 flags
|= (addr0
>> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M
;
303 if (addr0
& 0x40000000)
304 flags
|= IORESOURCE_PREFETCH
305 | PCI_BASE_ADDRESS_MEM_PREFETCH
;
306 } else if (addr0
& 0x01000000)
307 flags
= IORESOURCE_IO
| PCI_BASE_ADDRESS_SPACE_IO
;
311 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
313 static void pci_parse_of_addrs(struct device_node
*node
, struct pci_dev
*dev
)
317 struct resource
*res
;
321 addrs
= (u32
*) get_property(node
, "assigned-addresses", &proplen
);
324 DBG(" parse addresses (%d bytes) @ %p\n", proplen
, addrs
);
325 for (; proplen
>= 20; proplen
-= 20, addrs
+= 5) {
326 flags
= pci_parse_of_flags(addrs
[0]);
329 base
= GET_64BIT(addrs
, 1);
330 size
= GET_64BIT(addrs
, 3);
334 DBG(" base: %llx, size: %llx, i: %x\n",
335 (unsigned long long)base
, (unsigned long long)size
, i
);
337 if (PCI_BASE_ADDRESS_0
<= i
&& i
<= PCI_BASE_ADDRESS_5
) {
338 res
= &dev
->resource
[(i
- PCI_BASE_ADDRESS_0
) >> 2];
339 } else if (i
== dev
->rom_base_reg
) {
340 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
341 flags
|= IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
343 printk(KERN_ERR
"PCI: bad cfg reg num 0x%x\n", i
);
347 res
->end
= base
+ size
- 1;
349 res
->name
= pci_name(dev
);
350 fixup_resource(res
, dev
);
354 struct pci_dev
*of_create_pci_dev(struct device_node
*node
,
355 struct pci_bus
*bus
, int devfn
)
360 dev
= kmalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
363 type
= get_property(node
, "device_type", NULL
);
367 DBG(" create device, devfn: %x, type: %s\n", devfn
, type
);
369 memset(dev
, 0, sizeof(struct pci_dev
));
372 dev
->dev
.parent
= bus
->bridge
;
373 dev
->dev
.bus
= &pci_bus_type
;
375 dev
->multifunction
= 0; /* maybe a lie? */
377 dev
->vendor
= get_int_prop(node
, "vendor-id", 0xffff);
378 dev
->device
= get_int_prop(node
, "device-id", 0xffff);
379 dev
->subsystem_vendor
= get_int_prop(node
, "subsystem-vendor-id", 0);
380 dev
->subsystem_device
= get_int_prop(node
, "subsystem-id", 0);
382 dev
->cfg_size
= pci_cfg_space_size(dev
);
384 sprintf(pci_name(dev
), "%04x:%02x:%02x.%d", pci_domain_nr(bus
),
385 dev
->bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
386 dev
->class = get_int_prop(node
, "class-code", 0);
388 DBG(" class: 0x%x\n", dev
->class);
390 dev
->current_state
= 4; /* unknown power state */
392 if (!strcmp(type
, "pci") || !strcmp(type
, "pciex")) {
393 /* a PCI-PCI bridge */
394 dev
->hdr_type
= PCI_HEADER_TYPE_BRIDGE
;
395 dev
->rom_base_reg
= PCI_ROM_ADDRESS1
;
396 } else if (!strcmp(type
, "cardbus")) {
397 dev
->hdr_type
= PCI_HEADER_TYPE_CARDBUS
;
399 dev
->hdr_type
= PCI_HEADER_TYPE_NORMAL
;
400 dev
->rom_base_reg
= PCI_ROM_ADDRESS
;
401 /* Maybe do a default OF mapping here */
405 pci_parse_of_addrs(node
, dev
);
407 DBG(" adding to system ...\n");
409 pci_device_add(dev
, bus
);
411 /* XXX pci_scan_msi_device(dev); */
415 EXPORT_SYMBOL(of_create_pci_dev
);
417 void __devinit
of_scan_bus(struct device_node
*node
,
420 struct device_node
*child
= NULL
;
425 DBG("of_scan_bus(%s) bus no %d... \n", node
->full_name
, bus
->number
);
427 while ((child
= of_get_next_child(node
, child
)) != NULL
) {
428 DBG(" * %s\n", child
->full_name
);
429 reg
= (u32
*) get_property(child
, "reg", ®len
);
430 if (reg
== NULL
|| reglen
< 20)
432 devfn
= (reg
[0] >> 8) & 0xff;
434 /* create a new pci_dev for this device */
435 dev
= of_create_pci_dev(child
, bus
, devfn
);
438 DBG("dev header type: %x\n", dev
->hdr_type
);
440 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
441 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
442 of_scan_pci_bridge(child
, dev
);
447 EXPORT_SYMBOL(of_scan_bus
);
449 void __devinit
of_scan_pci_bridge(struct device_node
*node
,
453 u32
*busrange
, *ranges
;
455 struct resource
*res
;
459 DBG("of_scan_pci_bridge(%s)\n", node
->full_name
);
461 /* parse bus-range property */
462 busrange
= (u32
*) get_property(node
, "bus-range", &len
);
463 if (busrange
== NULL
|| len
!= 8) {
464 printk(KERN_DEBUG
"Can't get bus-range for PCI-PCI bridge %s\n",
468 ranges
= (u32
*) get_property(node
, "ranges", &len
);
469 if (ranges
== NULL
) {
470 printk(KERN_DEBUG
"Can't get ranges for PCI-PCI bridge %s\n",
475 bus
= pci_add_new_bus(dev
->bus
, dev
, busrange
[0]);
477 printk(KERN_ERR
"Failed to create pci bus for %s\n",
482 bus
->primary
= dev
->bus
->number
;
483 bus
->subordinate
= busrange
[1];
487 /* parse ranges property */
488 /* PCI #address-cells == 3 and #size-cells == 2 always */
489 res
= &dev
->resource
[PCI_BRIDGE_RESOURCES
];
490 for (i
= 0; i
< PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
; ++i
) {
492 bus
->resource
[i
] = res
;
496 for (; len
>= 32; len
-= 32, ranges
+= 8) {
497 flags
= pci_parse_of_flags(ranges
[0]);
498 size
= GET_64BIT(ranges
, 6);
499 if (flags
== 0 || size
== 0)
501 if (flags
& IORESOURCE_IO
) {
502 res
= bus
->resource
[0];
504 printk(KERN_ERR
"PCI: ignoring extra I/O range"
505 " for bridge %s\n", node
->full_name
);
509 if (i
>= PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
) {
510 printk(KERN_ERR
"PCI: too many memory ranges"
511 " for bridge %s\n", node
->full_name
);
514 res
= bus
->resource
[i
];
517 res
->start
= GET_64BIT(ranges
, 1);
518 res
->end
= res
->start
+ size
- 1;
520 fixup_resource(res
, dev
);
522 sprintf(bus
->name
, "PCI Bus %04x:%02x", pci_domain_nr(bus
),
524 DBG(" bus name: %s\n", bus
->name
);
526 mode
= PCI_PROBE_NORMAL
;
527 if (ppc_md
.pci_probe_mode
)
528 mode
= ppc_md
.pci_probe_mode(bus
);
529 DBG(" probe mode: %d\n", mode
);
531 if (mode
== PCI_PROBE_DEVTREE
)
532 of_scan_bus(node
, bus
);
533 else if (mode
== PCI_PROBE_NORMAL
)
534 pci_scan_child_bus(bus
);
536 EXPORT_SYMBOL(of_scan_pci_bridge
);
537 #endif /* CONFIG_PPC_MULTIPLATFORM */
539 void __devinit
scan_phb(struct pci_controller
*hose
)
542 struct device_node
*node
= hose
->arch_data
;
544 struct resource
*res
;
546 DBG("Scanning PHB %s\n", node
? node
->full_name
: "<NO NAME>");
548 bus
= pci_create_bus(NULL
, hose
->first_busno
, hose
->ops
, node
);
550 printk(KERN_ERR
"Failed to create bus for PCI domain %04x\n",
551 hose
->global_number
);
554 bus
->secondary
= hose
->first_busno
;
557 bus
->resource
[0] = res
= &hose
->io_resource
;
558 if (res
->flags
&& request_resource(&ioport_resource
, res
))
559 printk(KERN_ERR
"Failed to request PCI IO region "
560 "on PCI domain %04x\n", hose
->global_number
);
562 for (i
= 0; i
< 3; ++i
) {
563 res
= &hose
->mem_resources
[i
];
564 bus
->resource
[i
+1] = res
;
565 if (res
->flags
&& request_resource(&iomem_resource
, res
))
566 printk(KERN_ERR
"Failed to request PCI memory region "
567 "on PCI domain %04x\n", hose
->global_number
);
570 mode
= PCI_PROBE_NORMAL
;
571 #ifdef CONFIG_PPC_MULTIPLATFORM
572 if (node
&& ppc_md
.pci_probe_mode
)
573 mode
= ppc_md
.pci_probe_mode(bus
);
574 DBG(" probe mode: %d\n", mode
);
575 if (mode
== PCI_PROBE_DEVTREE
) {
576 bus
->subordinate
= hose
->last_busno
;
577 of_scan_bus(node
, bus
);
579 #endif /* CONFIG_PPC_MULTIPLATFORM */
580 if (mode
== PCI_PROBE_NORMAL
)
581 hose
->last_busno
= bus
->subordinate
= pci_scan_child_bus(bus
);
584 static int __init
pcibios_init(void)
586 struct pci_controller
*hose
, *tmp
;
588 /* For now, override phys_mem_access_prot. If we need it,
589 * later, we may move that initialization to each ppc_md
591 ppc_md
.phys_mem_access_prot
= pci_phys_mem_access_prot
;
593 #ifdef CONFIG_PPC_ISERIES
594 iSeries_pcibios_init();
597 printk(KERN_DEBUG
"PCI: Probing PCI hardware\n");
599 /* Scan all of the recorded PCI controllers. */
600 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
602 pci_bus_add_devices(hose
->bus
);
605 #ifndef CONFIG_PPC_ISERIES
607 pcibios_claim_of_setup();
609 /* FIXME: `else' will be removed when
610 pci_assign_unassigned_resources() is able to work
611 correctly with [partially] allocated PCI tree. */
612 pci_assign_unassigned_resources();
613 #endif /* !CONFIG_PPC_ISERIES */
615 /* Call machine dependent final fixup */
616 if (ppc_md
.pcibios_fixup
)
617 ppc_md
.pcibios_fixup();
619 /* Cache the location of the ISA bridge (if we have one) */
620 ppc64_isabridge_dev
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
621 if (ppc64_isabridge_dev
!= NULL
)
622 printk(KERN_DEBUG
"ISA bridge at %s\n", pci_name(ppc64_isabridge_dev
));
624 #ifdef CONFIG_PPC_MULTIPLATFORM
625 /* map in PCI I/O space */
629 printk(KERN_DEBUG
"PCI: Probing PCI hardware done\n");
634 subsys_initcall(pcibios_init
);
636 char __init
*pcibios_setup(char *str
)
641 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
646 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
649 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
650 struct resource
*res
= &dev
->resource
[i
];
652 /* Only set up the requested stuff */
653 if (!(mask
& (1<<i
)))
656 if (res
->flags
& IORESOURCE_IO
)
657 cmd
|= PCI_COMMAND_IO
;
658 if (res
->flags
& IORESOURCE_MEM
)
659 cmd
|= PCI_COMMAND_MEMORY
;
663 printk(KERN_DEBUG
"PCI: Enabling device: (%s), cmd %x\n",
665 /* Enable the appropriate bits in the PCI command register. */
666 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
672 * Return the domain number for this bus.
674 int pci_domain_nr(struct pci_bus
*bus
)
676 #ifdef CONFIG_PPC_ISERIES
679 struct pci_controller
*hose
= pci_bus_to_host(bus
);
681 return hose
->global_number
;
685 EXPORT_SYMBOL(pci_domain_nr
);
687 /* Decide whether to display the domain number in /proc */
688 int pci_proc_domain(struct pci_bus
*bus
)
690 #ifdef CONFIG_PPC_ISERIES
693 struct pci_controller
*hose
= pci_bus_to_host(bus
);
699 * Platform support for /proc/bus/pci/X/Y mmap()s,
700 * modelled on the sparc64 implementation by Dave Miller.
705 * Adjust vm_pgoff of VMA such that it is the physical page offset
706 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
708 * Basically, the user finds the base address for his device which he wishes
709 * to mmap. They read the 32-bit value from the config space base register,
710 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
711 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
713 * Returns negative error code on failure, zero on success.
715 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
716 unsigned long *offset
,
717 enum pci_mmap_state mmap_state
)
719 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
720 unsigned long io_offset
= 0;
724 return NULL
; /* should never happen */
726 /* If memory, add on the PCI bridge address offset */
727 if (mmap_state
== pci_mmap_mem
) {
728 *offset
+= hose
->pci_mem_offset
;
729 res_bit
= IORESOURCE_MEM
;
731 io_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
732 *offset
+= io_offset
;
733 res_bit
= IORESOURCE_IO
;
737 * Check that the offset requested corresponds to one of the
738 * resources of the device.
740 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
741 struct resource
*rp
= &dev
->resource
[i
];
742 int flags
= rp
->flags
;
744 /* treat ROM as memory (should be already) */
745 if (i
== PCI_ROM_RESOURCE
)
746 flags
|= IORESOURCE_MEM
;
748 /* Active and same type? */
749 if ((flags
& res_bit
) == 0)
752 /* In the range of this resource? */
753 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
756 /* found it! construct the final physical address */
757 if (mmap_state
== pci_mmap_io
)
758 *offset
+= hose
->io_base_phys
- io_offset
;
766 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
769 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
771 enum pci_mmap_state mmap_state
,
774 unsigned long prot
= pgprot_val(protection
);
776 /* Write combine is always 0 on non-memory space mappings. On
777 * memory space, if the user didn't pass 1, we check for a
778 * "prefetchable" resource. This is a bit hackish, but we use
779 * this to workaround the inability of /sysfs to provide a write
782 if (mmap_state
!= pci_mmap_mem
)
784 else if (write_combine
== 0) {
785 if (rp
->flags
& IORESOURCE_PREFETCH
)
789 /* XXX would be nice to have a way to ask for write-through */
790 prot
|= _PAGE_NO_CACHE
;
792 prot
&= ~_PAGE_GUARDED
;
794 prot
|= _PAGE_GUARDED
;
796 printk(KERN_DEBUG
"PCI map for %s:%lx, prot: %lx\n", pci_name(dev
), rp
->start
,
799 return __pgprot(prot
);
803 * This one is used by /dev/mem and fbdev who have no clue about the
804 * PCI device, it tries to find the PCI device first and calls the
807 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
812 struct pci_dev
*pdev
= NULL
;
813 struct resource
*found
= NULL
;
814 unsigned long prot
= pgprot_val(protection
);
815 unsigned long offset
= pfn
<< PAGE_SHIFT
;
818 if (page_is_ram(pfn
))
819 return __pgprot(prot
);
821 prot
|= _PAGE_NO_CACHE
| _PAGE_GUARDED
;
823 for_each_pci_dev(pdev
) {
824 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
825 struct resource
*rp
= &pdev
->resource
[i
];
826 int flags
= rp
->flags
;
828 /* Active and same type? */
829 if ((flags
& IORESOURCE_MEM
) == 0)
831 /* In the range of this resource? */
832 if (offset
< (rp
->start
& PAGE_MASK
) ||
842 if (found
->flags
& IORESOURCE_PREFETCH
)
843 prot
&= ~_PAGE_GUARDED
;
847 DBG("non-PCI map for %lx, prot: %lx\n", offset
, prot
);
849 return __pgprot(prot
);
854 * Perform the actual remap of the pages for a PCI device mapping, as
855 * appropriate for this architecture. The region in the process to map
856 * is described by vm_start and vm_end members of VMA, the base physical
857 * address is found in vm_pgoff.
858 * The pci device structure is provided so that architectures may make mapping
859 * decisions on a per-device or per-bus basis.
861 * Returns a negative error code on failure, zero on success.
863 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
864 enum pci_mmap_state mmap_state
, int write_combine
)
866 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
870 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
874 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
875 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
877 mmap_state
, write_combine
);
879 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
880 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
885 static ssize_t
pci_show_devspec(struct device
*dev
,
886 struct device_attribute
*attr
, char *buf
)
888 struct pci_dev
*pdev
;
889 struct device_node
*np
;
891 pdev
= to_pci_dev (dev
);
892 np
= pci_device_to_OF_node(pdev
);
893 if (np
== NULL
|| np
->full_name
== NULL
)
895 return sprintf(buf
, "%s", np
->full_name
);
897 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
899 void pcibios_add_platform_entries(struct pci_dev
*pdev
)
901 device_create_file(&pdev
->dev
, &dev_attr_devspec
);
904 #ifdef CONFIG_PPC_MULTIPLATFORM
906 #define ISA_SPACE_MASK 0x1
907 #define ISA_SPACE_IO 0x1
909 static void __devinit
pci_process_ISA_OF_ranges(struct device_node
*isa_node
,
910 unsigned long phb_io_base_phys
,
911 void __iomem
* phb_io_base_virt
)
913 /* Remove these asap */
927 struct isa_address isa_addr
;
928 struct pci_address pci_addr
;
932 struct isa_range
*range
;
933 unsigned long pci_addr
;
934 unsigned int isa_addr
;
938 range
= (struct isa_range
*) get_property(isa_node
, "ranges", &rlen
);
939 if (range
== NULL
|| (rlen
< sizeof(struct isa_range
))) {
940 printk(KERN_ERR
"no ISA ranges or unexpected isa range size,"
942 __ioremap_explicit(phb_io_base_phys
,
943 (unsigned long)phb_io_base_virt
,
944 0x10000, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
948 /* From "ISA Binding to 1275"
949 * The ranges property is laid out as an array of elements,
950 * each of which comprises:
951 * cells 0 - 1: an ISA address
952 * cells 2 - 4: a PCI address
953 * (size depending on dev->n_addr_cells)
954 * cell 5: the size of the range
956 if ((range
->isa_addr
.a_hi
&& ISA_SPACE_MASK
) == ISA_SPACE_IO
) {
957 isa_addr
= range
->isa_addr
.a_lo
;
958 pci_addr
= (unsigned long) range
->pci_addr
.a_mid
<< 32 |
959 range
->pci_addr
.a_lo
;
961 /* Assume these are both zero */
962 if ((pci_addr
!= 0) || (isa_addr
!= 0)) {
963 printk(KERN_ERR
"unexpected isa to pci mapping: %s\n",
968 size
= PAGE_ALIGN(range
->size
);
970 __ioremap_explicit(phb_io_base_phys
,
971 (unsigned long) phb_io_base_virt
,
972 size
, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
976 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
977 struct device_node
*dev
, int prim
)
979 unsigned int *ranges
, pci_space
;
983 struct resource
*res
;
984 int np
, na
= prom_n_addr_cells(dev
);
985 unsigned long pci_addr
, cpu_phys_addr
;
989 /* From "PCI Binding to 1275"
990 * The ranges property is laid out as an array of elements,
991 * each of which comprises:
992 * cells 0 - 2: a PCI address
993 * cells 3 or 3+4: a CPU physical address
994 * (size depending on dev->n_addr_cells)
995 * cells 4+5 or 5+6: the size of the range
997 ranges
= (unsigned int *) get_property(dev
, "ranges", &rlen
);
1000 hose
->io_base_phys
= 0;
1001 while ((rlen
-= np
* sizeof(unsigned int)) >= 0) {
1003 pci_space
= ranges
[0];
1004 pci_addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
1006 cpu_phys_addr
= ranges
[3];
1008 cpu_phys_addr
= (cpu_phys_addr
<< 32) | ranges
[4];
1010 size
= ((unsigned long)ranges
[na
+3] << 32) | ranges
[na
+4];
1015 /* Now consume following elements while they are contiguous */
1016 while (rlen
>= np
* sizeof(unsigned int)) {
1017 unsigned long addr
, phys
;
1019 if (ranges
[0] != pci_space
)
1021 addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
1024 phys
= (phys
<< 32) | ranges
[4];
1025 if (addr
!= pci_addr
+ size
||
1026 phys
!= cpu_phys_addr
+ size
)
1029 size
+= ((unsigned long)ranges
[na
+3] << 32)
1032 rlen
-= np
* sizeof(unsigned int);
1035 switch ((pci_space
>> 24) & 0x3) {
1036 case 1: /* I/O space */
1037 hose
->io_base_phys
= cpu_phys_addr
;
1038 hose
->pci_io_size
= size
;
1040 res
= &hose
->io_resource
;
1041 res
->flags
= IORESOURCE_IO
;
1042 res
->start
= pci_addr
;
1043 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose
->global_number
,
1044 res
->start
, res
->start
+ size
- 1);
1046 case 2: /* memory space */
1048 while (memno
< 3 && hose
->mem_resources
[memno
].flags
)
1052 hose
->pci_mem_offset
= cpu_phys_addr
- pci_addr
;
1054 res
= &hose
->mem_resources
[memno
];
1055 res
->flags
= IORESOURCE_MEM
;
1056 res
->start
= cpu_phys_addr
;
1057 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose
->global_number
,
1058 res
->start
, res
->start
+ size
- 1);
1063 res
->name
= dev
->full_name
;
1064 res
->end
= res
->start
+ size
- 1;
1066 res
->sibling
= NULL
;
1072 void __init
pci_setup_phb_io(struct pci_controller
*hose
, int primary
)
1074 unsigned long size
= hose
->pci_io_size
;
1075 unsigned long io_virt_offset
;
1076 struct resource
*res
;
1077 struct device_node
*isa_dn
;
1079 hose
->io_base_virt
= reserve_phb_iospace(size
);
1080 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1081 hose
->global_number
, hose
->io_base_phys
,
1082 (unsigned long) hose
->io_base_virt
);
1085 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1086 isa_dn
= of_find_node_by_type(NULL
, "isa");
1088 isa_io_base
= pci_io_base
;
1089 pci_process_ISA_OF_ranges(isa_dn
, hose
->io_base_phys
,
1090 hose
->io_base_virt
);
1091 of_node_put(isa_dn
);
1095 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1096 res
= &hose
->io_resource
;
1097 res
->start
+= io_virt_offset
;
1098 res
->end
+= io_virt_offset
;
1101 void __devinit
pci_setup_phb_io_dynamic(struct pci_controller
*hose
,
1104 unsigned long size
= hose
->pci_io_size
;
1105 unsigned long io_virt_offset
;
1106 struct resource
*res
;
1108 hose
->io_base_virt
= __ioremap(hose
->io_base_phys
, size
,
1109 _PAGE_NO_CACHE
| _PAGE_GUARDED
);
1110 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1111 hose
->global_number
, hose
->io_base_phys
,
1112 (unsigned long) hose
->io_base_virt
);
1115 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1117 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1118 res
= &hose
->io_resource
;
1119 res
->start
+= io_virt_offset
;
1120 res
->end
+= io_virt_offset
;
1124 static int get_bus_io_range(struct pci_bus
*bus
, unsigned long *start_phys
,
1125 unsigned long *start_virt
, unsigned long *size
)
1127 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1128 struct pci_bus_region region
;
1129 struct resource
*res
;
1132 res
= bus
->resource
[0];
1133 pcibios_resource_to_bus(bus
->self
, ®ion
, res
);
1134 *start_phys
= hose
->io_base_phys
+ region
.start
;
1135 *start_virt
= (unsigned long) hose
->io_base_virt
+
1137 if (region
.end
> region
.start
)
1138 *size
= region
.end
- region
.start
+ 1;
1140 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1141 __FUNCTION__
, region
.start
, region
.end
);
1147 res
= &hose
->io_resource
;
1148 *start_phys
= hose
->io_base_phys
;
1149 *start_virt
= (unsigned long) hose
->io_base_virt
;
1150 if (res
->end
> res
->start
)
1151 *size
= res
->end
- res
->start
+ 1;
1153 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1154 __FUNCTION__
, res
->start
, res
->end
);
1162 int unmap_bus_range(struct pci_bus
*bus
)
1164 unsigned long start_phys
;
1165 unsigned long start_virt
;
1169 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1173 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1175 if (iounmap_explicit((void __iomem
*) start_virt
, size
))
1180 EXPORT_SYMBOL(unmap_bus_range
);
1182 int remap_bus_range(struct pci_bus
*bus
)
1184 unsigned long start_phys
;
1185 unsigned long start_virt
;
1189 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1194 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1196 if (start_phys
== 0)
1198 printk(KERN_DEBUG
"mapping IO %lx -> %lx, size: %lx\n", start_phys
, start_virt
, size
);
1199 if (__ioremap_explicit(start_phys
, start_virt
, size
,
1200 _PAGE_NO_CACHE
| _PAGE_GUARDED
))
1205 EXPORT_SYMBOL(remap_bus_range
);
1207 static void phbs_remap_io(void)
1209 struct pci_controller
*hose
, *tmp
;
1211 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1212 remap_bus_range(hose
->bus
);
1215 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
1217 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1218 unsigned long offset
;
1220 if (res
->flags
& IORESOURCE_IO
) {
1221 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1223 res
->start
+= offset
;
1225 } else if (res
->flags
& IORESOURCE_MEM
) {
1226 res
->start
+= hose
->pci_mem_offset
;
1227 res
->end
+= hose
->pci_mem_offset
;
1231 void __devinit
pcibios_fixup_device_resources(struct pci_dev
*dev
,
1232 struct pci_bus
*bus
)
1234 /* Update device resources. */
1237 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
1238 if (dev
->resource
[i
].flags
)
1239 fixup_resource(&dev
->resource
[i
], dev
);
1241 EXPORT_SYMBOL(pcibios_fixup_device_resources
);
1244 static void __devinit
do_bus_setup(struct pci_bus
*bus
)
1246 struct pci_dev
*dev
;
1248 ppc_md
.iommu_bus_setup(bus
);
1250 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1251 ppc_md
.iommu_dev_setup(dev
);
1253 if (ppc_md
.irq_bus_setup
)
1254 ppc_md
.irq_bus_setup(bus
);
1257 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1259 struct pci_dev
*dev
= bus
->self
;
1261 if (dev
&& pci_probe_only
&&
1262 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
1263 /* This is a subordinate bridge */
1265 pci_read_bridge_bases(bus
);
1266 pcibios_fixup_device_resources(dev
, bus
);
1271 if (!pci_probe_only
)
1274 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1275 if ((dev
->class >> 8) != PCI_CLASS_BRIDGE_PCI
)
1276 pcibios_fixup_device_resources(dev
, bus
);
1278 EXPORT_SYMBOL(pcibios_fixup_bus
);
1281 * Reads the interrupt pin to determine if interrupt is use by card.
1282 * If the interrupt is used, then gets the interrupt line from the
1283 * openfirmware and sets it in the pci_dev and pci_config line.
1285 int pci_read_irq_line(struct pci_dev
*pci_dev
)
1290 DBG("Try to map irq for %s...\n", pci_name(pci_dev
));
1292 if (of_irq_map_pci(pci_dev
, &oirq
)) {
1293 DBG(" -> failed !\n");
1297 DBG(" -> got one, spec %d cells (0x%08x...) on %s\n",
1298 oirq
.size
, oirq
.specifier
[0], oirq
.controller
->full_name
);
1300 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
, oirq
.size
);
1301 if(virq
== NO_IRQ
) {
1302 DBG(" -> failed to map !\n");
1305 pci_dev
->irq
= virq
;
1306 pci_write_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, virq
);
1310 EXPORT_SYMBOL(pci_read_irq_line
);
1312 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1313 const struct resource
*rsrc
,
1314 u64
*start
, u64
*end
)
1316 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1317 unsigned long offset
= 0;
1322 if (rsrc
->flags
& IORESOURCE_IO
)
1323 offset
= pci_io_base
- (unsigned long)hose
->io_base_virt
+
1326 *start
= rsrc
->start
+ offset
;
1327 *end
= rsrc
->end
+ offset
;
1330 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
1335 struct pci_controller
*hose
, *tmp
;
1336 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1337 if (hose
->arch_data
== node
)
1339 node
= node
->parent
;
1344 #endif /* CONFIG_PPC_MULTIPLATFORM */
1346 unsigned long pci_address_to_pio(phys_addr_t address
)
1348 struct pci_controller
*hose
, *tmp
;
1350 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1351 if (address
>= hose
->io_base_phys
&&
1352 address
< (hose
->io_base_phys
+ hose
->pci_io_size
)) {
1353 unsigned long base
=
1354 (unsigned long)hose
->io_base_virt
- pci_io_base
;
1355 return base
+ (address
- hose
->io_base_phys
);
1358 return (unsigned int)-1;
1360 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
1363 #define IOBASE_BRIDGE_NUMBER 0
1364 #define IOBASE_MEMORY 1
1366 #define IOBASE_ISA_IO 3
1367 #define IOBASE_ISA_MEM 4
1369 long sys_pciconfig_iobase(long which
, unsigned long in_bus
,
1370 unsigned long in_devfn
)
1372 struct pci_controller
* hose
;
1373 struct list_head
*ln
;
1374 struct pci_bus
*bus
= NULL
;
1375 struct device_node
*hose_node
;
1377 /* Argh ! Please forgive me for that hack, but that's the
1378 * simplest way to get existing XFree to not lockup on some
1379 * G5 machines... So when something asks for bus 0 io base
1380 * (bus 0 is HT root), we return the AGP one instead.
1382 if (machine_is_compatible("MacRISC4"))
1386 /* That syscall isn't quite compatible with PCI domains, but it's
1387 * used on pre-domains setup. We return the first match
1390 for (ln
= pci_root_buses
.next
; ln
!= &pci_root_buses
; ln
= ln
->next
) {
1391 bus
= pci_bus_b(ln
);
1392 if (in_bus
>= bus
->number
&& in_bus
< (bus
->number
+ bus
->subordinate
))
1396 if (bus
== NULL
|| bus
->sysdata
== NULL
)
1399 hose_node
= (struct device_node
*)bus
->sysdata
;
1400 hose
= PCI_DN(hose_node
)->phb
;
1403 case IOBASE_BRIDGE_NUMBER
:
1404 return (long)hose
->first_busno
;
1406 return (long)hose
->pci_mem_offset
;
1408 return (long)hose
->io_base_phys
;
1410 return (long)isa_io_base
;
1411 case IOBASE_ISA_MEM
:
1419 int pcibus_to_node(struct pci_bus
*bus
)
1421 struct pci_controller
*phb
= pci_bus_to_host(bus
);
1424 EXPORT_SYMBOL(pcibus_to_node
);