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[linux-2.6.19-moxart.git] / include / asm-mips / cpu-features.h
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1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
8 */
9 #ifndef __ASM_CPU_FEATURES_H
10 #define __ASM_CPU_FEATURES_H
13 #include <asm/cpu.h>
14 #include <asm/cpu-info.h>
15 #include <cpu-feature-overrides.h>
18 * SMP assumption: Options of CPU 0 are a superset of all processors.
19 * This is true for all known MIPS systems.
21 #ifndef cpu_has_tlb
22 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
23 #endif
24 #ifndef cpu_has_4kex
25 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
26 #endif
27 #ifndef cpu_has_3k_cache
28 #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
29 #endif
30 #define cpu_has_6k_cache 0
31 #define cpu_has_8k_cache 0
32 #ifndef cpu_has_4k_cache
33 #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
34 #endif
35 #ifndef cpu_has_tx39_cache
36 #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
37 #endif
38 #ifndef cpu_has_sb1_cache
39 #define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE)
40 #endif
41 #ifndef cpu_has_fpu
42 #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
43 #endif
44 #ifndef cpu_has_32fpr
45 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
46 #endif
47 #ifndef cpu_has_counter
48 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
49 #endif
50 #ifndef cpu_has_watch
51 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
52 #endif
53 #ifndef cpu_has_divec
54 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
55 #endif
56 #ifndef cpu_has_vce
57 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
58 #endif
59 #ifndef cpu_has_cache_cdex_p
60 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
61 #endif
62 #ifndef cpu_has_cache_cdex_s
63 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
64 #endif
65 #ifndef cpu_has_prefetch
66 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
67 #endif
68 #ifndef cpu_has_mcheck
69 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
70 #endif
71 #ifndef cpu_has_ejtag
72 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
73 #endif
74 #ifndef cpu_has_llsc
75 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
76 #endif
77 #ifndef cpu_has_mips16
78 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
79 #endif
80 #ifndef cpu_has_mdmx
81 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
82 #endif
83 #ifndef cpu_has_mips3d
84 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
85 #endif
86 #ifndef cpu_has_smartmips
87 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
88 #endif
89 #ifndef cpu_has_vtag_icache
90 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
91 #endif
92 #ifndef cpu_has_dc_aliases
93 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
94 #endif
95 #ifndef cpu_has_ic_fills_f_dc
96 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
97 #endif
98 #ifndef cpu_has_pindexed_dcache
99 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
100 #endif
103 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
104 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
105 * don't. For maintaining I-cache coherency this means we need to flush the
106 * D-cache all the way back to whever the I-cache does refills from, so the
107 * I-cache has a chance to see the new data at all. Then we have to flush the
108 * I-cache also.
109 * Note we may have been rescheduled and may no longer be running on the CPU
110 * that did the store so we can't optimize this into only doing the flush on
111 * the local CPU.
113 #ifndef cpu_icache_snoops_remote_store
114 #ifdef CONFIG_SMP
115 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
116 #else
117 #define cpu_icache_snoops_remote_store 1
118 #endif
119 #endif
121 # ifndef cpu_has_mips32r1
122 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
123 # endif
124 # ifndef cpu_has_mips32r2
125 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
126 # endif
127 # ifndef cpu_has_mips64r1
128 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
129 # endif
130 # ifndef cpu_has_mips64r2
131 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
132 # endif
135 * Shortcuts ...
137 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
138 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
139 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
140 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
142 #ifndef cpu_has_dsp
143 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
144 #endif
146 #ifndef cpu_has_mipsmt
147 #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
148 #endif
150 #ifdef CONFIG_32BIT
151 # ifndef cpu_has_nofpuex
152 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
153 # endif
154 # ifndef cpu_has_64bits
155 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
156 # endif
157 # ifndef cpu_has_64bit_zero_reg
158 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
159 # endif
160 # ifndef cpu_has_64bit_gp_regs
161 # define cpu_has_64bit_gp_regs 0
162 # endif
163 # ifndef cpu_has_64bit_addresses
164 # define cpu_has_64bit_addresses 0
165 # endif
166 #endif
168 #ifdef CONFIG_64BIT
169 # ifndef cpu_has_nofpuex
170 # define cpu_has_nofpuex 0
171 # endif
172 # ifndef cpu_has_64bits
173 # define cpu_has_64bits 1
174 # endif
175 # ifndef cpu_has_64bit_zero_reg
176 # define cpu_has_64bit_zero_reg 1
177 # endif
178 # ifndef cpu_has_64bit_gp_regs
179 # define cpu_has_64bit_gp_regs 1
180 # endif
181 # ifndef cpu_has_64bit_addresses
182 # define cpu_has_64bit_addresses 1
183 # endif
184 #endif
186 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
187 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
188 #elif !defined(cpu_has_vint)
189 # define cpu_has_vint 0
190 #endif
192 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
193 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
194 #elif !defined(cpu_has_veic)
195 # define cpu_has_veic 0
196 #endif
198 #ifndef cpu_has_inclusive_pcaches
199 #define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
200 #endif
202 #ifndef cpu_dcache_line_size
203 #define cpu_dcache_line_size() current_cpu_data.dcache.linesz
204 #endif
205 #ifndef cpu_icache_line_size
206 #define cpu_icache_line_size() current_cpu_data.icache.linesz
207 #endif
208 #ifndef cpu_scache_line_size
209 #define cpu_scache_line_size() current_cpu_data.scache.linesz
210 #endif
212 #endif /* __ASM_CPU_FEATURES_H */