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MOXA linux-2.6.x / linux-2.6.19-uc1 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz
[linux-2.6.19-moxart.git] / include / asm-arm / arch-s3c24a0 / S3C24A0.h
blobd829416461eec0a51d8e78b5f3af7dd6aebec30a
1 /*
2 * linux/include/asm-arm/arch-s3c24a0/S3C24A0.h
3 *
4 * $Id: S3C24A0.h,v 1.2 2005/11/28 03:55:11 gerg Exp $
5 *
6 */
7
8 #ifndef _S3C24A0_H_
9 #define _S3C24A0_H_
10
11 #include "hardware.h"
12 #include "bitfield.h"
13
14 /*
15 * clock and power ( chapter 32 )
16 */
17
18 #define LOCKTIME __REG(0x40000000)
19 #define XTALWSET __REG(0x40000004)
20 #define MPLLCON __REG(0x40000010)
21 #define UPLLCON __REG(0x40000014)
22 #define CLKCON __REG(0x40000020)
23 #define CLKSRC __REG(0x40000024)
24 #define CLKDIVN __REG(0x40000028)
25 #define POWERMAN __REG(0x40000030)
26 #define SOFTRST __REG(0x40000038)
27
28 /* fields */
29 #define fLOCK_U Fld(12,16) /* UPLL lock time in LOCKTIME */
30 #define fLOCK_M Fld(12,0) /* MPLL lock time in LOCKTIME */
31 #define fXTAL_U Fld(16,16) /* UPLL wait time in XTALWSET */
32 #define fXTAL_M Fld(16,0) /* MPLL wait time in XTALWSET */
33 #define fPLL_MDIV Fld(8,12)
34 #define fPLL_PDIV Fld(6,4)
35 #define fPLL_SDIV Fld(2,0)
36 #define fEXTDIV Fld(3,0) /* external clock div. in CLKSRC */
37 #define fCLK_CAMDIV Fld(4,8) /* CAM clock div. in CLKDIV */
38 #define fCLK_MP4DIV Fld(4,4) /* MPEG4 clock div. in CLKDIV */
39 #define fCNFG_BF Fld(2,9) /* battery fault handling config in PWRMAN */
40 #define fSLEEP_CODE Fld(8,0) /* sleep mode setting code in PWRMAN */
41 /* bits */
42 #define CLKCON_VPOST (1<<25) /* CLKCON */
43 #define CLKCON_MPEG4IF (1<<24)
44 #define CLKCON_CAM_UPLL (1<<23)
45 #define CLKCON_LCD (1<<22)
46 #define CLKCON_CAM_HCLK (1<<21)
47 #define CLKCON_MPEG4 (1<<20)
48 #define CLKCON_KEYPAD (1<<19)
49 #define CLKCON_ADC (1<<18)
50 #define CLKCON_SD (1<<17)
51 #define CLKCON_MS (1<<16) /* memory stick */
52 #define CLKCON_USBD (1<<15)
53 #define CLKCON_GPIO (1<<14)
54 #define CLKCON_IIS (1<<13)
55 #define CLKCON_IIC (1<<12)
56 #define CLKCON_SPI (1<<11)
57 #define CLKCON_UART1 (1<<10)
58 #define CLKCON_UART0 (1<<9)
59 #define CLKCON_PWM (1<<8)
60 #define CLKCON_USBH (1<<7)
61 #define CLKCON_AC97 (1<<6)
62 #define CLKCON_EAHB (1<<5)
63 #define CLKCON_IrDA (1<<4)
64 #define CLKCON_IDLE (1<<2)
65 #define CLKCON_MON (1<<1)
66 #define CLKCON_STOP (1<<0)
67 #define CLKSRC_OSC (1<<8) /* CLKSRC */
68 #define CLKSRC_nUPLL (1<<7)
69 #define CLKSRC_nPLL (1<<5)
70 #define CLKSRC_EXT (1<<4)
71 #define CLKDIV_HCLK (1<<1) /* CLKDIV */
72 #define CLKDIV_PCLK (1<<0)
73 #define PWRMAN_MASKTS (1<<8) /* PWRMAN */
74
75 //#define fCLKDIVN_BUS Fld(2,0) /* S3C24A0X */
76 #define fCLKDIVN_BUS Fld(3,0) /* SW.LEE: S3C24A0A */
77 #define CLKDIVN_BUS FExtr(CLKDIVN, fCLKDIVN_BUS)
78 #define CLKDIVN_CAM(x) FInsrt((x), fCLK_CAMDIV)
79 #define CLKDIVN_CAM_MSK FMsk(fCLK_CAMDIV)
80 #define CLKDIVN_CAM_VAL FExtr(CLKDIVN, fCLK_CAMDIV)
81 #define CLKDIVN_MP4(x) FInsrt((x), fCLK_MP4DIV)
82 #define CLKDIVN_MP4_MSK FMsk(fCLK_MP4DIV)
83
84
85 /*
86 * PWM timer ( chapter 7 )
87 *
88 * five 16bit timers.
89 * two 8bit prescalers, four 4bit dividers
90 * programmable duty control of output waveform
91 * auto-load mode, one-shot pulse mode
92 * dead-zone generator
93 */
94 #define bPWM_TIMER(Nb) __REG(0x44000000 + (Nb))
95 #define bPWM_BUFn(Nb,x) bPWM_TIMER(0x0c + (Nb)*0x0c + (x))
96 /* Registers */
97 #define TCFG0 __REG(0x44000000)
98 #define TCFG1 __REG(0x44000004)
99 #define TCON __REG(0x44000008)
100 #define TCNTB0 __REG(0x4400000C)
101 #define TCMPB0 __REG(0x44000010)
102 #define TCNTO0 __REG(0x44000014)
103 #define TCNTB1 bPWM_BUFn(1,0x0)
104 #define TCMPB1 bPWM_BUFn(1,0x4)
105 #define TCNTO1 bPWM_BUFn(1,0x8)
106 #define TCNTB2 bPWM_BUFn(2,0x0)
107 #define TCMPB2 bPWM_BUFn(2,0x4)
108 #define TCNTO2 bPWM_BUFn(2,0x8)
109 #define TCNTB3 bPWM_BUFn(3,0x0)
110 #define TCMPB3 bPWM_BUFn(3,0x4)
111 #define TCNTO3 bPWM_BUFn(3,0x8)
112 #define TCNTB4 bPWM_BUFn(4,0x0)
113 #define TCNTO4 bPWM_BUFn(4,0x4)
114
115 #define fTCFG0_DZONE Fld(8,16) /* the dead zone length (= timer 0) */
116 #define fTCFG0_PRE1 Fld(8,8) /* prescaler value for time 2,3,4 */
117 #define fTCFG0_PRE0 Fld(8,0) /* prescaler value for time 0,1 */
118 #define SET_PRESCALER0(x) ({ TCFG0 = (TCFG0 & ~(0xff)) | (x); })
119 #define GET_PRESCALER0() FExtr(TCFG0, fTCFG0_PRE0)
120 #define SET_PRESCALER1(x) ({ TCFG0 = (TCFG0 & ~(0xff << 8)) | ((x) << 8); })
121 #define GET_PRESCALER1() FExtr(TCFG0, fTCFG0_PRE0)
122
123 #define fTCFG1_DMA Fld(4,20) /* select DMA request channel */
124 #define fTCFG1_T4MUX Fld(4,16) /* timer4 input mux */
125 #define fTCFG1_T3MUX Fld(4,12) /* timer3 input mux */
126 #define fTCFG1_T2MUX Fld(4,8) /* timer2 input mux */
127 #define fTCFG1_T1MUX Fld(4,4) /* timer1 input mux */
128 #define fTCFG1_T0MUX Fld(4,0) /* timer0 input mux */
129 #define TIMER0_DIV(x) FInsrt((x), fTCFG1_T0MUX)
130 #define TIMER1_DIV(x) FInsrt((x), fTCFG1_T1MUX)
131 #define TIMER2_DIV(x) FInsrt((x), fTCFG1_T2MUX)
132 #define TIMER3_DIV(x) FInsrt((x), fTCFG1_T3MUX)
133 #define TIMER4_DIV(x) FInsrt((x), fTCFG1_T4MUX)
134
135 #define fTCON_TIMER4 Fld(3,20)
136 #define fTCON_TIMER3 Fld(4,16)
137 #define fTCON_TIMER2 Fld(4,12)
138 #define fTCON_TIMER1 Fld(4,8)
139 #define fTCON_TIMER0 Fld(5,0)
140
141 #define fCNTB Fld(16,0)
142 #define fCNTO Fld(16,0)
143 #define fCMPB Fld(16,0)
144
145 #define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE)
146 #define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1)
147 #define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0)
148 #define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */
149 #define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */
150 #define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */
151 #define COUNT_4_ON (TCON_4_ONOFF*1)
152 #define COUNT_4_OFF (TCON_4_ONOFF*0)
153 #define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */
154 #define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */
155 #define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */
156 #define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */
157 #define TCON_2_AUTO (1 << 15) /* auto reload on/off for Timer 3 */
158 #define TCON_2_INVERT (1 << 14) /* 1: Inverter on for TOUT3 */
159 #define TCON_2_MAN (1 << 13) /* manual Update TCNTB3,TCMPB3 */
160 #define TCON_2_ONOFF (1 << 12) /* 0: Stop, 1: start Timer 3 */
161 #define TCON_1_AUTO (1 << 11) /* auto reload on/off for Timer 3 */
162 #define TCON_1_INVERT (1 << 10) /* 1: Inverter on for TOUT3 */
163 #define TCON_1_MAN (1 << 9) /* manual Update TCNTB3,TCMPB3 */
164 #define TCON_1_ONOFF (1 << 8) /* 0: Stop, 1: start Timer 3 */
165 #define TCON_0_AUTO (1 << 3) /* auto reload on/off for Timer 3 */
166 #define TCON_0_INVERT (1 << 2) /* 1: Inverter on for TOUT3 */
167 #define TCON_0_MAN (1 << 1) /* manual Update TCNTB3,TCMPB3 */
168 #define TCON_0_ONOFF (1 << 0) /* 0: Stop, 1: start Timer 3 */
169
170 #define TIMER3_ATLOAD_ON (TCON_3_AUTO*1)
171 #define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO)
172 #define TIMER3_IVT_ON (TCON_3_INVERT*1)
173 #define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT))
174 #define TIMER3_MANUP (TCON_3_MAN*1)
175 #define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN))
176 #define TIMER3_ON (TCON_3_ONOFF*1)
177 #define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF))
178 #define TIMER2_ATLOAD_ON (TCON_2_AUTO*1)
179 #define TIMER2_ATLAOD_OFF FClrBit(TCON, TCON_2_AUTO)
180 #define TIMER2_IVT_ON (TCON_2_INVERT*1)
181 #define TIMER2_IVT_OFF (FClrBit(TCON, TCON_2_INVERT))
182 #define TIMER2_MANUP (TCON_2_MAN*1)
183 #define TIMER2_NOP (FClrBit(TCON, TCON_2_MAN))
184 #define TIMER2_ON (TCON_2_ONOFF*1)
185 #define TIMER2_OFF (FClrBit(TCON, TCON_2_ONOFF))
186 #define TIMER1_ATLOAD_ON (TCON_1_AUTO*1)
187 #define TIMER1_ATLAOD_OFF FClrBit(TCON, TCON_1_AUTO)
188 #define TIMER1_IVT_ON (TCON_1_INVERT*1)
189 #define TIMER1_IVT_OFF (FClrBit(TCON, TCON_1_INVERT))
190 #define TIMER1_MANUP (TCON_1_MAN*1)
191 #define TIMER1_NOP (FClrBit(TCON, TCON_1_MAN))
192 #define TIMER1_ON (TCON_1_ONOFF*1)
193 #define TIMER1_OFF (FClrBit(TCON, TCON_1_ONOFF))
194 #define TIMER0_ATLOAD_ON (TCON_0_AUTO*1)
195 #define TIMER0_ATLAOD_OFF FClrBit(TCON, TCON_0_AUTO)
196 #define TIMER0_IVT_ON (TCON_0_INVERT*1)
197 #define TIMER0_IVT_OFF (FClrBit(TCON, TCON_0_INVERT))
198 #define TIMER0_MANUP (TCON_0_MAN*1)
199 #define TIMER0_NOP (FClrBit(TCON, TCON_0_MAN))
200 #define TIMER0_ON (TCON_0_ONOFF*1)
201 #define TIMER0_OFF (FClrBit(TCON, TCON_0_ONOFF))
202
203 #define TCON_TIMER1_CLR FClrFld(TCON, fTCON_TIMER1);
204 #define TCON_TIMER2_CLR FClrFld(TCON, fTCON_TIMER2);
205 #define TCON_TIMER3_CLR FClrFld(TCON, fTCON_TIMER3);
206
207
208 /*
209 * NAND ( chapter 4 )
210 *
211 */
212 #include "s3c24a0_nand.h"
213
214 /* S3C24A0-A LCD CONTROLLER DEVICE ONLY */
215 #ifdef CONFIG_ARCH_S3C24A0A
216 #define bLCD_CTL(Nb) __REG(0x4a000000 + (Nb))
217 #define LCDCON1 bLCD_CTL(0x00) /* LCD CONTROL 1 */
218 #define LCDCON2 bLCD_CTL(0x04) /* LCD CONTROL 2 */
219 #define LCDTCON1 bLCD_CTL(0x08) /* LCD TIME CONTROL 1 */
220 #define LCDTCON2 bLCD_CTL(0x0c) /* LCD TIME CONTROL 2 */
221 #define LCDTCON3 bLCD_CTL(0x10) /* LCD TIME CONTROL 3 */
222 #define LCDOSD1 bLCD_CTL(0x14) /* LCD OSD CONTROL REGISTER */
223 #define LCDOSD2 bLCD_CTL(0x18) /* Foreground image(OSD Image) left top position set */
224 #define LCDOSD3 bLCD_CTL(0x1c) /* Foreground image(OSD Image) right bottom position set */
225 #define LCDSADDRB1 bLCD_CTL(0x20) /* Frame buffer start address 1 (Background buffer 1) */
226 #define LCDSADDRB2 bLCD_CTL(0x24) /* Frame buffer start address 2 (Background buffer 2) */
227 #define LCDSADDRF1 bLCD_CTL(0x28) /* Frame buffer start address 1 (Foreground buffer 1) */
228 #define LCDSADDRF2 bLCD_CTL(0x2c) /* Frame buffer start address 2 (Foreground buffer 2) */
229 #define LCDEADDRB1 bLCD_CTL(0x30) /* Frame buffer end address 1 (Background buffer 1) */
230 #define LCDEADDRB2 bLCD_CTL(0x34) /* Frame buffer end address 2 (Background buffer 2) */
231 #define LCDEADDRF1 bLCD_CTL(0x38) /* Frame buffer end address 1 (Foreground buffer 1) */
232 #define LCDEADDRF3 bLCD_CTL(0x3c) /* Frame buffer end address 2 (Foreground buffer 2) */
233 #define LCDVSCRB1 bLCD_CTL(0x40) /* Virture Screen OFFSIZE and PAGE WIDTH (Background buffer 1) */
234 #define LCDVSCRB2 bLCD_CTL(0x44) /* Virture Screen OFFSIZE and PAGE WIDTH (Background buffer 2) */
235 #define LCDVSCRF1 bLCD_CTL(0x48) /* Virture Screen OFFSIZE and PAGE WIDTH (Foreground buffer 1) */
236 #define LCDVSCRF2 bLCD_CTL(0x4c) /* Virture Screen OFFSIZE and PAGE WIDTH (Foreground buffer 2) */
237 #define LCDINTCON bLCD_CTL(0x50) /* LCD Interrupt Control */
238 #define LCDKEYCON bLCD_CTL(0x54) /* COLOR KEY CONTROL 1 */
239 #define LCDKEYVAL bLCD_CTL(0x58) /* COLOR KEY CONTROL 2 */
240 #define LCDBGCON bLCD_CTL(0x5c) /* Background color Control */
241 #define LCDFGCON bLCD_CTL(0x60) /* Foreground color Control */
242 #define LCDDITHCON bLCD_CTL(0x64) /* LCD Dithering control active Matrix */
243
244 #define PALETTEBG 0x4A001000 //Background Palette start address
245 #define PALETTEFG 0x4A002000 //Background Palette start address
246
247 /* LCDCON1 */
248 #define fBURSTLEN Fld(2,28) /* DMA's BURST length selection*/
249 #define BURSTLEN4 FInsrt(0x2, fBURSTLEN)
250 #define BURSTLEN8 FInsrt(0x1, fBURSTLEN)
251 #define BURSTLEN16 FInsrt(0x0, fBURSTLEN)
252 #define BDBCON_BUF1 (0 << 21) /* Active frame slect control background image */
253 #define BDBCON_BUF2 (1 << 21) /* it will be adoted from next frame data */
254 #define FDBCON_BUF1 (0 << 20) /* Active frame select control foreground image */
255 #define FDBCON_BUF2 (1 << 20) /* it will adopted from next frame data */
256 #define DIVEN (1 << 19) /* 1:ENABLE 0:Disable */
257 #define DIVDIS (0 << 19) /* 0:disable */
258 #define fCLKVAL Fld(6,13)
259 #define CLKVALMSK FMsk(fCLKVAL) /* clk value bit clear */
260 #define CLKVAL(x) FInsrt((x), fCLKVAL) /* VCLK = HCLK / [(CLKVAL+1)x2] */
261 #define CLKDIR_DIVIDE (1 << 12) /* Select the clk src as 0:direct or 1:divide using CLKVAl register*/
262 #define CLKDIR_DIRECT (0 << 12) /* Select the clk src as 0:direct or 1:divide using CLKVAl register*/
263 #define fPNRMODE Fld(2,9) /* Select Disaplay mode */
264 #define PNRMODE_PRGB FInsrt(0x00, fPNRMODE) /* parallel RGB */
265 #define PNRMODE_PBGR FInsrt(0x01, fPNRMODE) /* parallel BGR */
266 #define PNRMODE_SRGB FInsrt(0x02, fPNRMODE) /* Serial RGB */
267 #define PNRMODE_SBGR FInsrt(0x03, fPNRMODE) /* Serial RGB */
268 #define fBPPMODEF Fld(3,6) /* SELECT THE BPP MODE FOR FOREGROUND IMAGE (OSD)*/
269 #define BPPMODEF_8_P FInsrt(0x3, fBPPMODEF) /* 8BPP palettized */
270 #define BPPMODEF_8_NP FInsrt(0x4, fBPPMODEF) /* 8BPP non palettized RGB-3:3:2 */
271 #define BPPMODEF_565 FInsrt(0x5, fBPPMODEF) /* 16BPP NON palettized RGB-5:6:5 */
272 #define BPPMODEF_5551 FInsrt(0x6, fBPPMODEF) /* 16BPP NON palettized RGB-5:5:5:1*/
273 #define BPPMODEF_18_UP FInsrt(0x7, fBPPMODEF) /* unpaked 18BPP non-palettized */
274 #define fBPPMODEB Fld(4,2) /* select the BPP mode for fore ground image*/
275 #define MPPMODEB_1 FInsrt(0x00, fBPPMODEB) /* 1bpp */
276 #define MPPMODEB_2 FInsrt(0x01, fBPPMODEB) /* 2bpp */
277 #define MPPMODEB_4 FInsrt(0x02, fBPPMODEB) /* 4bpp */
278 #define MPPMODEB_8 FInsrt(0x03, fBPPMODEB) /* 8bpp palettized */
279 #define MPPMODEB_8N FInsrt(0x04, fBPPMODEB) /* 8bpp non palettized 3:3:2*/
280 #define MPPMODEB_565 FInsrt(0x05, fBPPMODEB) /* 16bpp non palettized 5:6:5*/
281 #define MPPMODEB_5551 FInsrt(0x06, fBPPMODEB) /* 16bpp non palettized 5:5:5:1*/
282 #define MPPMODEB_18 FInsrt(0x07, fBPPMODEB) /* unpacked 18bpp */
283 #define ENVID (1 << 1) /* 0:Disable 1:Enable LCD video output and logic immediatly */
284 #define ENVID_F (1 << 0) /* 0:Dis 1:Ena wait until Current frame end. */
285
286 /* LCDCON2 */
287 #define fPALFRM Fld(2,9) /* this bit determines the size of the palette data*/
288 #define PALFRM_666 FInsrt(0x01, fPALFRM) /* 18 BIT RGB-6:6:6 */
289 #define PALFRM_565 FInsrt(0x02, fPALFRM) /* 16 BIT RGB-5:6:5 */
290 #define PALFRM_5551 FInsrt(0x03, fPALFRM) /* 16 BIT RGB-5:5:5:1 */
291 #define IVCLK_RISING (1 << 7) /* this bit controls the polarity of the VCLK active edge */
292 #define IVCLK_FALLING (0 << 7) /* 1 :rising edge 0: falling edge */
293 #define IHSYNC_INVERT (1 << 6) /* HSYNC polarity inverted */
294 #define IHSYNC_NORMAL (0 << 6) /* HSYNC polarity normal */
295 #define IVSYNC_INVERT (1 << 5) /* VSYNC polarity inverted */
296 #define IVSYNC_NORMAL (0 << 5) /* VSYNC polarity normal */
297 #define IVDE_INVERT (1 << 3) /* DE polarity inverted */
298 #define IVDE_NORMAL (0 << 3) /* DE polarity normal */
299 #define BITSWP_EN (1 << 2) /* 1:BIT Swap Enable */
300 #define BITSWP_DIS (0 << 2) /* 0:BIT Swap Disable */
301 #define BYTESWP_EN (1 << 1) /* 1:BYTE Swap Enable */
302 #define BUTESWP_DIS (0 << 1) /* 0:BYTE Swap Disable */
303 #define HAWSWP_EN (1 << 0) /* 1:HALF WORD Swap Enable */
304 #define HAWSWP_DIS (0 << 0) /* 0:HALF WORD swap Disable */
305
306 /* LCD Time Control 1 Register */
307 #define VBPD(x) FInsrt((x), Fld(8,16)) /* VSync Back porch */
308 #define VFPD(x) FInsrt((x), Fld(8, 8)) /* VSync Front porch */
309 #define VSPW(x) FInsrt((x), Fld(8, 0)) /* VSync level width */
310 /* LCD Time Control 2 Register */
311 #define HBPD(x) FInsrt((x), Fld(8,16)) /* VSync Back porch */
312 #define HFPD(x) FInsrt((x), Fld(8, 8)) /* VSync Front porch */
313 #define HSPW(x) FInsrt((x), Fld(8, 0)) /* VSync level width */
314 /* LCD Time Control 3 register */
315 #define LINEVAL(x) FInsrt((x), Fld(11,11)) /* these bits determine the vertical size of lcd panel */
316 #define HOZVAL(x) FInsrt((x), Fld(11, 0)) /* these bits determine the horizontal size of lcd panel*//* LCD OSD Control 1 register */
317 #define OSDEN (1 << 9) /* OSD Enable */
318 #define OSDDIS (0 << 9) /* OSD Disable */
319 #define OSD_BLD_PIX (1 << 8) /* BLENDING MODE Per pixel blending (18 BPP only) */
320 #define OSD_BLD_PLANE (0 << 8) /* Per plane blending (8/16/18 BPP mode) */
321 #define OSD_ALPHA(x) FInsrt((x), Fld(8,0)) /* 8-bit Alpha value for Per plane defined by Equation 28-1. */
322 /* LCD OSD Control 2 Register */
323 #define OSD_LEFTTOP_X(x) FInsrt((x), Fld(11,11)) /*Horizontal screen coordinate for left top pixel of OSD image*/
324 #define OSD_LEFTTOP_Y(x) FInsrt((y), Fld(11, 0)) /* Vertical screen coordinate for left top pixel of OSD image*/
325 /* LCD OSD Control 3 Register */
326 /*OSD_RIGHTBOT_X,_Y <= LCD Panel size of X, Y */
327 #define OSD_RIGHTBOT_X(x) FInsrt((x), Fld(11,11)) /*Hor scr coordinate for right bottom pixel of OSD image. */
328 #define OSD_RIGHTBOT_Y(y) FInsrt((y), Fld(11, 0)) /* Ver scr coordinate for right bottom pixel of OSD image.*/
329 /* FRAME Buffer start address Register
330 LCDSADDRB1 Frame buffer start address register for Background buffer 1
331 LCDSADDRB2 Frame buffer start address register for Background buffer 2
332 LCDSADDRF1 Frame buffer start address register for Foreground(OSD) buffer 1
333 LCDSADDRF2 Frame buffer start address register for Foreground(OSD) buffer 2*/
334 #define LCDBANK(x) FInsrt((x), Fld( 8,24)) /* the bank location for the video buffer in the system memory. */
335 #define LCDBASEU(x) FInsrt((x), Fld(24, 0)) /* the start address of the LCD frame buffer. */
336 /* FRAME BUFFER END address Register
337 LCDEADDRB1 Frame buffer end address register for Background buffer 1
338 LCDEADDRB2 Frame buffer end address register for Background buffer 2
339 LCDEADDRF1 Frame buffer end address register for Foreground(OSD) buffer 1
340 LCDEADDRF2 Frame buffer end address register for Foreground(OSD) buffer 2
341
342 LCDBASEL = LCDBASEU + (PAGEWIDTH+OFFSIZE) x (LINEVAL+1) */
343 #define LCDBASEL(x) FInsrt((x), Fld(24,0)) /* the end address of the LCD frame buffer. */
344 /* Virture Screen offsize and page width registers
345 LCDVSCRB1 Virtual screen OFFSIZE and PAGEWIDTH for Background buffer 1
346 LCDVSCRB2 Virtual screen OFFSIZE and PAGEWIDTH for Background buffer 2
347 LCDVSCRF1 Virtual screen OFFSIZE and PAGEWIDTH for Foreground(OSD) buffer 1
348 LCDVSCRF2 Virtual screen OFFSIZE and PAGEWIDTH for Foreground(OSD) buffer 2*/
349 #define OFFSIZE(x) FInsrt((x), Fld(13,13)) /* Virtual screen offset size (the number of byte). */
350 #define PAGEWIDTH(x) FInsrt((x), Fld(13, 0)) /* Virtual screen page width (the number of byte). */
351 /* LCD Interrupt Control Register */
352 #define fFRAME_INT2 Fld(2,10) /* LCD Frame Interrupt 2 at start of */
353 #define FRAMESEL0_BP FInsrt(0x0, fFRAME_INT2) /* BACK Porch */
354 #define FRAMESEL0_VS FInsrt(0x1, fFRAME_INT2) /* VSYNC */
355 #define FRAMESEL0_ACT FInsrt(0x2, fFRAME_INT2) /* ACTIVE */
356 #define FRAMESEL0_FP FInsrt(0x3, fFRAME_INT2) /* FRONT */
357 #define fFRAME_INT1 Fld(2,8) /* LCD Frame Interrupt 1 at start of */
358 #define FRAMESEL1_BP FInsrt(0x1, fFRAME_INT1) /* BACK Porch */
359 #define FRAMESEL1_VS FInsrt(0x2, fFRAME_INT1) /* VSYNC */
360 #define FRAMESEL1_FP FInsrt(0x3, fFRAME_INT1) /* FRONTPorch */
361 #define INTFRAME_EN (1 << 7) /* LCD Frame interrupt Enable */
362 #define INTFRAME_DIS (0 << 7) /* LCD Frame interrupt Disable */
363 #define fFIFOSEL Fld(2,5) /* LCD FIFO INTERRUPT SELECT BIT */
364 #define FIFO_ALL FInsrt(0x00, fFIFOSEL) /* All fifi or CASE */
365 #define FIFO_BG FInsrt(0x01, fFIFOSEL) /* Background only */
366 #define FIFO_FG FInsrt(0x02, fFIFOSEL) /* FOREGROUND FIFO ONLY */
367 #define fFIFOLEVEL Fld(3,2) /* LCD FIFO interrupt level select 1~128 word */
368 #define FIFO_32W FInsrt(0x00, fFIFOLEVEL) /* 32 WORD LEFT */
369 #define FIFO_64W FInsrt(0x01, fFIFOLEVEL) /* 64 WORD */
370 #define FIFO_96W FInsrt(0x02, fFIFOLEVEL) /* 96 WORD */
371 #define FIFO_OR FInsrt(0x03, fFIFOLEVEL) /* 32,64,96 WORD */
372 #define INTFIFO_EN (1<<1)
373 #define INTFIFO_DIS (1<<1)
374 #define LCD_INTEN (1 << 0) /* LCD interrupt Enable */
375 #define LCD_INTDIS (0 << 0) /* LCD Interrupt Disable */
376 /* LCD color key LCDKEYCON 1 register */
377 #define KEYEN (1 << 25) /* color key enable, blending disable */
378 #define KEYDIS (0 << 25) /* color key disable, blending enable */
379 #define DIRCON_FORE (1 << 24) /* pixel from foreground image is displayed (only in OSD area) */
380 #define DIRCON_BACK (0 << 24) /* pixel from background image is displayed (only in OSD area) */
381 #define COMPKEY(x) FInsrt((X), Fld(24,0)) /* Each bit is correspond to the COLVAL[23:0]. */
382 /* color key 2 register LCDCOLVAL */
383 #define COLVAL(x) FInsrt((x), Fld(24,0)) /* Color key value for the transparent pixel effect. */
384 /* Background Color MAP */
385 #define BGCOLEN (1 << 24) /* Background color mapping control bit enable */
386 #define BGCOLDIS (0 << 24) /* Background color mapping control bit disable */
387 #define BGCOLOR(x) FInsrt((x), Fld(24,0)) /* Color Value */
388 /* Foreground Color MAP LCDFGCON */
389 #define FGCOLEN (1 << 24) /* Foreground color mapping control bit Enable. */
390 #define FGCOLDIS (0 << 24) /* Foreground color mapping control bit Disable */
391 #define FGCOLOR(x) FInsrt((x), Fld(24,0)) /* Color Value */
392 /* Dithering Contrl 1 Register LCD DITHERING MODE */
393 #define RDITHPOS_6BIT FInsrt(0x01, Fld(2,5)) /* Red Dither bit control 6bit */
394 #define RDITHPOS_5BIT FInsrt(0x02, Fld(2,5)) /* Red Dither bit control 5bit */
395 #define GDITHPOS_6BIT FInsrt(0x01, Fld(2,3)) /* Green Dither bit control 6bit */
396 #define GDITHPOS_5BIT FInsrt(0x02, Fld(2,3)) /* Green Dither bit control 5bit */
397 #define BDITHPOS_6BIT FInsrt(0x01, Fld(2,5)) /* Blue Dither bit control 6bit */
398 #define BDITHPOS_5BIT FInsrt(0x02, Fld(2,5)) /* Blue Dither bit control 5bit */
399 #define DITHEN (1 << 0) /* Dithering Enable bit */
400 #define DITHDIS (0 << 0) /* Dithering Disable bit */
401
402 #else
403 /* S3C24A0-X DEVICE ONLY */
404 /*
405 * LCD (chapter 27 )
406 */
407 #define bLCD_CTL(Nb) __REG(0x4a000000 + (Nb))
408 #define LCDCON1 bLCD_CTL(0x00)
409 #define LCDCON2 bLCD_CTL(0x04)
410 #define LCDCON3 bLCD_CTL(0x08)
411 #define LCDCON4 bLCD_CTL(0x0c)
412 #define LCDCON5 bLCD_CTL(0x10)
413 #define LCDADDR1 bLCD_CTL(0x14)
414 #define LCDADDR2 bLCD_CTL(0x18)
415 #define LCDADDR3 bLCD_CTL(0x1c)
416 #define TPAL bLCD_CTL(0x50)
417 #define LCDINTPND bLCD_CTL(0x54)
418 #define LCDSRCPND bLCD_CTL(0x58)
419 #define LCDINTMSK bLCD_CTL(0x5c)
420 #define OSD_SADDR bLCD_CTL(0x6c)
421 #define OSD_EADDR bLCD_CTL(0x70)
422 #define OSD_LT bLCD_CTL(0x74) /* left top */
423 #define OSD_RB bLCD_CTL(0x78) /* right bottom & control */
424 #define LCD_PAL bLCD_CTL(0x400) /* palette register */
425
426 #define fLCD1_LINECNT Fld(10,18) /* the status of the line counter */
427 #define LCD1_LINECNT FMsk(fLCD_LINECNT)
428 #define fLCD1_CLKVAL Fld(10,8) /* rates of VCLK and CLKVAL[9:0] */
429 #define LCD1_CLKVAL(x) FInsrt((x), fLCD1_CLKVAL)
430 #define LCD1_CLKVAL_MSK FMsk(fLCD1_CLKVAL)
431 #define fLCD1_PNR Fld(2,5) /* select the display mode */
432 #define LCD1_PNR_TFT FInsrt(0x3, fLCD1_PNR) /* TFT LCD */
433 #define fLCD1_BPP Fld(4,1) /* select BPP(Bit Per Pixel) */
434 #define LCD1_BPP_1T FInsrt(0x8, fLCD1_BPP) /* TFT: 1 bpp */
435 #define LCD1_BPP_2T FInsrt(0x9, fLCD1_BPP) /* TFT: 2 bpp */
436 #define LCD1_BPP_4T FInsrt(0xa, fLCD1_BPP) /* TFT: 4 bpp */
437 #define LCD1_BPP_8T FInsrt(0xb, fLCD1_BPP) /* TFT: 8 bpp */
438 #define LCD1_BPP_16T FInsrt(0xc, fLCD1_BPP) /* TFT: 16 bpp */
439 #define LCD1_ENVID (1 << 0) /* 1: Enable the video output */
440 #define fLCD2_VBPD Fld(8,24) /* Vertical Back Porch */
441 #define LCD2_VBPD(x) FInsrt(((x)-1), fLCD2_VBPD)
442 #define fLCD2_LINEVAL Fld(10,14) /* vertical size of LCD */
443 #define LCD2_LINEVAL_MSK FMsk(fLCD2_LINEVAL)
444 #define LCD2_LINEVAL(x) FInsrt(((x)-1), fLCD2_LINEVAL)
445 #define fLCD2_VFPD Fld(8,6) /* Vertical Front Porch */
446 #define LCD2_VFPD(x) FInsrt(((x)-1), fLCD2_VFPD)
447 #define fLCD2_VSPW Fld(6,0) /* Vertical Sync Pulse Width */
448 #define LCD2_VSPW(x) FInsrt(((x)-1), fLCD2_VSPW)
449 #define fLCD3_HBPD Fld(7,19) /* Horizontal Back Porch */
450 #define LCD3_HBPD(x) FInsrt(((x)-1), fLCD3_HBPD)
451 #define fLCD3_HOZVAL Fld(11,8) /* horizontal size of LCD */
452 #define LCD3_HOZVAL_MSK FMsk(fLCD3_HOZVAL)
453 #define LCD3_HOZVAL(x) FInsrt(((x)-1), fLCD3_HOZVAL)
454 #define fLCD3_HFPD Fld(8,0) /* Horizontal Front Porch */
455 #define LCD3_HFPD(x) FInsrt(((x)-1), fLCD3_HFPD)
456 #define fLCD4_HSPW Fld(8,0) /* Horizontal Sync Pulse Width */
457 #define LCD4_HSPW(x) FInsrt(((x)-1), fLCD4_HSPW)
458 #define fLCD5_VSTAT Fld(2,15) /* Vertical Status (ReadOnly) */
459 #define LCD5_VSTAT FMsk(fLCD5_VSTAT)
460 #define LCD5_VSTAT_VS 0x00 /* VSYNC */
461 #define LCD5_VSTAT_BP 0x01 /* Back Porch */
462 #define LCD5_VSTAT_AC 0x02 /* Active */
463 #define LCD5_VSTAT_FP 0x03 /* Front Porch */
464 #define fLCD5_HSTAT Fld(2,13) /* Horizontal Status (ReadOnly) */
465 #define LCD5_HSTAT FMsk(fLCD5_HSTAT)
466 #define LCD5_HSTAT_HS 0x00 /* HSYNC */
467 #define LCD5_HSTAT_BP 0x01 /* Back Porch */
468 #define LCD5_HSTAT_AC 0x02 /* Active */
469 #define LCD5_HSTAT_FP 0x03 /* Front Porch */
470 #define LCD5_FRM565 (1 << 11) /* 1 : RGB 5:6:5 , 0 : RGB 5:5:5:1 */
471 #define LCD5_INVVCL (1 << 10) /*
472 1 : video data is fetched at VCLK falling edge
473 0 : video data is fetched at VCLK rising edge */
474 #define LCD5_HSYNC (1 << 9) /* 1: HSYNC pulse polarity is inverted */
475 #define LCD5_VSYNC (1 << 8) /* 1: VSYNC pulse polarity is inverted */
476 #define LCD5_INVVD (1 << 7) /* 1: VD pulse polarity is inverted */
477 #define LCD5_INVVDEN (1 << 6) /* 1: VDEN signal polarity is inverted */
478 #define LCD5_INVPWREN (1 << 5) /* 1: PWREN signal polarity is inverted */
479 #define LCD5_INVLEND (1 << 4) /* 1: LEND signal polarity is inverted */
480 #define LCD5_PWREN (1 << 3) /* 1: enable PWREN signal */
481 #define LCD5_LEND (1 << 2) /* 1: enable LEND signal */
482 #define LCD5_BSWP (1 << 1) /* 1: Byte swap enable */
483 #define LCD5_HWSWP (1 << 0) /* 1: HalfWord swap enable */
484
485 #define fLCDADDR_BANK Fld(9,21) /* bank location for video buffer */
486 #define LCDADDR_BANK(x) FInsrt((x), fLCDADDR_BANK)
487 #define fLCDADDR_BASEU Fld(21,0) /* address of upper left corner */
488 #define LCDADDR_BASEU(x) FInsrt((x), fLCDADDR_BASEU)
489 #define fLCDADDR_BASEL Fld(21,0) /* address of lower right corner */
490 #define LCDADDR_BASEL(x) FInsrt((x), fLCDADDR_BASEL)
491 #define fLCDADDR_OFFSET Fld(11,11) /* Virtual screen offset size
492 (# of half words) */
493 #define LCDADDR_OFFSET(x) FInsrt((x), fLCDADDR_OFFSET)
494 #define fLCDADDR_PAGE Fld(11,0) /* Virtual screen page width
495 (# of half words) */
496 #define LCDADDR_PAGE(x) FInsrt((x), fLCDADDR_PAGE)
497
498 #define TPAL_LEN (1 << 24) /* 1 : Temp. Pallete Register enable */
499 #define fTPAL_VAL Fld(24,0) /* Temp. Pallete Register value */
500 #define TPAL_VAL(x) FInsrt((x), fTPAL_VAL)
501 #define TPAL_VAL_RED(x) FInsrt((x), Fld(8,16))
502 #define TPAL_VAL_GREEN(x) FInsrt((x), Fld(8,8))
503 #define TPAL_VAL_BLUE(x) FInsrt((x), Fld(8,0))
504
505 #define fOSD_SADDR Fld(30,0) /* OSD DMA start address of A[30:1] */
506 #define OSD_Saddr(x) FInsrt((x), fOSD_SADDR)
507 #define fOSD_EADDR Fld(30,0) /* OSD DMA end address of A[30:1] */
508 #define OSD_Eaddr(x) FInsrt((x), fOSD_EADDR)
509 #define OSD_BLD (1<<24) /* 0: per plane blending */
510 #define fOSD_ALPHA Fld(4,20) /* 4-bit alpha value */
511 #define OSD_ALPHA(x) FInsrt((x), fOSD_ALPHA)
512 #define fOSD_LT_X Fld(10,10) /* left-top X */
513 #define OSD_LT_X(x) FInsrt((x), fOSD_LT_X)
514 #define fOSD_LT_Y Fld(10,0) /* left-top Y */
515 #define OSD_LT_Y(x) FInsrt((x), fOSD_LT_Y)
516 #define OSD_EN (1<<31) /* 1: enable OSD */
517 #define fOSD_WIDTH Fld(11,20) /* OSD width . # of half words */
518 #define OSD_WIDTH(x) FInsrt((x), fOSD_WIDTH)
519 #define fOSD_RB_X Fld(10,10) /* right bottom X */
520 #define OSD_RB_X(x) FInsrt((x), fOSD_RB_X)
521 #define fOSD_RB_Y Fld(10,0) /* right bottom Y */
522 #define OSD_RB_Y(x) FInsrt((x), fOSD_RB_Y)
523 #endif
524
525 /*
526 * UART ( chapter 11 )
527 */
528 #define UART_CTL_BASE 0x44400000
529 #define UART0_CTL_BASE UART_CTL_BASE
530 #define UART1_CTL_BASE (UART_CTL_BASE + 0x4000)
531 #define bUART(x, Nb) __REG(UART_CTL_BASE + (x)*0x4000 + (Nb))
532 /* offset */
533 #define oULCON 0x00
534 #define oUCON 0x04
535 #define oUFCON 0x08
536 #define oUMCON 0x0c
537 #define oUTRSTAT 0x10
538 #define oUERSTAT 0x14
539 #define oUFSTAT 0x18
540 #define oUMSTAT 0x1c
541 #define oUTXH 0x20
542 #define oURXH 0x24
543 #define oUBRDIV 0x28
544 /* Registers */
545 #define ULCON0 bUART(0, oULCON)
546 #define UCON0 bUART(0, oUCON)
547 #define UFCON0 bUART(0, oUFCON)
548 #define UMCON0 bUART(0, oUMCON)
549 #define UTRSTAT0 bUART(0, oUTRSTAT)
550 #define UERSTAT0 bUART(0, oUERSTAT)
551 #define UFSTAT0 bUART(0, oUFSTAT)
552 #define UMSTAT0 bUART(0, oUMSTAT)
553 #define UTXH0 bUART(0, oUTXH)
554 #define URXH0 bUART(0, oURXH)
555 #define UBRDIV0 bUART(0, oUBRDIV)
556 #define ULCON1 bUART(1, oULCON)
557 #define UCON1 bUART(1, oUCON)
558 #define UFCON1 bUART(1, oUFCON)
559 #define UMCON1 bUART(1, oUMCON)
560 #define UTRSTAT1 bUART(1, oUTRSTAT)
561 #define UERSTAT1 bUART(1, oUERSTAT)
562 #define UFSTAT1 bUART(1, oUFSTAT)
563 #define UMSTAT1 bUART(1, oUMSTAT)
564 #define UTXH1 bUART(1, oUTXH)
565 #define URXH1 bUART(1, oURXH)
566 #define UBRDIV1 bUART(1, oUBRDIV)
567 /* ... */
568
569 #define ULCON_IR (1 << 6) /* use Infra-Red mode */
570 #define fULCON_PAR Fld(3,3) /* what parity mode? */
571 #define ULCON_PAR FMsk(fULCON_PAR)
572 #define ULCON_PAR_NONE FInsrt(0x0, fULCON_PAR) /* No Parity */
573 #define ULCON_PAR_ODD FInsrt(0x4, fULCON_PAR) /* Odd Parity */
574 #define ULCON_PAR_EVEN FInsrt(0x5, fULCON_PAR) /* Even Parity */
575 #define ULCON_PAR_1 FInsrt(0x6, fULCON_PAR) /* Parity force/checked as 1 */
576 #define ULCON_PAR_0 FInsrt(0x7, fULCON_PAR) /* Parity force/checked as 0 */
577 #define ULCON_STOP (1 << 2) /* The number of stop bits */
578 #define ULCON_ONE_STOP (0 << 2) /* 1 stop bit */
579 #define ULCON_TWO_STOP (1 << 2) /* 2 stop bit */
580 #define fULCON_WL Fld(2, 0) /* word length */
581 #define ULCON_WL FMsk(fULCON_WL)
582 #define ULCON_WL5 FInsrt(0x0, fULCON_WL) /* 5 bits */
583 #define ULCON_WL6 FInsrt(0x1, fULCON_WL) /* 6 bits */
584 #define ULCON_WL7 FInsrt(0x2, fULCON_WL) /* 7 bits */
585 #define ULCON_WL8 FInsrt(0x3, fULCON_WL) /* 8 bits */
586
587 #define ULCON_CFGMASK (ULCON_IR | ULCON_PAR | ULCON_WL)
588
589 #define UCON_CLK_SEL (1 << 10) /* select clock for UART */
590 #define UCON_CLK_PCLK (0 << 10) /* PCLK for UART baud rate */
591 #define UCON_CLK_UCLK (1 << 10) /* UCLK for UART baud rate */
592 #define UCON_TX_INT_TYPE (1 << 9) /* TX Interrupt request type */
593 #define UCON_TX_INT_PLS (0 << 9) /* Pulse */
594 #define UCON_TX_INT_LVL (1 << 9) /* Level */
595 #define UCON_RX_INT_TYPE (1 << 8) /* RX Interrupt request type */
596 #define UCON_RX_INT_PLS (0 << 8) /* Pulse */
597 #define UCON_RX_INT_LVL (1 << 8) /* Level */
598 #define UCON_RX_TIMEOUT (1 << 7) /* RX timeout enable */
599 #define UCON_RX_ERR_INT (1 << 6) /* RX error status interrupt enable */
600 #define UCON_LOOPBACK (1 << 5) /* to enter the loop-back mode */
601 #define UCON_BRK_SIG (1 << 4) /* to send a break during 1 frame time */
602 #define fUCON_TX Fld(2,2) /* function to write Tx data to the buffer */
603 #define UCON_TX FMsk(fUCON_TX)
604 #define UCON_TX_DIS FInsrt(0x0, fUCON_TX) /* Disable */
605 #define UCON_TX_INT FInsrt(0x1, fUCON_TX) /* Interrupt or polling */
606 #define UCON_TX_DMA02 FInsrt(0x2, fUCON_TX) /* DMA0,2 for UART0 */
607 #define UCON_TX_DMA13 FInsrt(0x3, fUCON_TX) /* DMA1,3 for UART1 */
608 #define fUCON_RX Fld(2,0) /* function to read Rx data from buffer */
609 #define UCON_RX FMsk(fUCON_RX)
610 #define UCON_RX_DIS FInsrt(0x0, fUCON_RX) /* Disable */
611 #define UCON_RX_INT FInsrt(0x1, fUCON_RX) /* Interrupt or polling */
612 #define UCON_RX_DMA02 FInsrt(0x2, fUCON_RX) /* DMA0,2 for UART0 */
613 #define UCON_RX_DMA13 FInsrt(0x3, fUCON_RX) /* DMA1,3 for UART1 */
614
615 #define fUFCON_TX_TR Fld(2,6) /* trigger level of transmit FIFO */
616 #define UFCON_TX_TR FMsk(fUFCON_TX_TR)
617 #define UFCON_TX_TR0 FInsrt(0x0, fUFCON_TX_TR) /* Empty */
618 #define UFCON_TX_TR16 FInsrt(0x1, fUFCON_TX_TR) /* 16-byte */
619 #define UFCON_TX_TR32 FInsrt(0x2, fUFCON_TX_TR) /* 32-byte */
620 #define UFCON_TX_TR48 FInsrt(0x3, fUFCON_TX_TR) /* 48-byte */
621 #define fUFCON_RX_TR Fld(2,4) /* trigger level of receive FIFO */
622 #define UFCON_RX_TR FMsk(fUFCON_RX_TR)
623 #define UFCON_RX_TR1 FInsrt(0x0, fUFCON_RX_TR) /* 1-byte */
624 #define UFCON_RX_TR8 FInsrt(0x1, fUFCON_RX_TR) /* 8-byte */
625 #define UFCON_RX_TR16 FInsrt(0x2, fUFCON_RX_TR) /* 16-byte */
626 #define UFCON_RX_TR32 FInsrt(0x3, fUFCON_RX_TR) /* 32-byte */
627 #define UFCON_TX_CLR (1 << 2) /* auto-cleared after resetting FIFO */
628 #define UFCON_RX_CLR (1 << 1) /* auto-cleared after resetting FIFO */
629 #define UFCON_FIFO_EN (1 << 0) /* FIFO Enable */
630
631 #define UMCON_AFC (1 << 4) /* Enable Auto Flow Control */
632 #define UMCON_SEND (1 << 0) /* if no AFC, set nRTS 1:'L' 0:'H' level */
633
634 #define UTRSTAT_TR_EMP (1 << 2) /* 1: Transmitter buffer &
635 shifter register empty */
636 #define UTRSTAT_TX_EMP (1 << 1) /* Transmit buffer reg. is empty */
637 #define UTRSTAT_RX_RDY (1 << 0) /* Receive buffer reg. has data */
638
639 #define UERSTAT_OVERRUN (1 << 0) /* Overrun Error */
640 #define UERSTAT_ERR_MASK UERSTAT_OVERRUN
641
642 #define UFSTAT_TX_FULL (1 << 14) /* Transmit FIFO is full */
643 #define fUFSTAT_TX_CNT Fld(6,8) /* Number of data in Tx FIFO */
644 #define UFSTAT_TX_CNT FMsk(fUFSTAT_TX_CNT)
645 #define UFSTAT_RX_FULL (1 << 6) /* Receive FIFO is full */
646 #define fUFSTAT_RX_CNT Fld(6,0) /* Number of data in Rx FIFO */
647 #define UFSTAT_RX_CNT FMsk(fUFSTAT_RX_CNT)
648 #define UART1_TXFIFO_CNT() FExtr(UFSTAT1, fUFSTAT_TX_CNT)
649 #define UART1_RXFIFO_CNT() FExtr(UFSTAT1, fUFSTAT_RX_CNT)
650
651 #define UMSTAT_dCTS (1 << 4) /* delta CTS */
652 #define UMSTAT_CTS (1 << 0) /* CTS(Clear to Send) signal */
653
654 #define UTXH_DATA 0x000000FF /* Transmit data for UARTn */
655 #define URXH_DATA 0x000000FF /* Receive data for UARTn */
656 #define UBRDIVn 0x0000FFFF /* Baud rate division value (> 0) */
657
658 /*
659 * GPIO ( chapter 20 )
660 */
661 #define GPIO_CONL_NUM (2)
662 #define GPIO_CONM_NUM (1)
663 #define GPIO_CONU_NUM (0)
664 #define GPIO_CONL_BASE (0<<3)
665 #define GPIO_CONM_BASE (11<<3)
666 #define GPIO_CONU_BASE (19<<3)
667 #define GPIO_CONL (GPIO_CONL_NUM | GPIO_CONL_BASE)
668 #define GPIO_CONM (GPIO_CONM_NUM | GPIO_CONM_BASE)
669 #define GPIO_CONU (GPIO_CONU_NUM | GPIO_CONU_BASE)
670
671 #define GPCON(x) __REG(0x44800000 + (x) * 0x4)
672 #define GPCONU __REG(0x44800000)
673 #define GPCONM __REG(0x44800004)
674 #define GPCONL __REG(0x44800008)
675 #define GPDAT __REG(0x4480000c)
676 #define GPUP __REG(0x44800010)
677 #define GPIO_OFS_SHIFT 0
678 #define GPIO_CON_SHIFT 8
679 #define GPIO_PULLUP_SHIFT 16
680 #define GPIO_MODE_SHIFT 24
681 #define GPIO_OFS_MASK 0x000000ff
682 #define GPIO_CON_MASK 0x0000ff00
683 #define GPIO_PULLUP_MASK 0x00ff0000
684 #define GPIO_MODE_MASK 0xff000000
685 #define GPIO_MODE_IN (0 << GPIO_MODE_SHIFT)
686 #define GPIO_MODE_OUT (1 << GPIO_MODE_SHIFT)
687 #define GPIO_MODE_ALT0 (2 << GPIO_MODE_SHIFT)
688 #define GPIO_MODE_ALT1 (3 << GPIO_MODE_SHIFT)
689 #define GPIO_PULLUP_EN (0 << GPIO_PULLUP_SHIFT)
690 #define GPIO_PULLUP_DIS (1 << GPIO_PULLUP_SHIFT)
691
692 #define MAKE_GPIO_NUM(c, o) ((c << GPIO_CON_SHIFT) | (o << GPIO_OFS_SHIFT))
693
694 #define GRAB_MODE(x) (((x) & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT)
695 #define GRAB_PULLUP(x) (((x) & GPIO_PULLUP_MASK) >> GPIO_PULLUP_SHIFT)
696 #define GRAB_OFS(x) (((x) & GPIO_OFS_MASK) >> GPIO_OFS_SHIFT)
697 #define GRAB_CON_NUM(x) ((((x) & GPIO_CON_MASK) >> GPIO_CON_SHIFT) & 0x07)
698 #define GRAB_CON_OFS(x) (GRAB_OFS(x) - (((x) & GPIO_CON_MASK) >> (GPIO_CON_SHIFT+3)))
699
700 #define GPIO_0 MAKE_GPIO_NUM(GPIO_CONL, 0)
701 #define GPIO_1 MAKE_GPIO_NUM(GPIO_CONL, 1)
702 #define GPIO_2 MAKE_GPIO_NUM(GPIO_CONL, 2)
703 #define GPIO_3 MAKE_GPIO_NUM(GPIO_CONL, 3)
704 #define GPIO_4 MAKE_GPIO_NUM(GPIO_CONL, 4)
705 #define GPIO_5 MAKE_GPIO_NUM(GPIO_CONL, 5)
706 #define GPIO_6 MAKE_GPIO_NUM(GPIO_CONL, 6)
707 #define GPIO_7 MAKE_GPIO_NUM(GPIO_CONL, 7)
708 #define GPIO_8 MAKE_GPIO_NUM(GPIO_CONL, 8)
709 #define GPIO_9 MAKE_GPIO_NUM(GPIO_CONL, 9)
710 #define GPIO_10 MAKE_GPIO_NUM(GPIO_CONL, 10)
711 #define GPIO_11 MAKE_GPIO_NUM(GPIO_CONM, 11)
712 #define GPIO_12 MAKE_GPIO_NUM(GPIO_CONM, 12)
713 #define GPIO_13 MAKE_GPIO_NUM(GPIO_CONM, 13)
714 #define GPIO_14 MAKE_GPIO_NUM(GPIO_CONM, 14)
715 #define GPIO_15 MAKE_GPIO_NUM(GPIO_CONM, 15)
716 #define GPIO_16 MAKE_GPIO_NUM(GPIO_CONM, 16)
717 #define GPIO_17 MAKE_GPIO_NUM(GPIO_CONM, 17)
718 #define GPIO_18 MAKE_GPIO_NUM(GPIO_CONM, 18)
719 #define GPIO_19 MAKE_GPIO_NUM(GPIO_CONU, 19)
720 #define GPIO_20 MAKE_GPIO_NUM(GPIO_CONU, 20)
721 #define GPIO_21 MAKE_GPIO_NUM(GPIO_CONU, 21)
722 #define GPIO_22 MAKE_GPIO_NUM(GPIO_CONU, 22)
723 #define GPIO_23 MAKE_GPIO_NUM(GPIO_CONU, 23)
724 #define GPIO_24 MAKE_GPIO_NUM(GPIO_CONU, 24)
725 #define GPIO_25 MAKE_GPIO_NUM(GPIO_CONU, 25)
726 #define GPIO_26 MAKE_GPIO_NUM(GPIO_CONU, 26)
727 #define GPIO_27 MAKE_GPIO_NUM(GPIO_CONU, 27)
728 #define GPIO_28 MAKE_GPIO_NUM(GPIO_CONU, 28)
729 #define GPIO_29 MAKE_GPIO_NUM(GPIO_CONU, 29)
730 #define GPIO_30 MAKE_GPIO_NUM(GPIO_CONU, 30)
731 #define GPIO_31 MAKE_GPIO_NUM(GPIO_CONU, 31)
732 /* major alt. */
733 #define GPIO_MODE_EINT GPIO_MODE_ALT0
734 #define GPIO_MODE_RTC_ALARMINT GPIO_MODE_ALT1
735 #define GPIO_MODE_IrDA GPIO_MODE_ALT1
736 #define GPIO_MODE_PWM GPIO_MODE_ALT0
737 #define GPIO_MODE_SPI GPIO_MODE_ALT1
738 #define GPIO_MODE_EXT_DMA GPIO_MODE_ALT0
739 #define GPIO_MODE_EXT_KEYP GPIO_MODE_ALT1
740 #define GPIO_MODE_UART GPIO_MODE_ALT0
741 /* canonical */
742 #define GPIO_MODE_IrDA_SDBW GPIO_MODE_IrDA
743 #define GPIO_MODE_IrDA_TXD GPIO_MODE_IrDA
744 #define GPIO_MODE_IrDA_RXD GPIO_MODE_IrDA
745 #define GPIO_MODE_PWM_ECLK GPIO_MODE_PWM
746 #define GPIO_MODE_PWM_TOUT GPIO_MODE_PWM
747 #define GPIO_MODE_PWM_TOUT0 GPIO_MODE_PWM
748 #define GPIO_MODE_PWM_TOUT1 GPIO_MODE_PWM
749 #define GPIO_MODE_PWM_TOUT2 GPIO_MODE_PWM
750 #define GPIO_MODE_PWM_TOUT3 GPIO_MODE_PWM
751 #define GPIO_MODE_SPI_MODI GPIO_MODE_SPI
752 #define GPIO_MODE_SPI_MISO GPIO_MODE_SPI
753 #define GPIO_MODE_DMAREQ0 GPIO_MODE_EXT_DMA
754 #define GPIO_MODE_DMAREQ1 GPIO_MODE_EXT_DMA
755 #define GPIO_MODE_DMAACK0 GPIO_MODE_EXT_DMA
756 #define GPIO_MODE_DMAACK1 GPIO_MODE_EXT_DMA
757 #define GPIO_MODE_KEYP_ROW0 GPIO_MODE_EXT_KEYP
758 #define GPIO_MODE_KEYP_ROW1 GPIO_MODE_EXT_KEYP
759 #define GPIO_MODE_KEYP_ROW2 GPIO_MODE_EXT_KEYP
760 #define GPIO_MODE_KEYP_ROW3 GPIO_MODE_EXT_KEYP
761 #define GPIO_MODE_KEYP_ROW4 GPIO_MODE_EXT_KEYP
762 #define GPIO_MODE_KEYP_COL0 GPIO_MODE_EXT_KEYP
763 #define GPIO_MODE_KEYP_COL1 GPIO_MODE_EXT_KEYP
764 #define GPIO_MODE_KEYP_COL2 GPIO_MODE_EXT_KEYP
765 #define GPIO_MODE_KEYP_COL3 GPIO_MODE_EXT_KEYP
766 #define GPIO_MODE_KEYP_COL4 GPIO_MODE_EXT_KEYP
767 #define GPIO_MODE_uCTSn1 GPIO_MODE_UART
768 #define GPIO_MODE_uRTSn1 GPIO_MODE_UART
769 #define GPIO_MODE_uTXD1 GPIO_MODE_UART
770 #define GPIO_MODE_uRXD1 GPIO_MODE_UART
771
772 #define ENPU __REG(0x44800040) /* normal port pullup in sleep */
773 #define ENPU_EN __REG(0x44800064) /* ENPU enable */
774 #define GPDAT_S __REG(0x44800048) /* GPDAT in sleep */
775 #define GPDAT_SEN __REG(0x4480004c) /* GPDAT_S enable */
776 #define GPUP_S __REG(0x44800050) /* GPUP in sleep */
777 #define DATR0_S __REG(0x44800054) /* data in sleep */
778 #define DATR1_S __REG(0x44800058) /* data in sleep */
779 #define OEN0_S __REG(0x4480005c) /* output in sleep */
780 #define OEN1_S __REG(0x44800060) /* output in sleep */
781
782 #define ALIVECON __REG(0x44800044) /* clock for alive mode in sleep */
783 #define RSTCNT __REG(0x44800068) /* reset count for power settle-down */
784
785 #define set_gpio_ctrl(x) \
786 ({ GPCON(GRAB_CON_NUM((x))) &= ~(0x3 << (GRAB_CON_OFS((x))*2)); \
787 GPCON(GRAB_CON_NUM(x)) |= (GRAB_MODE(x) << (GRAB_CON_OFS((x))*2)); \
788 GPUP &= ~(1 << GRAB_OFS((x))); \
789 GPUP |= (GRAB_PULLUP((x)) << GRAB_OFS((x))); })
790 #define read_gpio_bit(x) ((GPDAT & (1<<GRAB_OFS((x)))) >> GRAB_OFS((x)))
791 #define write_gpio_bit(x, v) \
792 ({ GPDAT &= ~(0x1 << GRAB_OFS((x))); \
793 GPDAT |= ((v) << GRAB_OFS((x))); })
794
795 /*
796 * USB Host ( chapter 17 )
797 * - OHCI 1.0
798 * - USB 1.1
799 */
800 #define USB_OHCI_BASE __REG(0x41000000)
801
802 /*
803 * SROM Bank (chapter 2) for CS8900A
804 */
805 #define SROM_BW __REG(0x40c20000)
806 #define SROM_BC1 __REG(0x40c20008)
807
808
809 /*
810 * Interrupt ( chpater 6 )
811 */
812 #define SRCPND __REG(0x40200000)
813 #define INTMOD __REG(0x40200004)
814 #define INTMSK __REG(0x40200008)
815 #define PRIORITY __REG(0x4020000c)
816 #define INTPND __REG(0x40200010)
817 #define INTOFFSET __REG(0x40200014)
818 #define SUBSRCPND __REG(0x40200018)
819 #define INTSUBMSK __REG(0x4020001c)
820
821 #define EINTMASK __REG(0x44800034)
822 #define EINTPEND __REG(0x44800038)
823
824 #define EINTCR0 __REG(0x44800018)
825 #define EINTCR1 __REG(0x4480001c)
826 #define EINTCR2 __REG(0x44800020)
827
828
829 /*
830 * BUS Martrix
831 */
832
833 #define PRIORITY0 __REG(0x40ce0000)
834 #define PRIORITY1 __REG(0x40ce0004)
835 #define PRIORITY_S_FIX 0x0
836 #define PRIORITY_I_FIX 0x2
837
838 /*
839 * Watchdog timer ( chapter 8 )
840 */
841 #define WTCON __REG(0x44100000)
842 #define WTDAT __REG(0x44100004)
843 #define WTCNT __REG(0x44100008)
844
845 /*
846 * Real time clock ( chapter 10 )
847 *
848 * Note: All RTC registers have to be accessed by byte unit
849 * using STRB and LDRB instructions or char type pointer (page on 10-4)
850 */
851 #define RTCCON __REG(0x44200040)
852 #define TICNT __REG(0x44200044)
853 #define RTCALM __REG(0x44200050)
854 #define ALMSEC __REG(0x44200054)
855 #define ALMMIN __REG(0x44200058)
856 #define ALMHOUR __REG(0x4420005c)
857 #define ALMDATE __REG(0x44200060)
858 #define ALMMON __REG(0x44200064)
859 #define ALMYEAR __REG(0x44200068)
860 #define RTCRST __REG(0x4420006c)
861 #define BCDSEC __REG(0x44200070)
862 #define BCDMIN __REG(0x44200074)
863 #define BCDHOUR __REG(0x44200078)
864 #define BCDDATE __REG(0x4420007c)
865 #define BCDDAY __REG(0x44200080)
866 #define BCDMON __REG(0x44200084)
867 #define BCDYEAR __REG(0x44200088)
868
869 /* Fields */
870 #define fRTC_SEC Fld(7,0)
871 #define fRTC_MIN Fld(7,0)
872 #define fRTC_HOUR Fld(6,0)
873 #define fRTC_DATE Fld(6,0)
874 #define fRTC_DAY Fld(2,0)
875 #define fRTC_MON Fld(5,0)
876 #define fRTC_YEAR Fld(8,0)
877 /* Mask */
878 #define Msk_RTCSEC FMsk(fRTC_SEC)
879 #define Msk_RTCMIN FMsk(fRTC_MIN)
880 #define Msk_RTCHOUR FMsk(fRTC_HOUR)
881 #define Msk_RTCDAY FMsk(fRTC_DAY)
882 #define Msk_RTCDATE FMsk(fRTC_DATE)
883 #define Msk_RTCMON FMsk(fRTC_MON)
884 #define Msk_RTCYEAR FMsk(fRTC_YEAR)
885 /* bits */
886 #define RTCCON_EN (1 << 0) /* RTC Control Enable */
887 #define RTCCON_CLKSEL (1 << 1) /* BCD clock as XTAL 1/2^25 clock */
888 #define RTCCON_CNTSEL (1 << 2) /* 0: Merge BCD counters */
889 #define RTCCON_CLKRST (1 << 3) /* RTC clock count reset */
890
891 /* Tick Time count register */
892 #define RTCALM_GLOBAL (1 << 6) /* Global alarm enable */
893 #define RTCALM_YEAR (1 << 5) /* Year alarm enable */
894 #define RTCALM_MON (1 << 4) /* Month alarm enable */
895 #define RTCALM_DAY (1 << 3) /* Day alarm enable */
896 #define RTCALM_HOUR (1 << 2) /* Hour alarm enable */
897 #define RTCALM_MIN (1 << 1) /* Minute alarm enable */
898 #define RTCALM_SEC (1 << 0) /* Second alarm enable */
899 #define RTCALM_EN (RTCALM_GLOBAL | RTCALM_YEAR | RTCALM_MON |\
900 RTCALM_DAY | RTCALM_HOUR | RTCALM_MIN |\
901 RTCALM_SEC)
902 #define RTCALM_DIS (~RTCALM_EN)
903
904 /* ADC and Touch Screen Interface */
905 #define ADC_CTL_BASE 0x45800000
906 #define bADC_CTL(Nb) __REG(ADC_CTL_BASE + (Nb))
907 // Registers
908 #define ADCCON bADC_CTL(0x00) // R/W, ADC control register
909 #define ADCTSC bADC_CTL(0x04) // R/W, ADC touch screen ctl reg
910 #define ADCDLY bADC_CTL(0x08) // R/W, ADC start or interval delay reg
911 #define ADCDAX bADC_CTL(0x0c) // R , ADC conversion data reg
912 #define ADCDAY bADC_CTL(0x10) // R , ADC conversion data reg
913 // ADCCON
914 #define fECFLG Fld(1, 15) // R , End of conversion flag
915 #define ECFLG_VAL FExtr(ADCCON, fECFLG)
916 #define CONV_PROCESS 0
917 #define CONV_END 1
918
919 #define fPRSCEN Fld(1, 14)
920 #define PRSCEN_DIS FInsrt(0, fPRSCEN)
921 #define PRSCEN_EN FInsrt(1, fPRSCEN)
922
923 #define fPRSCVL Fld(8, 6)
924 #define PRSCVL(x) FInsrt(x, fPRSCVL)
925
926 #define fSEL_MUX Fld(3, 3)
927 #define ADC_IN_SEL(x) FInsrt(x, fSEL_MUX)
928 #define ADC_IN0 0
929 #define ADC_IN1 1
930 #define ADC_IN2 2
931 #define ADC_IN3 3
932 #define ADC_IN4 4
933 #define ADC_IN5 5
934 #define ADC_IN6 6
935 #define ADC_IN7 7
936
937 #define fSTDBM Fld(1, 2) // Standby mode select
938 #define STDBM_NORMAL FInsrt(0, fSTDBM)
939 #define STDBM_STANDBY FInsrt(1, fSTDBM)
940
941 #define fREAD_START Fld(1, 1)
942 #define READ_START_DIS FInsrt(0, fREAD_START)
943 #define READ_START_EN FInsrt(1, fREAD_START)
944
945 #define fENABLE_START Fld(1, 0)
946 #define ENABLE_START_NOOP FInsrt(0, fENABLE_START)
947 #define ENABLE_START_START FInsrt(1, fENABLE_START)
948
949 // ADCTSC
950 #define fYM_SEN Fld(1, 7)
951 #define YM_HIZ FInsrt(0, fYM_SEN)
952 #define YM_GND FInsrt(1, fYM_SEN)
953 #define fYP_SEN Fld(1, 6)
954 #define YP_EXTVLT FInsrt(0, fYP_SEN)
955 #define YP_AIN5 FInsrt(1, fYP_SEN)
956 #define fXM_SEN Fld(1, 5)
957 #define XM_HIZ FInsrt(0, fXM_SEN)
958 #define XM_GND FInsrt(1, fXM_SEN)
959 #define fXP_SEN Fld(1, 4)
960 #define XP_EXTVLT FInsrt(0, fXP_SEN)
961 #define XP_AIN7 FInsrt(1, fXP_SEN)
962 #define fPULL_UP Fld(1, 3)
963 #define XP_PULL_UP_EN FInsrt(0, fPULL_UP)
964 #define XP_PULL_UP_DIS FInsrt(1, fPULL_UP)
965 #define fAUTO_PST Fld(1, 2)
966 #define AUTO_PST_NORMAL FInsrt(0, fAUTO_PST)
967 #define AUTO_PST_AUTO FInsrt(1, fAUTO_PST)
968 #define fXY_PST Fld(2, 0)
969 #define XY_PST_NOOP FInsrt(0, fXY_PST)
970 #define XY_PST_X_POS FInsrt(1, fXY_PST)
971 #define XY_PST_Y_POS FInsrt(2, fXY_PST)
972 #define XY_PST_WAIT_INT FInsrt(3, fXY_PST)
973
974 // ADC Conversion DATA Field, commons
975 #define fUPDOWN Fld(1, 15)
976 #define fDAT_AUTO_PST Fld(1, 14)
977 #define fDAT_XY_PST Fld(2, 12)
978 #define fPST_DATA Fld(10, 0) // PST : position
979
980 #define PST_DAT_MSK 0x3FF
981 #define PST_DAT_VAL(x) (FExtr(x, fPST_DATA) & PST_DAT_MSK)
982 // ADCDAX
983 #define XPDATA PST_DAT_VAL(ADCDAX)
984 // ADCDAY
985 #define YPDATA PST_DAT_VAL(ADCDAY)
986
987 /*
988 * IIS Bus Interface ( chapter 14 )
989 */
990 #define IISCON __REG(0x44700000)
991 #define IISMOD __REG(0x44700004)
992 #define IISPSR __REG(0x44700008)
993 #define IISFIFOC __REG(0x4470000c)
994 #define IISFIFOE __REG(0x44700010)
995
996 #define IISCON_CH_RIGHT (1 << 8) /* Right channel */
997 #define IISCON_CH_LEFT (0 << 8) /* Left channel */
998 #define IISCON_TX_RDY (1 << 7) /* Transmit FIFO is ready(not empty) */
999 #define IISCON_RX_RDY (1 << 6) /* Receive FIFO is ready (not full) */
1000 #define IISCON_TX_DMA (1 << 5) /* Transmit DMA service reqeust */
1001 #define IISCON_RX_DMA (1 << 4) /* Receive DMA service reqeust */
1002 #define IISCON_TX_IDLE (1 << 3) /* Transmit Channel idle */
1003 #define IISCON_RX_IDLE (1 << 2) /* Receive Channel idle */
1004 #define IISCON_PRESCALE (1 << 1) /* IIS Prescaler Enable */
1005 #define IISCON_EN (1 << 0) /* IIS enable(start) */
1006
1007 #define IISMOD_SEL_MA (0 << 8) /* Master mode
1008 (IISLRCK, IISCLK are Output) */
1009 #define IISMOD_SEL_SL (1 << 8) /* Slave mode
1010 (IISLRCK, IISCLK are Input) */
1011 #define fIISMOD_SEL_TR Fld(2, 6) /* Transmit/Receive mode */
1012 #define IISMOD_SEL_TR FMsk(fIISMOD_SEL_TR)
1013 #define IISMOD_SEL_NO FInsrt(0x0, fIISMOD_SEL_TR) /* No Transfer */
1014 #define IISMOD_SEL_RX FInsrt(0x1, fIISMOD_SEL_TR) /* Receive */
1015 #define IISMOD_SEL_TX FInsrt(0x2, fIISMOD_SEL_TR) /* Transmit */
1016 #define IISMOD_SEL_BOTH FInsrt(0x3, fIISMOD_SEL_TR) /* Tx & Rx */
1017 #define IISMOD_CH_RIGHT (0 << 5) /* high for right channel */
1018 #define IISMOD_CH_LEFT (1 << 5) /* high for left channel */
1019 #define IISMOD_FMT_IIS (0 << 4) /* IIS-compatible format */
1020 #define IISMOD_FMT_MSB (1 << 4) /* MSB(left)-justified format */
1021 #define IISMOD_BIT_8 (0 << 3) /* Serial data bit/channel is 8 bit*/
1022 #define IISMOD_BIT_16 (1 << 3) /* Serial data bit/channel is 16 bit*/
1023 #define IISMOD_FREQ_256 (0 << 2) /* Master clock freq = 256 fs */
1024 #define IISMOD_FREQ_384 (1 << 2) /* Master clock freq = 384 fs */
1025 #define fIISMOD_SFREQ Fld(2, 0) /* Serial bit clock frequency */
1026 #define IISMOD_SFREQ FMsk(fIISMOD_SFREQ) /* fs = sampling frequency */
1027 #define IISMOD_SFREQ_16 FInsrt(0x0, fIISMOD_SFREQ) /* 16 fs */
1028 #define IISMOD_SFREQ_32 FInsrt(0x1, fIISMOD_SFREQ) /* 32 fs */
1029 #define IISMOD_SFREQ_48 FInsrt(0x2, fIISMOD_SFREQ) /* 48 fs */
1030
1031 #define fIISPSR_A Fld(5, 5) /* Prescaler Control A */
1032 #define IISPSR_A(x) FInsrt((x), fIISPSR_A)
1033 #define fIISPSR_B Fld(5, 0) /* Prescaler Control B */
1034 #define IISPSR_B(x) FInsrt((x), fIISPSR_B)
1035
1036 #define IISFCON_TX_NORM (0 << 15) /* Transmit FIFO access mode: normal */
1037 #define IISFCON_TX_DMA (1 << 15) /* Transmit FIFO access mode: DMA */
1038 #define IISFCON_RX_NORM (0 << 14) /* Receive FIFO access mode: normal */
1039 #define IISFCON_RX_DMA (1 << 14) /* Receive FIFO access mode: DMA */
1040 #define IISFCON_TX_EN (1 << 13) /* Transmit FIFO enable */
1041 #define IISFCON_RX_EN (1 << 12) /* Recevice FIFO enable */
1042 #define fIISFCON_TX_CNT Fld(6, 6) /* Tx FIFO data count (Read-Only) */
1043 #define IISFCON_TX_CNT FMsk(fIISFCON_TX_CNT)
1044 #define fIISFCON_RX_CNT Fld(6, 0) /* Rx FIFO data count (Read-Only) */
1045 #define IISFCON_RX_CNT FMsk(fIISFCON_RX_CNT)
1046
1047 /*
1048 * DMA controller ( chapter 9 )
1049 */
1050 #define DMA_CTL_BASE 0x40400000
1051 #define bDMA_CTL(Nb,x) __REG(DMA_CTL_BASE + (0x100000*Nb) + (x))
1052 /* DMA channel 0 */
1053 #define DISRC0 bDMA_CTL(0, 0x00)
1054 #define DISRCC0 bDMA_CTL(0, 0x04)
1055 #define DIDST0 bDMA_CTL(0, 0x08)
1056 #define DIDSTC0 bDMA_CTL(0, 0x0c)
1057 #define DCON0 bDMA_CTL(0, 0x10)
1058 #define DSTAT0 bDMA_CTL(0, 0x14)
1059 #define DCSRC0 bDMA_CTL(0, 0x18)
1060 #define DCDST0 bDMA_CTL(0, 0x1c)
1061 #define DMTRIG0 bDMA_CTL(0, 0x20)
1062 /* DMA channel 1 */
1063 #define DISRC1 bDMA_CTL(1, 0x00)
1064 #define DISRCC1 bDMA_CTL(1, 0x04)
1065 #define DIDST1 bDMA_CTL(1, 0x08)
1066 #define DIDSTC1 bDMA_CTL(1, 0x0c)
1067 #define DCON1 bDMA_CTL(1, 0x10)
1068 #define DSTAT1 bDMA_CTL(1, 0x14)
1069 #define DCSRC1 bDMA_CTL(1, 0x18)
1070 #define DCDST1 bDMA_CTL(1, 0x1c)
1071 #define DMTRIG1 bDMA_CTL(1, 0x20)
1072 /* DMA channel 2 */
1073 #define DISRC2 bDMA_CTL(2, 0x00)
1074 #define DISRCC2 bDMA_CTL(2, 0x04)
1075 #define DIDST2 bDMA_CTL(2, 0x08)
1076 #define DIDSTC2 bDMA_CTL(2, 0x0c)
1077 #define DCON2 bDMA_CTL(2, 0x10)
1078 #define DSTAT2 bDMA_CTL(2, 0x14)
1079 #define DCSRC2 bDMA_CTL(2, 0x18)
1080 #define DCDST2 bDMA_CTL(2, 0x1c)
1081 #define DMTRIG2 bDMA_CTL(2, 0x20)
1082 /* DMA channel 3 */
1083 #define DISRC3 bDMA_CTL(3, 0x00)
1084 #define DISRCC3 bDMA_CTL(3, 0x04)
1085 #define DIDST3 bDMA_CTL(3, 0x08)
1086 #define DIDSTC3 bDMA_CTL(3, 0x0c)
1087 #define DCON3 bDMA_CTL(3, 0x10)
1088 #define DSTAT3 bDMA_CTL(3, 0x14)
1089 #define DCSRC3 bDMA_CTL(3, 0x18)
1090 #define DCDST3 bDMA_CTL(3, 0x1c)
1091 #define DMTRIG3 bDMA_CTL(3, 0x20)
1092
1093 /* DISRC, DIDST Control registers */
1094 #define fDMA_BASE_ADDR Fld(30, 0) /* base address of src/dst data */
1095 #define DMA_BASE_ADDR(x) FInsrt(x, fDMA_BASE_ADDR)
1096 #define LOC_SRC (1 << 1) /* select the location of source */
1097 #define ON_AHB (LOC_SRC*0)
1098 #define ON_APB (LOC_SRC*1)
1099 #define ADDR_MODE (1 << 0) /* select the address increment */
1100 #define ADDR_INC (ADDR_MODE*0)
1101 #define ADDR_FIX (ADDR_MODE*1)
1102
1103 /* DCON Definitions */
1104 #define DCON_MODE (1 << 31) /* 0: demand, 1: handshake */
1105 #define DEMAND_MODE (DCON_MODE*0)
1106 #define HS_MODE (DCON_MODE*1)
1107 #define DCON_SYNC (1 << 30) /* sync to 0:PCLK, 1:HCLK */
1108 #define SYNC_PCLK (DCON_SYNC*0)
1109 #define SYNC_HCLK (DCON_SYNC*1)
1110 #define DCON_INT (1 << 29)
1111 #define POLLING_MODE (DCON_INT*0)
1112 #define INT_MODE (DCON_INT*1)
1113 #define DCON_TSZ (1 << 28) /* tx size 0: a unit, 1: burst */
1114 #define TSZ_UNIT (DCON_TSZ*0)
1115 #define TSZ_BURST (DCON_TSZ*1)
1116 #define DCON_SERVMODE (1 << 27) /* 0: single, 1: whole service */
1117 #define SINGLE_SERVICE (DCON_SERVMODE*0)
1118 #define WHOLE_SERVICE (DCON_SERVMODE*1)
1119 #define fDCON_HWSRC Fld(3, 24) /* select request source */
1120 #define CH0_nXDREQ0 0
1121 #define CH0_UART0 1
1122 #define CH0_I2SSDI 2
1123 #define CH0_TIMER 3
1124 #define CH0_USBEP1 4
1125 #define CH0_AC97_PCMOUT 5
1126 #define CH0_MSTICK 6
1127 #define CH0_IRDA 7
1128 #define CH1_nXDREQ1 0
1129 #define CH1_UART1 1
1130 #define CH1_I2SSDO 2
1131 #define CH1_SPI 3
1132 #define CH1_USBEP2 4
1133 #define CH1_AC97_PCMIN 5
1134 #define CH1_AC97_PCMOUT 6
1135 #define CH1_IRDA 7
1136 #define CH2_UART0 0
1137 #define CH2_I2SSDO 1
1138 #define CH2_SDMMC 2
1139 #define CH2_TIMER 3
1140 #define CH2_USBEP3 4
1141 #define CH2_AC97_MICIN 5
1142 #define CH2_AC97_PCMIN 6
1143 #define CH3_UART1 0
1144 #define CH3_SDMMC 1
1145 #define CH3_SPI 2
1146 #define CH3_TIMER 3
1147 #define CH3_USBEP4 4
1148 #define CH3_MSTICK 5
1149 #define CH3_AC97_MICIN 6
1150 #define HWSRC(x) FInsrt(x, fDCON_HWSRC)
1151 #define DCON_SWHW_SEL (1 << 23) /* DMA src 0: s/w 1: h/w */
1152 #define DMA_SRC_SW (DCON_SWHW_SEL*0)
1153 #define DMA_SRC_HW (DCON_SWHW_SEL*1)
1154 #define DCON_RELOAD (1 << 22) /* set auto-reload */
1155 #define SET_ATRELOAD (DCON_RELOAD*0)
1156 #define CLR_ATRELOAD (DCON_RELOAD*1)
1157 #define fDCON_DSZ Fld(2, 20)
1158 #define DSZ_BYTE 0
1159 #define DSZ_HALFWORD 1
1160 #define DSZ_WORD 2
1161 #define DSZ(x) FInsrt(x, fDCON_DSZ)
1162 #define readDSZ(x) FExtr(x, fDCON_DSZ)
1163 #define fDCON_TC Fld(20,0)
1164 #define TX_CNT(x) FInsrt(x, fDCON_TC)
1165 /* STATUS Register Definitions */
1166 #define fDSTAT_ST Fld(2,20) /* Status of DMA Controller */
1167 #define fDSTAT_TC Fld(20,0) /* Current value of transfer count */
1168 #define DMA_STATUS(chan) FExtr((DSTAT0 + (0x20 * chan)), fDSTAT_ST)
1169 #define DMA_BUSY (1 << 0)
1170 #define DMA_READY (0 << 0)
1171 #define DMA_CURR_TC(chan) FExtr((DSTAT0 + (0x20 * chan)), fDSTAT_TC)
1172 /* DMA Trigger Register Definitions */
1173 #define DMASKTRIG_STOP (1 << 2) /* Stop the DMA operation */
1174 #define DMA_STOP (DMASKTRIG_STOP*1)
1175 #define DMA_STOP_CLR (DMASKTRIG_STOP*0)
1176 #define DMASKTRIG_ONOFF (1 << 1) /* DMA channel on/off */
1177 #define CHANNEL_ON (DMASKTRIG_ONOFF*1)
1178 #define CHANNEL_OFF (DMASKTRIG_ONOFF*0)
1179 #define DMASKTRIG_SW (1 << 0) /* Trigger DMA ch. in S/W req. mode */
1180 #define DMA_SW_REQ_CLR (DMASKTRIG_SW*0)
1181 #define DMA_SW_REQ (DMASKTRIG_SW*1)
1182
1183 /*
1184 * KeyIF - keypad interface
1185 * chapter 28
1186 */
1187 #define KEYDAT __REG(0x44900000)
1188 #define KEYINTC __REG(0x44900004)
1189 #define KEYFLT0 __REG(0x44900008)
1190 #define KEYFLT1 __REG(0x4490000C)
1191 #define fKEYDAT_KEYS Fld(5,0) /* RO : intput decoding data */
1192 #define KEYDAT_KEYS FExtr(KEYDAT, fKEYDAT_KEYS)
1193 #define KEYDAT_KEYVAL (1<<5) /* RO : 0=valid, 1=invalid */
1194 #define KEYDAT_KEYCLR (1<<6) /* WO : 0=noaction, 1=clear */
1195 #define KEYDAT_KEYEN (1<<7) /* RW : 0=disable, 1=enable */
1196 #define fKEYINTLV Fld(3,0)
1197 #define KEYINTLV_LL 0 /* low level */
1198 #define KEYINTLV_HL 1 /* high level */
1199 #define KEYINTLV_RE 2 /* rising edge */
1200 #define KEYINTLV_FE 4 /* falling edge */
1201 #define KEYINTLV_BE 6 /* both edges */
1202 #define KEYINTLV(x) FInsrt((x), fKEYINTLV)
1203 #define KEYINTEN (1<<3) /* interrupt enable */
1204 #define fKEYFLT_SELCLK Fld(1,0)
1205 #define SELCLK_RTC 0
1206 #define SELCLK_GCLK 1
1207 #define KEYFLT_SELCLK(x) FInsrt((x),fKEYFLT_SELCLK)
1208 #define KEYFLT_FILEN (1<<1)
1209 #define fKEYFLT_WIDTH Fld( 14,0)
1210 #define KEYFLT_WIDTH(x) FInsrt((x), fKEYFLT_WIDTH)
1211 #define KEYP_STAT (((GPDAT & 0x00FF0000) >> 16 ) & 0x7D )
1212
1213 /*
1214 * Video Post Processor ?
1215 *
1216 * chapter 26.
1217 */
1218 #define VP_MODE __REG(0x4a100000) /* RW */
1219 #define VP_RATIO_Y __REG(0x4a100004) /* RW */
1220 #define VP_RATIO_CB __REG(0x4a100008) /* RW */
1221 #define VP_RATIO_CR __REG(0x4a10000c) /* RW */
1222 #define VP_SRC_WIDTH __REG(0x4a100010) /* RW */
1223 #define VP_SRC_HEIGHT __REG(0x4a100014) /* RW */
1224 #define VP_DST_WIDTH __REG(0x4a100018) /* RW */
1225 #define VP_DST_HEIGHT __REG(0x4a10001c) /* RW */
1226 #define VP_START_Y1 __REG(0x4a100020) /* RW */
1227 #define VP_START_Y2 __REG(0x4a100024) /* RW */
1228 #define VP_START_Y3 __REG(0x4a100028) /* RW */
1229 #define VP_START_Y4 __REG(0x4a10002c) /* RW */
1230 #define VP_START_CB1 __REG(0x4a100030) /* RW */
1231 #define VP_START_CB2 __REG(0x4a100034) /* RW */
1232 #define VP_START_CB3 __REG(0x4a100038) /* RW */
1233 #define VP_START_CB4 __REG(0x4a10003c) /* RW */
1234 #define VP_START_CR1 __REG(0x4a100040) /* RW */
1235 #define VP_START_CR2 __REG(0x4a100044) /* RW */
1236 #define VP_START_CR3 __REG(0x4a100048) /* RW */
1237 #define VP_START_CR4 __REG(0x4a10004c) /* RW */
1238 #define VP_START_RGB1 __REG(0x4a100050) /* RW */
1239 #define VP_START_RGB2 __REG(0x4a100054) /* RW */
1240 #define VP_START_RGB3 __REG(0x4a100058) /* RW */
1241 #define VP_START_RGB4 __REG(0x4a10005c) /* RW */
1242 #define VP_END_Y1 __REG(0x4a100060) /* RW */
1243 #define VP_END_Y2 __REG(0x4a100064) /* RW */
1244 #define VP_END_Y3 __REG(0x4a100068) /* RW */
1245 #define VP_END_Y4 __REG(0x4a10006c) /* RW */
1246 #define VP_END_CB1 __REG(0x4a100070) /* RW */
1247 #define VP_END_CB2 __REG(0x4a100074) /* RW */
1248 #define VP_END_CB3 __REG(0x4a100078) /* RW */
1249 #define VP_END_CB4 __REG(0x4a10007c) /* RW */
1250 #define VP_END_CR1 __REG(0x4a100080) /* RW */
1251 #define VP_END_CR2 __REG(0x4a100084) /* RW */
1252 #define VP_END_CR3 __REG(0x4a100088) /* RW */
1253 #define VP_END_CR4 __REG(0x4a10008c) /* RW */
1254 #define VP_END_RGB1 __REG(0x4a100090) /* RW */
1255 #define VP_END_RGB2 __REG(0x4a100094) /* RW */
1256 #define VP_END_RGB3 __REG(0x4a100098) /* RW */
1257 #define VP_END_RGB4 __REG(0x4a10009c) /* RW */
1258 #define VP_BYPASS __REG(0x4a1000f0) /* RW */
1259 #define VP_OFS_Y __REG(0x4a1000f4) /* RW */
1260 #define VP_OFS_CB __REG(0x4a1000f8) /* RW */
1261 #define VP_OFS_CR __REG(0x4a1000fc) /* RW */
1262 #define VP_OFS_RGB __REG(0x4a100100) /* RW */
1263
1264 #define VP_STY(__x) __REG(0x4a100020 + 4*(__x))
1265 #define VP_STCB(__x) __REG(0x4a100030 + 4*(__x))
1266 #define VP_STCR(__x) __REG(0x4a100040 + 4*(__x))
1267 #define VP_STRGB(__x) __REG(0x4a100050 + 4*(__x))
1268 #define VP_EDY(__x) __REG(0x4a100060 + 4*(__x))
1269 #define VP_EDCB(__x) __REG(0x4a100070 + 4*(__x))
1270 #define VP_EDCR(__x) __REG(0x4a100080 + 4*(__x))
1271 #define VP_EDRGB(__x) __REG(0x4a100090 + 4*(__x))
1272
1273 #define fVP_MODE_FRMCNT Fld(2,10)
1274 #define VP_MODE_FRMCNT(x) FExtr((x), fVP_MODE_FRMCNT)
1275 #define VP_MODE_BYPASSFC (1<<9)
1276 #define VP_MODE_BYPASSCSC (1<<8)
1277 #define VP_MODE_INT (1<<7)
1278 #define VP_MODE_INTPND (1<<6)
1279 #define VP_MODE_EN (1<<5)
1280 #define VP_MODE_ORGB24 (1<<4) /* output : 0=RGB16(565) , 1=RGB24 */
1281 #define VP_MODE_IFMT (1<<3) /* input : 0=YUV , 1=RGB */
1282 #define VP_MODE_INTLV (1<<2)
1283 #define VP_MODE_IRGB24 (1<<1) /* input : 0=RGB16(565) , 1=RGB24 */
1284 #define VP_MODE_IYUV (1<<0) /* if (VP_MODE_IFMT==0 && VP_MODE_INTLV==1)
1285 0=YUYV , 1=UYVY */
1286
1287 #define fVP_RATIO_V Fld(16,16)
1288 #define fVP_RATIO_H Fld(16,0)
1289 #define VP_RATIO_V(x) FInsrt((x), fVP_RATIO_V)
1290 #define VP_RATIO_H(x) FInsrt((x), fVP_RATIO_H)
1291
1292 #define fVP_IMG_SIZE_Y Fld(10,20)
1293 #define fVP_IMG_SIZE_CB Fld(10,10)
1294 #define fVP_IMG_SIZE_CR Fld(10,0)
1295 #define VP_IMG_SIZE_Y(x) FInsrt((x), fVP_IMG_SIZE_Y)
1296 #define VP_IMG_SIZE_CB(x) FInsrt((x), fVP_IMG_SIZE_CB)
1297 #define VP_IMG_SIZE_CR(x) FInsrt((x), fVP_IMG_SIZE_CR)
1298 #define VP_IMG_SIZE_R(x) FInsrt((x), fVP_IMG_SIZE_Y)
1299 #define VP_IMG_SIZE_G(x) FInsrt((x), fVP_IMG_SIZE_CB)
1300 #define VP_IMG_SIZE_B(x) FInsrt((x), fVP_IMG_SIZE_CR)
1301 #define VP_SIZE_XX(__x) ((__x)-1)
1302
1303 #define VP_BYPASS_EN (1<<24)
1304 #define fVP_BYPASS_LOW Fld(12,12)
1305 #define fVP_BYPASS_HIGH Fld(12,0)
1306 #define VP_BYPASS_LOW(x) FInsrt((x), fVP_BYPASS_LOW)
1307 #define VP_BYPASS_HIGH(x) FInsrt((x), fVP_BYPASS_HIGH)
1308
1309
1310 /*
1311 * IrDA Controller (Chapter 12)
1312 */
1313 #define IRDACNT __REG(0x41800000) /* Control */
1314 #define IRDAMDR __REG(0x41800004) /* Mode definition */
1315 #define IRDACNF __REG(0x41800008) /* IRQ//DMA configuration */
1316 #define IRDAIER __REG(0x4180000c) /* IRQ enable */
1317 #define IRDAIIR __REG(0x41800010) /* IRQ indentification */
1318 #define IRDALSR __REG(0x41800014) /* Line status */
1319 #define IRDAFCR __REG(0x41800018) /* FIFO control */
1320 #define IRDAPRL __REG(0x4180001c) /* Preamble length */
1321 #define IRDARBR __REG(0x41800020) /* Tx/Rx Buffer */
1322 #define IRDATXNO __REG(0x41800024) /* Total number of data bytes remained in Tx FIFO */
1323 #define IRDARXNO __REG(0x41800028) /* Total number of data remained in Rx FIFO (in bytes) */
1324 #define IRDATXFLL __REG(0x4180002c) /* Tx frame length (Low) */
1325 #define IRDATXFLH __REG(0x41800030) /* Tx frame length (High) */
1326 #define IRDARXFLL __REG(0x41800034) /* Rx frame length (Low) */
1327 #define IRDARXFLH __REG(0x41800038) /* Rx frame length (High */
1328 #define IRDATIME __REG(0x4180003c) /* Timing control */
1329
1330 /*
1331 * SPI Interface
1332 */
1333 #define SPCON0 __REG(0x44500000)
1334 #define SPSTA0 __REG(0x44500004)
1335 #define SPPIN0 __REG(0x44500008)
1336 #define SPPRE0 __REG(0x4450000C)
1337 #define SPTDAT0 __REG(0x44500010)
1338 #define SPRDAT0 __REG(0x44500014)
1339 #define SPCON1 __REG(0x44500020)
1340 #define SPSTA1 __REG(0x44500024)
1341 #define SPPIN1 __REG(0x44500028)
1342 #define SPPRE1 __REG(0x4450002C)
1343 #define SPTDAT1 __REG(0x44500030)
1344 #define SPRDAT1 __REG(0x44500034)
1345
1346 #define fSPCON_SMOD Fld(2,5) /* SPI mode select */
1347 #define SPCON_SMOD FMsk(fSPCON_SMOD)
1348 #define SPCON_SMOD_POLL FInsrt(0x0, fSPCON_SMOD)
1349 #define SPCON_SMOD_INT FInsrt(0x1, fSPCON_SMOD)
1350 #define SPCON_SMOD_DMA FInsrt(0x2, fSPCON_SMOD)
1351 #define SPCON_ENSCK (1 << 4)
1352 #define SPCON_MSTR (1 << 3)
1353 #define SPCON_CPOL (1 << 2)
1354 #define SPCON_CPOL_LOW (1 << 2)
1355 #define SPCON_CPOL_HIGH (0 << 2)
1356 #define SPCON_CPHA (1 << 1)
1357 #define SPCON_CPHA_FMTA (0 << 1)
1358 #define SPCON_CPHA_FMTB (1 << 1)
1359 #define SPCON_TAGD (1 << 0)
1360
1361 #define SPSTA_DCOL (1 << 2) /* Data Collision Error */
1362 #define SPSTA_MULF (1 << 1) /* Multi Master Error */
1363 #define SPSTA_READY (1 << 0) /* Data Tx/Rx ready */
1364
1365 /*
1366 * IIC Controller (Chapter 13)
1367 */
1368
1369 #define IICCON __REG(0x44600000)
1370 #define IICSTAT __REG(0x44600004)
1371 #define IICADD __REG(0x44600008)
1372 #define IICDS __REG(0x4460000C)
1373 #define IICADADLY __REG(0x44600010)
1374
1375 /*
1376 * Memory Stick Controller (Chapter 31)
1377 */
1378 #define _MS_BASE0 0x46100000
1379 #define _MS_BASE1 0x46108000
1380 #define bMS_CTL0(x) __REG(_MS_BASE0 + (x))
1381 #define bMS_CTL1(x) __REG(_MS_BASE1 + 4*(x))
1382 #define MSPRE bMS_CTL0(0) /* Prescaler Control */
1383 #define MSFINTCON bMS_CTL0(4) /* FIFO Interrupt Control */
1384 #define MS_TP_CMD bMS_CTL1(0) /* Transfer Protocol Command */
1385 #define MS_CTRL_STA bMS_CTL1(1) /* Control1 and Status */
1386 #define MS_DAT bMS_CTL1(2) /* Data FIFO */
1387 #define MS_INT bMS_CTL1(3) /* Interrupt Control and Status */
1388 #define MS_INS bMS_CTL1(4) /* INS port Control and Status */
1389 #define MS_ACMD bMS_CTL1(5) /* Auto Command/Polarity Control */
1390 #define MS_ATP_CMD bMS_CTL1(6) /* Auto Transfer Protocol Command */
1391
1392 #define MSPRE_EN (1 << 2) /* Prescaler control,
1393 0:Disable, 1:Enable. */
1394 #define MSPRE_VAL (0x3 << 0) /* Prescaler value */
1395 #define MSPRE_VAL1 (0x0 << 0) /* 1/1 */
1396 #define MSPRE_VAL2 (0x1 << 0) /* 1/2 */
1397 #define MSPRE_VAL4 (0x2 << 0) /* 1/4 */
1398 #define MSPRE_VAL8 (0x3 << 0) /* 1/8 */
1399
1400 #define MSFINTCON_EN 0x1 /* FIFO interrupt control,
1401 0:only for XINT,
1402 1:FIFO interrupt enable */
1403
1404 #define MS_CTRL_RST (1 << 15) /* Internal logic reset */
1405 #define MS_CTRL_PWS (1 << 14) /* Power save mode */
1406 #define MS_CTRL_SIEN (1 << 13) /* Serial interface enable */
1407 #define MS_CTRL_NOCRC (1 << 11) /* INT_CRC disable */
1408 #define MS_CTRL_BSYCNT (0x7 << 8) /* Busy timeout count
1409 timeout time = BSYCNT*4+2[pclks] */
1410 #define fMS_CTRL_BSYCNT Fld(3,8)
1411 #define MS_CTRL_BSY(x) FInsrt((x), fMS_CTRL_BSYCNT)
1412 #define MS_INT_STA (1 << 7) /* interrupt generated */
1413 #define MS_DRQ_STA (1 << 6) /* DMA requested */
1414 #define MS_RBE_STA (1 << 3) /* Receive buffer empty */
1415 #define MS_RBF_STA (1 << 2) /* Receive buffer full */
1416 #define MS_TBE_STA (1 << 1) /* Transmit buffer empty */
1417 #define MS_TBF_STA (1 << 0) /* Transmit buffer full */
1418
1419 #define MS_INT_EN (1 << 15) /* Memory stick Interrupt enable */
1420 #define MS_TR_INTEN (1 << 14) /* Data transfer interrupt enable */
1421 #define MS_INS_INTEN (1 << 13) /* Insertion interrupt enable */
1422 #define MS_INT_P_END (1 << 7) /* Protocol end interrupt status
1423 0 = In progress 1 = Complete */
1424 #define MS_INT_SIF (1 << 6) /* Serial interface receive INTd */
1425 #define MS_INT_TR (1 << 5) /* Data transfer request INTd */
1426 #define MS_INT_INS (1 << 4) /* Insertion INTd */
1427 #define MS_INT_CRC (1 << 1) /* INT_CRC error */
1428 #define MS_INT_TOE (1 << 0) /* BUSY timeout error */
1429
1430 #define MS_INS_EN (1 << 12) /* INS port enable */
1431 #define MS_INS_STA (1 << 4) /* INS port status. 1:Low(Insert) */
1432
1433 #define MS_ACMD_EN (1 << 15) /* Auto Command op. enable */
1434 #define MS_ACMD_RISING (0 << 14) /* serial data input is rising Edge */
1435 #define MS_ACMD_FALLING (1 << 14) /* serial data input is falling Edge */
1436
1437 /*
1438 * Modem Interface (Chapter 19)
1439 */
1440 #define INT2AP __REG(0x41180000)
1441 #define INT2MDM __REG(0x41180004)
1442
1443 #define fINT2AP_ADR Fld(11,0) /* IRQ to AP address */
1444 #define INT2AP_ADR FMsk(fINT2AP_ADR)
1445 #define fINT2MDM_ADR Fld(11,0) /* IRQ to Modem address */
1446 #define INT2MDM_ADR FMsk(fINT2MDM_ADR)
1447
1448 /*
1449 * Power management
1450 */
1451 #define ALIVECON __REG(0x44800044)
1452 #define GPDATINSLEEP __REG(0x44800048)
1453 #define ENGPINSLEEP __REG(0x4480004c)
1454 #define GPUPINSLEEP __REG(0x44800050)
1455 #define DATRINSLEEP0 __REG(0x44800054)
1456 #define DATRINSLEEP1 __REG(0x44800058)
1457 #define OENINSLEEP0 __REG(0x4480005c)
1458 #define OENINSLEEP1 __REG(0x44800060)
1459 #define ENPUINSLEEP __REG(0x44800064)
1460 #define RSTCNT __REG(0x44800068)
1461
1462 #endif /* _S3C24A0_H_ */
MOXA 2.6.19 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz