include/asm-arm/arch-atmel/hardware.h

   1 /*
   2  * linux/include/asm-arm/arch-atmel/hardware.h
   3  *
   4  * for Atmel AT91 series
   5  * 2001 Erwin Authried
   6  *
   7  * modified for linux 2.6 by Hyok S. Choi, 2004
   8  */
   9
  10 #ifndef __ASM_ARCH_HARDWARE_H
  11 #define __ASM_ARCH_HARDWARE_H
  12
  13 #include <asm/sizes.h>
  14
  15 #ifndef __ASSEMBLY__
  16
  17 /* the machine dependent  bootmem reserve and free routines */
  18 #define MACH_RESERVE_BOOTMEM()
  19 #define MACH_FREE_BOOTMEM()
  20
  21 /* yes, freeing initmem is okay */
  22 #define DO_FREE_INITMEM()       (1)
  23
  24 #endif
  25
  26 #define ATMEL_MEM_SIZE     (CONFIG_DRAM_SIZE)
  27 #define MEM_SIZE            ATMEL_MEM_SIZE
  28 #define PA_SDRAM_BASE         CONFIG_DRAM_BASE
  29
  30 /* 0=TC0, 1=TC1, 2=TC2 */
  31 #define KERNEL_TIMER 1
  32
  33 #ifdef CONFIG_CPU_AT91X40
  34 #include "at91x40.h"
  35 #elif CONFIG_CPU_AT91X63
  36 #include "at91x63.h"
  37 #else
  38   #error "Configuration error: No CPU defined"
  39 #endif
  40
  41 /*
  42  ******************* COMMON PART ********************
  43  */
  44 #define AIC_SMR(i)  (AIC_BASE+i*4)
  45 #define AIC_IVR     (AIC_BASE+0x100)
  46 #define AIC_FVR     (AIC_BASE+0x104)
  47 #define AIC_ISR     (AIC_BASE+0x108)
  48 #define AIC_IPR     (AIC_BASE+0x10C)
  49 #define AIC_IMR     (AIC_BASE+0x110)
  50 #define AIC_CISR        (AIC_BASE+0x114)
  51 #define AIC_IECR        (AIC_BASE+0x120)
  52 #define AIC_IDCR        (AIC_BASE+0x124)
  53 #define AIC_ICCR        (AIC_BASE+0x128)
  54 #define AIC_ISCR        (AIC_BASE+0x12C)
  55 #define AIC_EOICR   (AIC_BASE+0x130)
  56
  57
  58 #ifndef __ASSEMBLER__
  59 struct at91_timer_channel
  60 {
  61         unsigned long ccr;                              // channel control register             (WO)
  62         unsigned long cmr;                              // channel mode register                (RW)
  63         unsigned long reserved[2];
  64         unsigned long cv;                               // counter value                                (RW)
  65         unsigned long ra;                               // register A                                   (RW)
  66         unsigned long rb;                               // register B                                   (RW)
  67         unsigned long rc;                               // register C                                   (RW)
  68         unsigned long sr;                               // status register                              (RO)
  69         unsigned long ier;                              // interrupt enable register    (WO)
  70         unsigned long idr;                              // interrupt disable register   (WO)
  71         unsigned long imr;                              // interrupt mask register              (RO)
  72 };
  73
  74 struct at91_timers
  75 {
  76         struct {
  77                 struct at91_timer_channel ch;
  78                 unsigned char padding[0x40-sizeof(struct at91_timer_channel)];
  79         } chans[3];
  80         unsigned  long bcr;                             // block control register               (WO)
  81         unsigned  long bmr;                             // block mode    register               (RW)
  82 };
  83 #endif
  84
  85 /*  TC control register */
  86 #define TC_SYNC (1)
  87
  88 /*  TC mode register */
  89 #define TC2XC2S(x)      (x & 0x3)
  90 #define TC1XC1S(x)      (x<<2 & 0xc)
  91 #define TC0XC0S(x)      (x<<4 & 0x30)
  92 #define TCNXCNS(timer,v) ((v) << (timer<<1))
  93
  94 /* TC channel control */
  95 #define TC_CLKEN        (1)
  96 #define TC_CLKDIS       (1<<1)
  97 #define TC_SWTRG        (1<<2)
  98
  99 /* TC interrupts enable/disable/mask and status registers */
 100 #define TC_MTIOB        (1<<18)
 101 #define TC_MTIOA        (1<<17)
 102 #define TC_CLKSTA       (1<<16)
 103
 104 #define TC_ETRGS        (1<<7)
 105 #define TC_LDRBS        (1<<6)
 106 #define TC_LDRAS        (1<<5)
 107 #define TC_CPCS         (1<<4)
 108 #define TC_CPBS         (1<<3)
 109 #define TC_CPAS         (1<<2)
 110 #define TC_LOVRS        (1<<1)
 111 #define TC_COVFS        (1)
 112
 113 /*
 114  *      USART registers
 115  */
 116
 117
 118 /*  US control register */
 119 #define US_SENDA        (1<<12)
 120 #define US_STTO         (1<<11)
 121 #define US_STPBRK       (1<<10)
 122 #define US_STTBRK       (1<<9)
 123 #define US_RSTSTA       (1<<8)
 124 #define US_TXDIS        (1<<7)
 125 #define US_TXEN         (1<<6)
 126 #define US_RXDIS        (1<<5)
 127 #define US_RXEN         (1<<4)
 128 #define US_RSTTX        (1<<3)
 129 #define US_RSTRX        (1<<2)
 130
 131 /* US mode register */
 132 #define US_CLK0         (1<<18)
 133 #define US_MODE9        (1<<17)
 134 #define US_CHMODE(x)(x<<14 & 0xc000)
 135 #define US_NBSTOP(x)(x<<12 & 0x3000)
 136 #define US_PAR(x)       (x<<9 & 0xe00)
 137 #define US_SYNC         (1<<8)
 138 #define US_CHRL(x)      (x<<6 & 0xc0)
 139 #define US_USCLKS(x)(x<<4 & 0x30)
 140
 141 /* US interrupts enable/disable/mask and status register */
 142 #define US_DMSI         (1<<10)
 143 #define US_TXEMPTY      (1<<9)
 144 #define US_TIMEOUT      (1<<8)
 145 #define US_PARE         (1<<7)
 146 #define US_FRAME        (1<<6)
 147 #define US_OVRE         (1<<5)
 148 #define US_ENDTX        (1<<4)
 149 #define US_ENDRX        (1<<3)
 150 #define US_RXBRK        (1<<2)
 151 #define US_TXRDY        (1<<1)
 152 #define US_RXRDY        (1)
 153
 154 #define US_ALL_INTS (US_DMSI|US_TXEMPTY|US_TIMEOUT|US_PARE|US_FRAME|US_OVRE|US_ENDTX|US_ENDRX|US_RXBRK|US_TXRDY|US_RXRDY)
 155
 156 #ifndef __ASSEMBLER__
 157 struct atmel_usart_regs{
 158         unsigned long cr;               // control
 159         unsigned long mr;               // mode
 160         unsigned long ier;              // interrupt enable
 161         unsigned long idr;              // interrupt disable
 162         unsigned long imr;              // interrupt mask
 163         unsigned long csr;              // channel status
 164         unsigned long rhr;              // receive holding
 165         unsigned long thr;              // tramsmit holding
 166         unsigned long brgr;             // baud rate generator
 167         unsigned long rtor;             // rx time-out
 168         unsigned long ttgr;             // tx time-guard
 169         unsigned long res1;
 170         unsigned long rpr;              // rx pointer
 171         unsigned long rcr;              // rx counter
 172         unsigned long tpr;              // tx pointer
 173         unsigned long tcr;              // tx counter
 174 };
 175
 176 static inline void at91_usart_init(volatile struct atmel_usart_regs *uart, int baudrate)
 177 {
 178
 179         uart->cr = US_TXDIS | US_RXDIS | US_RSTTX | US_RSTRX;
 180         /* clear Rx receive and Tx sent counters */
 181         uart->rcr = 0;
 182         uart->tcr = 0;
 183
 184         uart->idr = US_TXEMPTY;         /* tx disable */
 185         uart->idr = US_ENDRX | US_TIMEOUT; /* rx disable */
 186
 187         /* Set the serial port into a safe sane state */
 188         uart->mr = US_USCLKS(0) | US_CLK0 | US_CHMODE(0) | US_NBSTOP(0) |
 189                     US_PAR(4) | US_CHRL(3);
 190
 191         /* FIXME: uart->brgr = ARM_CLK/16/baudrate; */
 192         uart->brgr = ARM_CLK/16/9600;
 193
 194         uart->rtor = 20;                        // timeout = value * 4 *bit period
 195         uart->ttgr = 0;                         // no guard time
 196         uart->rcr = 0;
 197         uart->rpr = 0;
 198         uart->tcr = 0;
 199         uart->tpr = 0;
 200 #ifdef US_RTS
 201         uart->mc = 0;
 202 #endif
 203 }
 204
 205 static inline void at91_usart_putc(volatile struct atmel_usart_regs *uart, unsigned char c)
 206 {
 207        uart->cr=US_TXEN;
 208        uart->thr=c;
 209        while(1) {
 210                 if (uart->csr & US_TXEMPTY) break;
 211        }
 212 }
 213 #endif
 214
 215 #define PIO(i)          (1<<i)
 216
 217 #ifndef __ASSEMBLER__
 218 struct pio_regs{
 219         unsigned long per;
 220         unsigned long pdr;
 221         unsigned long psr;
 222         unsigned long res1;
 223         unsigned long oer;
 224         unsigned long odr;
 225         unsigned long osr;
 226         unsigned long res2;
 227         unsigned long ifer;
 228         unsigned long ifdr;
 229         unsigned long ifsr;
 230         unsigned long res3;
 231         unsigned long sodr;
 232         unsigned long codr;
 233         unsigned long odsr;
 234         unsigned long pdsr;
 235         unsigned long ier;
 236         unsigned long idr;
 237         unsigned long imr;
 238         unsigned long isr;
 239 };
 240 #endif
 241
 242 #ifndef __ASSEMBLER__
 243 struct pmc_regs{
 244         unsigned long scer;
 245         unsigned long scdr;
 246         unsigned long scsr;
 247         unsigned long reserved;
 248         unsigned long pcer;
 249         unsigned long pcdr;
 250         unsigned long pcsr;
 251 };
 252 #endif
 253
 254 #endif  /* _ASM_ARCH_HARDWARE_H */
 255
 256