arch/arm/mach-s3c44b0x/driver/rtl8019.h

   1
   2 #define SHIFT(x)        (x<<1)
   3
   4 #define BaseAddr        0x6000000
   5 #define RWPORT  (BaseAddr+SHIFT(0x10))  /* dma read write address, form 0x10 - 0x17 */
   6 #define RstAddr (BaseAddr+SHIFT(0x18))  /* reset register, 0x18, 0x1a, 0x1c, 0x1e even address is recommanded */
   7
   8 /* page 0 */
   9 #define Pstart  (BaseAddr+SHIFT(1))     /* page start */
  10 #define Pstop   (BaseAddr+SHIFT(2))     /* page stop */
  11 #define BNRY    (BaseAddr+SHIFT(3))
  12 #define TPSR    (BaseAddr+SHIFT(4))     /* transmit page start */
  13 #define TBCR0   (BaseAddr+SHIFT(5))
  14 #define TBCR1   (BaseAddr+SHIFT(6))
  15 #define ISR     (BaseAddr+SHIFT(7))     /* interrupt status register */
  16
  17 #define RSAR0   (BaseAddr+SHIFT(8))     /* dma read address */
  18 #define RSAR1   (BaseAddr+SHIFT(9))
  19 #define RBCR0   (BaseAddr+SHIFT(10))    /* dma read byte count */
  20 #define RBCR1   (BaseAddr+SHIFT(11))
  21
  22 #define RCR     (BaseAddr+SHIFT(12))    /* receive config */
  23 #define TCR     (BaseAddr+SHIFT(13))    /* transmit config */
  24 #define DCR     (BaseAddr+SHIFT(14))    /* data config */
  25 #define IMR     (BaseAddr+SHIFT(15))    /* interrupt mask */
  26
  27 #define ID8019L (BaseAddr+SHIFT(10))
  28 #define ID8019H (BaseAddr+SHIFT(11))
  29
  30 /* page 1 */
  31 #define PAR0    (BaseAddr+SHIFT(1))
  32 #define PAR1    (BaseAddr+SHIFT(2))
  33 #define PAR2    (BaseAddr+SHIFT(3))
  34 #define PAR3    (BaseAddr+SHIFT(4))
  35 #define PAR4    (BaseAddr+SHIFT(5))
  36 #define PAR6    (BaseAddr+SHIFT(6))
  37
  38 #define CURR    (BaseAddr+SHIFT(7))
  39 #define MAR0    (BaseAddr+SHIFT(8))
  40 #define MAR1    (BaseAddr+SHIFT(9))
  41 #define MAR2    (BaseAddr+SHIFT(10))
  42 #define MAR3    (BaseAddr+SHIFT(11))
  43 #define MAR4    (BaseAddr+SHIFT(12))
  44 #define MAR5    (BaseAddr+SHIFT(13))
  45 #define MAR6    (BaseAddr+SHIFT(14))
  46 #define MAR7    (BaseAddr+SHIFT(15))
  47
  48 /* page 2 */
  49
  50 /* page 3 */
  51 #define CR9346  (BaseAddr+SHIFT(1))
  52 #define CONFIG0 (BaseAddr+SHIFT(3))
  53 #define CONFIG1 (BaseAddr+SHIFT(4))
  54 #define CONFIG2 (BaseAddr+SHIFT(5))
  55 #define CONFIG3 (BaseAddr+SHIFT(6))