2 * Linux-DVB Driver for DiBcom's DiB9000 and demodulator-family.
4 * Copyright (C) 2005-10 DiBcom (http://www.dibcom.fr/)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation, version 2.
10 #include <linux/kernel.h>
11 #include <linux/i2c.h>
12 #include <linux/mutex.h>
15 #include "dvb_frontend.h"
18 #include "dibx000_common.h"
21 module_param(debug
, int, 0644);
22 MODULE_PARM_DESC(debug
, "turn on debugging (default: 0)");
24 #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB9000: "); printk(args); printk("\n"); } } while (0)
25 #define MAX_NUMBER_OF_FRONTENDS 6
28 struct i2c_adapter
*i2c_adap
;
35 #define DIB_LOCK struct mutex
36 #define DibAcquireLock(lock) mutex_lock_interruptible(lock)
37 #define DibReleaseLock(lock) mutex_unlock(lock)
38 #define DibInitLock(lock) mutex_init(lock)
39 #define DibFreeLock(lock)
41 struct dib9000_pid_ctrl
{
42 #define DIB9000_PID_FILTER_CTRL 0
43 #define DIB9000_PID_FILTER 1
50 struct dib9000_state
{
51 struct i2c_device i2c
;
53 struct dibx000_i2c_master i2c_master
;
54 struct i2c_adapter tuner_adap
;
55 struct i2c_adapter component_bus
;
60 enum frontend_tune_state tune_state
;
62 struct dvb_frontend_parametersContext channel_status
;
66 #define DIB9000_GPIO_DEFAULT_DIRECTIONS 0xffff
68 #define DIB9000_GPIO_DEFAULT_VALUES 0x0000
70 #define DIB9000_GPIO_DEFAULT_PWM_POS 0xffff
73 union { /* common for all chips */
79 struct dib9000_fe_memory_map
{
85 DIB_LOCK mbx_if_lock
; /* to protect read/write operations */
86 DIB_LOCK mbx_lock
; /* to protect the whole mailbox handling */
88 DIB_LOCK mem_lock
; /* to protect the memory accesses */
89 DIB_LOCK mem_mbx_lock
; /* to protect the memory-based mailbox */
91 #define MBX_MAX_WORDS (256 - 200 - 2)
92 #define DIB9000_MSG_CACHE_SIZE 2
93 u16 message_cache
[DIB9000_MSG_CACHE_SIZE
][MBX_MAX_WORDS
];
98 union { /* common for all platforms */
100 struct dib9000_config cfg
;
104 struct dvb_frontend
*fe
[MAX_NUMBER_OF_FRONTENDS
];
105 u16 component_bus_speed
;
107 /* for the I2C transfer */
108 struct i2c_msg msg
[2];
109 u8 i2c_write_buffer
[255];
110 u8 i2c_read_buffer
[255];
112 u8 get_frontend_internal
;
113 struct dib9000_pid_ctrl pid_ctrl
[10];
114 s8 pid_ctrl_index
; /* -1: empty list; -2: do not use the list */
117 static const u32 fe_info
[44] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
118 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
119 0, 0, 0, 0, 0, 0, 0, 0
122 enum dib9000_power_mode
{
123 DIB9000_POWER_ALL
= 0,
126 DIB9000_POWER_INTERF_ANALOG_AGC
,
127 DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD
,
128 DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD
,
129 DIB9000_POWER_INTERFACE_ONLY
,
132 enum dib9000_out_messages
{
134 OUT_MSG_HOST_BUF_FAIL
,
136 OUT_MSG_BRIDGE_I2C_W
,
137 OUT_MSG_BRIDGE_I2C_R
,
138 OUT_MSG_BRIDGE_APB_W
,
139 OUT_MSG_BRIDGE_APB_R
,
140 OUT_MSG_SCAN_CHANNEL
,
145 OUT_MSG_ENABLE_TIME_SLICE
,
147 OUT_MSG_FE_CHANNEL_SEARCH
,
148 OUT_MSG_FE_CHANNEL_TUNE
,
156 OUT_MSG_ENABLE_DIVERSITY
,
157 OUT_MSG_SET_OUTPUT_MODE
,
158 OUT_MSG_SET_PRIORITARY_CHANNEL
,
163 enum dib9000_in_messages
{
167 IN_MSG_ACK_FREE_ITEM
,
170 IN_MSG_RAWTS_MONITOR
,
171 IN_MSG_END_BRIDGE_I2C_RW
,
172 IN_MSG_END_BRIDGE_APB_RW
,
177 IN_MSG_FE_FW_DL_DONE
,
179 IN_MSG_ACK_CHANGE_SVC
,
183 /* memory_access requests */
184 #define FE_MM_W_CHANNEL 0
185 #define FE_MM_W_FE_INFO 1
186 #define FE_MM_RW_SYNC 2
188 #define FE_SYNC_CHANNEL 1
189 #define FE_SYNC_W_GENERIC_MONIT 2
190 #define FE_SYNC_COMPONENT_ACCESS 3
192 #define FE_MM_R_CHANNEL_SEARCH_STATE 3
193 #define FE_MM_R_CHANNEL_UNION_CONTEXT 4
194 #define FE_MM_R_FE_INFO 5
195 #define FE_MM_R_FE_MONITOR 6
197 #define FE_MM_W_CHANNEL_HEAD 7
198 #define FE_MM_W_CHANNEL_UNION 8
199 #define FE_MM_W_CHANNEL_CONTEXT 9
200 #define FE_MM_R_CHANNEL_UNION 10
201 #define FE_MM_R_CHANNEL_CONTEXT 11
202 #define FE_MM_R_CHANNEL_TUNE_STATE 12
204 #define FE_MM_R_GENERIC_MONITORING_SIZE 13
205 #define FE_MM_W_GENERIC_MONITORING 14
206 #define FE_MM_R_GENERIC_MONITORING 15
208 #define FE_MM_W_COMPONENT_ACCESS 16
209 #define FE_MM_RW_COMPONENT_ACCESS_BUFFER 17
210 static int dib9000_risc_apb_access_read(struct dib9000_state
*state
, u32 address
, u16 attribute
, const u8
* tx
, u32 txlen
, u8
* b
, u32 len
);
211 static int dib9000_risc_apb_access_write(struct dib9000_state
*state
, u32 address
, u16 attribute
, const u8
* b
, u32 len
);
213 static u16
to_fw_output_mode(u16 mode
)
218 case OUTMODE_MPEG2_PAR_GATED_CLK
:
220 case OUTMODE_MPEG2_PAR_CONT_CLK
:
222 case OUTMODE_MPEG2_SERIAL
:
224 case OUTMODE_DIVERSITY
:
226 case OUTMODE_MPEG2_FIFO
:
228 case OUTMODE_ANALOG_ADC
:
235 static u16
dib9000_read16_attr(struct dib9000_state
*state
, u16 reg
, u8
* b
, u32 len
, u16 attribute
)
237 u32 chunk_size
= 126;
241 if (state
->platform
.risc
.fw_is_running
&& (reg
< 1024))
242 return dib9000_risc_apb_access_read(state
, reg
, attribute
, NULL
, 0, b
, len
);
244 memset(state
->msg
, 0, 2 * sizeof(struct i2c_msg
));
245 state
->msg
[0].addr
= state
->i2c
.i2c_addr
>> 1;
246 state
->msg
[0].flags
= 0;
247 state
->msg
[0].buf
= state
->i2c_write_buffer
;
248 state
->msg
[0].len
= 2;
249 state
->msg
[1].addr
= state
->i2c
.i2c_addr
>> 1;
250 state
->msg
[1].flags
= I2C_M_RD
;
251 state
->msg
[1].buf
= b
;
252 state
->msg
[1].len
= len
;
254 state
->i2c_write_buffer
[0] = reg
>> 8;
255 state
->i2c_write_buffer
[1] = reg
& 0xff;
257 if (attribute
& DATA_BUS_ACCESS_MODE_8BIT
)
258 state
->i2c_write_buffer
[0] |= (1 << 5);
259 if (attribute
& DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT
)
260 state
->i2c_write_buffer
[0] |= (1 << 4);
263 l
= len
< chunk_size
? len
: chunk_size
;
264 state
->msg
[1].len
= l
;
265 state
->msg
[1].buf
= b
;
266 ret
= i2c_transfer(state
->i2c
.i2c_adap
, state
->msg
, 2) != 2 ? -EREMOTEIO
: 0;
268 dprintk("i2c read error on %d", reg
);
275 if (!(attribute
& DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT
))
277 } while ((ret
== 0) && len
);
282 static u16
dib9000_i2c_read16(struct i2c_device
*i2c
, u16 reg
)
284 struct i2c_msg msg
[2] = {
285 {.addr
= i2c
->i2c_addr
>> 1, .flags
= 0,
286 .buf
= i2c
->i2c_write_buffer
, .len
= 2},
287 {.addr
= i2c
->i2c_addr
>> 1, .flags
= I2C_M_RD
,
288 .buf
= i2c
->i2c_read_buffer
, .len
= 2},
291 i2c
->i2c_write_buffer
[0] = reg
>> 8;
292 i2c
->i2c_write_buffer
[1] = reg
& 0xff;
294 if (i2c_transfer(i2c
->i2c_adap
, msg
, 2) != 2) {
295 dprintk("read register %x error", reg
);
299 return (i2c
->i2c_read_buffer
[0] << 8) | i2c
->i2c_read_buffer
[1];
302 static inline u16
dib9000_read_word(struct dib9000_state
*state
, u16 reg
)
304 if (dib9000_read16_attr(state
, reg
, state
->i2c_read_buffer
, 2, 0) != 0)
306 return (state
->i2c_read_buffer
[0] << 8) | state
->i2c_read_buffer
[1];
309 static inline u16
dib9000_read_word_attr(struct dib9000_state
*state
, u16 reg
, u16 attribute
)
311 if (dib9000_read16_attr(state
, reg
, state
->i2c_read_buffer
, 2,
314 return (state
->i2c_read_buffer
[0] << 8) | state
->i2c_read_buffer
[1];
317 #define dib9000_read16_noinc_attr(state, reg, b, len, attribute) dib9000_read16_attr(state, reg, b, len, (attribute) | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
319 static u16
dib9000_write16_attr(struct dib9000_state
*state
, u16 reg
, const u8
* buf
, u32 len
, u16 attribute
)
321 u32 chunk_size
= 126;
325 if (state
->platform
.risc
.fw_is_running
&& (reg
< 1024)) {
326 if (dib9000_risc_apb_access_write
327 (state
, reg
, DATA_BUS_ACCESS_MODE_16BIT
| DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT
| attribute
, buf
, len
) != 0)
332 memset(&state
->msg
[0], 0, sizeof(struct i2c_msg
));
333 state
->msg
[0].addr
= state
->i2c
.i2c_addr
>> 1;
334 state
->msg
[0].flags
= 0;
335 state
->msg
[0].buf
= state
->i2c_write_buffer
;
336 state
->msg
[0].len
= len
+ 2;
338 state
->i2c_write_buffer
[0] = (reg
>> 8) & 0xff;
339 state
->i2c_write_buffer
[1] = (reg
) & 0xff;
341 if (attribute
& DATA_BUS_ACCESS_MODE_8BIT
)
342 state
->i2c_write_buffer
[0] |= (1 << 5);
343 if (attribute
& DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT
)
344 state
->i2c_write_buffer
[0] |= (1 << 4);
347 l
= len
< chunk_size
? len
: chunk_size
;
348 state
->msg
[0].len
= l
+ 2;
349 memcpy(&state
->i2c_write_buffer
[2], buf
, l
);
351 ret
= i2c_transfer(state
->i2c
.i2c_adap
, state
->msg
, 1) != 1 ? -EREMOTEIO
: 0;
356 if (!(attribute
& DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT
))
358 } while ((ret
== 0) && len
);
363 static int dib9000_i2c_write16(struct i2c_device
*i2c
, u16 reg
, u16 val
)
365 struct i2c_msg msg
= {
366 .addr
= i2c
->i2c_addr
>> 1, .flags
= 0,
367 .buf
= i2c
->i2c_write_buffer
, .len
= 4
370 i2c
->i2c_write_buffer
[0] = (reg
>> 8) & 0xff;
371 i2c
->i2c_write_buffer
[1] = reg
& 0xff;
372 i2c
->i2c_write_buffer
[2] = (val
>> 8) & 0xff;
373 i2c
->i2c_write_buffer
[3] = val
& 0xff;
375 return i2c_transfer(i2c
->i2c_adap
, &msg
, 1) != 1 ? -EREMOTEIO
: 0;
378 static inline int dib9000_write_word(struct dib9000_state
*state
, u16 reg
, u16 val
)
380 u8 b
[2] = { val
>> 8, val
& 0xff };
381 return dib9000_write16_attr(state
, reg
, b
, 2, 0);
384 static inline int dib9000_write_word_attr(struct dib9000_state
*state
, u16 reg
, u16 val
, u16 attribute
)
386 u8 b
[2] = { val
>> 8, val
& 0xff };
387 return dib9000_write16_attr(state
, reg
, b
, 2, attribute
);
390 #define dib9000_write(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, 0)
391 #define dib9000_write16_noinc(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
392 #define dib9000_write16_noinc_attr(state, reg, buf, len, attribute) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | (attribute))
394 #define dib9000_mbx_send(state, id, data, len) dib9000_mbx_send_attr(state, id, data, len, 0)
395 #define dib9000_mbx_get_message(state, id, msg, len) dib9000_mbx_get_message_attr(state, id, msg, len, 0)
397 #define MAC_IRQ (1 << 1)
398 #define IRQ_POL_MSK (1 << 4)
400 #define dib9000_risc_mem_read_chunks(state, b, len) dib9000_read16_attr(state, 1063, b, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
401 #define dib9000_risc_mem_write_chunks(state, buf, len) dib9000_write16_attr(state, 1063, buf, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
403 static void dib9000_risc_mem_setup_cmd(struct dib9000_state
*state
, u32 addr
, u32 len
, u8 reading
)
407 /* dprintk("%d memcmd: %d %d %d\n", state->fe_id, addr, addr+len, len); */
413 b
[4] = (u8
) (addr
>> 8);
414 b
[5] = (u8
) (addr
& 0xff);
418 b
[12] = (u8
) (addr
>> 8);
419 b
[13] = (u8
) (addr
& 0xff);
424 b
[8] = (u8
) (addr
>> 8);
425 b
[9] = (u8
) (addr
& 0xff);
427 dib9000_write(state
, 1056, b
, 14);
429 dib9000_write_word(state
, 1056, (1 << 15) | 1);
430 state
->platform
.risc
.memcmd
= -1; /* if it was called directly reset it - to force a future setup-call to set it */
433 static void dib9000_risc_mem_setup(struct dib9000_state
*state
, u8 cmd
)
435 struct dib9000_fe_memory_map
*m
= &state
->platform
.risc
.fe_mm
[cmd
& 0x7f];
436 /* decide whether we need to "refresh" the memory controller */
437 if (state
->platform
.risc
.memcmd
== cmd
&& /* same command */
438 !(cmd
& 0x80 && m
->size
< 67)) /* and we do not want to read something with less than 67 bytes looping - working around a bug in the memory controller */
440 dib9000_risc_mem_setup_cmd(state
, m
->addr
, m
->size
, cmd
& 0x80);
441 state
->platform
.risc
.memcmd
= cmd
;
444 static int dib9000_risc_mem_read(struct dib9000_state
*state
, u8 cmd
, u8
* b
, u16 len
)
446 if (!state
->platform
.risc
.fw_is_running
)
449 if (DibAcquireLock(&state
->platform
.risc
.mem_lock
) < 0) {
450 dprintk("could not get the lock");
453 dib9000_risc_mem_setup(state
, cmd
| 0x80);
454 dib9000_risc_mem_read_chunks(state
, b
, len
);
455 DibReleaseLock(&state
->platform
.risc
.mem_lock
);
459 static int dib9000_risc_mem_write(struct dib9000_state
*state
, u8 cmd
, const u8
* b
)
461 struct dib9000_fe_memory_map
*m
= &state
->platform
.risc
.fe_mm
[cmd
];
462 if (!state
->platform
.risc
.fw_is_running
)
465 if (DibAcquireLock(&state
->platform
.risc
.mem_lock
) < 0) {
466 dprintk("could not get the lock");
469 dib9000_risc_mem_setup(state
, cmd
);
470 dib9000_risc_mem_write_chunks(state
, b
, m
->size
);
471 DibReleaseLock(&state
->platform
.risc
.mem_lock
);
475 static int dib9000_firmware_download(struct dib9000_state
*state
, u8 risc_id
, u16 key
, const u8
* code
, u32 len
)
484 /* config crtl reg */
485 dib9000_write_word(state
, 1024 + offs
, 0x000f);
486 dib9000_write_word(state
, 1025 + offs
, 0);
487 dib9000_write_word(state
, 1031 + offs
, key
);
489 dprintk("going to download %dB of microcode", len
);
490 if (dib9000_write16_noinc(state
, 1026 + offs
, (u8
*) code
, (u16
) len
) != 0) {
491 dprintk("error while downloading microcode for RISC %c", 'A' + risc_id
);
495 dprintk("Microcode for RISC %c loaded", 'A' + risc_id
);
500 static int dib9000_mbx_host_init(struct dib9000_state
*state
, u8 risc_id
)
512 dib9000_write_word(state
, 1027 + mbox_offs
, 0x8000);
514 /* Read reset status */
516 reset_reg
= dib9000_read_word(state
, 1027 + mbox_offs
);
518 } while ((reset_reg
& 0x8000) && --tries
);
520 if (reset_reg
& 0x8000) {
521 dprintk("MBX: init ERROR, no response from RISC %c", 'A' + risc_id
);
524 dprintk("MBX: initialized");
528 #define MAX_MAILBOX_TRY 100
529 static int dib9000_mbx_send_attr(struct dib9000_state
*state
, u8 id
, u16
* data
, u8 len
, u16 attr
)
537 if (!state
->platform
.risc
.fw_is_running
)
540 if (DibAcquireLock(&state
->platform
.risc
.mbx_if_lock
) < 0) {
541 dprintk("could not get the lock");
544 tmp
= MAX_MAILBOX_TRY
;
546 size
= dib9000_read_word_attr(state
, 1043, attr
) & 0xff;
547 if ((size
+ len
+ 1) > MBX_MAX_WORDS
&& --tmp
) {
548 dprintk("MBX: RISC mbx full, retrying");
554 /*dprintk( "MBX: size: %d", size); */
561 dprintk("--> %02x %d ", id
, len
+ 1);
562 for (i
= 0; i
< len
; i
++)
563 dprintk("%04x ", data
[i
]);
567 /* byte-order conversion - works on big (where it is not necessary) or little endian */
569 for (i
= 0; i
< len
; i
++) {
578 if (dib9000_write16_noinc_attr(state
, 1045, b
, 2, attr
) != 0 || dib9000_write16_noinc_attr(state
, 1045, (u8
*) data
, len
* 2, attr
) != 0) {
583 /* update register nb_mes_in_RX */
584 ret
= (u8
) dib9000_write_word_attr(state
, 1043, 1 << 14, attr
);
587 DibReleaseLock(&state
->platform
.risc
.mbx_if_lock
);
592 static u8
dib9000_mbx_read(struct dib9000_state
*state
, u16
* data
, u8 risc_id
, u16 attr
)
602 if (!state
->platform
.risc
.fw_is_running
)
605 if (DibAcquireLock(&state
->platform
.risc
.mbx_if_lock
) < 0) {
606 dprintk("could not get the lock");
614 /* Length and type in the first word */
615 *data
= dib9000_read_word_attr(state
, 1029 + mc_base
, attr
);
618 if (size
<= MBX_MAX_WORDS
) {
620 size
--; /* Initial word already read */
622 dib9000_read16_noinc_attr(state
, 1029 + mc_base
, (u8
*) data
, size
* 2, attr
);
624 /* to word conversion */
625 for (i
= 0; i
< size
; i
++) {
627 *data
= (tmp
>> 8) | (tmp
<< 8);
633 for (i
= 0; i
< size
+ 1; i
++)
634 dprintk("%04x ", d
[i
]);
638 dprintk("MBX: message is too big for message cache (%d), flushing message", size
);
639 size
--; /* Initial word already read */
641 dib9000_read16_noinc_attr(state
, 1029 + mc_base
, (u8
*) data
, 2, attr
);
643 /* Update register nb_mes_in_TX */
644 dib9000_write_word_attr(state
, 1028 + mc_base
, 1 << 14, attr
);
646 DibReleaseLock(&state
->platform
.risc
.mbx_if_lock
);
651 static int dib9000_risc_debug_buf(struct dib9000_state
*state
, u16
* data
, u8 size
)
653 u32 ts
= data
[1] << 16 | data
[0];
654 char *b
= (char *)&data
[2];
656 b
[2 * (size
- 2) - 1] = '\0'; /* Bullet proof the buffer */
661 dprintk("RISC%d: %d.%04d %s", state
->fe_id
, ts
/ 10000, ts
% 10000, *b
? b
: "<emtpy>");
665 static int dib9000_mbx_fetch_to_cache(struct dib9000_state
*state
, u16 attr
)
670 /* find a free slot */
671 for (i
= 0; i
< DIB9000_MSG_CACHE_SIZE
; i
++) {
672 block
= state
->platform
.risc
.message_cache
[i
];
674 size
= dib9000_mbx_read(state
, block
, 1, attr
);
676 /* dprintk( "MBX: fetched %04x message to cache", *block); */
678 switch (*block
>> 8) {
679 case IN_MSG_DEBUG_BUF
:
680 dib9000_risc_debug_buf(state
, block
+ 1, size
); /* debug-messages are going to be printed right away */
681 *block
= 0; /* free the block */
684 case IN_MSG_DATA
: /* FE-TRACE */
685 dib9000_risc_data_process(state
, block
+ 1, size
);
696 dprintk("MBX: no free cache-slot found for new message...");
700 static u8
dib9000_mbx_count(struct dib9000_state
*state
, u8 risc_id
, u16 attr
)
703 return (u8
) (dib9000_read_word_attr(state
, 1028, attr
) >> 10) & 0x1f; /* 5 bit field */
705 return (u8
) (dib9000_read_word_attr(state
, 1044, attr
) >> 8) & 0x7f; /* 7 bit field */
708 static int dib9000_mbx_process(struct dib9000_state
*state
, u16 attr
)
712 if (!state
->platform
.risc
.fw_is_running
)
715 if (DibAcquireLock(&state
->platform
.risc
.mbx_lock
) < 0) {
716 dprintk("could not get the lock");
720 if (dib9000_mbx_count(state
, 1, attr
)) /* 1=RiscB */
721 ret
= dib9000_mbx_fetch_to_cache(state
, attr
);
723 dib9000_read_word_attr(state
, 1229, attr
); /* Clear the IRQ */
725 /* dprintk( "cleared IRQ: %x", tmp); */
726 DibReleaseLock(&state
->platform
.risc
.mbx_lock
);
731 static int dib9000_mbx_get_message_attr(struct dib9000_state
*state
, u16 id
, u16
* msg
, u8
* size
, u16 attr
)
739 /* dib9000_mbx_get_from_cache(); */
740 for (i
= 0; i
< DIB9000_MSG_CACHE_SIZE
; i
++) {
741 block
= state
->platform
.risc
.message_cache
[i
];
742 if ((*block
>> 8) == id
) {
743 *size
= (*block
& 0xff) - 1;
744 memcpy(msg
, block
+ 1, (*size
) * 2);
745 *block
= 0; /* free the block */
746 i
= 0; /* signal that we found a message */
754 if (dib9000_mbx_process(state
, attr
) == -1) /* try to fetch one message - if any */
760 dprintk("waiting for message %d timed out", id
);
767 static int dib9000_risc_check_version(struct dib9000_state
*state
)
773 if (dib9000_mbx_send(state
, OUT_MSG_REQ_VERSION
, &fw_version
, 1) != 0)
776 if (dib9000_mbx_get_message(state
, IN_MSG_VERSION
, (u16
*) r
, &size
) < 0)
779 fw_version
= (r
[0] << 8) | r
[1];
780 dprintk("RISC: ver: %d.%02d (IC: %d)", fw_version
>> 10, fw_version
& 0x3ff, (r
[2] << 8) | r
[3]);
782 if ((fw_version
>> 10) != 7)
785 switch (fw_version
& 0x3ff) {
794 dprintk("RISC: invalid firmware version");
798 dprintk("RISC: valid firmware version");
802 static int dib9000_fw_boot(struct dib9000_state
*state
, const u8
* codeA
, u32 lenA
, const u8
* codeB
, u32 lenB
)
804 /* Reconfig pool mac ram */
805 dib9000_write_word(state
, 1225, 0x02); /* A: 8k C, 4 k D - B: 32k C 6 k D - IRAM 96k */
806 dib9000_write_word(state
, 1226, 0x05);
808 /* Toggles IP crypto to Host APB interface. */
809 dib9000_write_word(state
, 1542, 1);
811 /* Set jump and no jump in the dma box */
812 dib9000_write_word(state
, 1074, 0);
813 dib9000_write_word(state
, 1075, 0);
815 /* Set MAC as APB Master. */
816 dib9000_write_word(state
, 1237, 0);
818 /* Reset the RISCs */
820 dib9000_write_word(state
, 1024, 2);
822 dib9000_write_word(state
, 1024, 15);
824 dib9000_write_word(state
, 1040, 2);
827 dib9000_firmware_download(state
, 0, 0x1234, codeA
, lenA
);
829 dib9000_firmware_download(state
, 1, 0x1234, codeB
, lenB
);
833 dib9000_write_word(state
, 1024, 0);
835 dib9000_write_word(state
, 1040, 0);
838 if (dib9000_mbx_host_init(state
, 0) != 0)
841 if (dib9000_mbx_host_init(state
, 1) != 0)
845 state
->platform
.risc
.fw_is_running
= 1;
847 if (dib9000_risc_check_version(state
) != 0)
850 state
->platform
.risc
.memcmd
= 0xff;
854 static u16
dib9000_identify(struct i2c_device
*client
)
858 value
= dib9000_i2c_read16(client
, 896);
859 if (value
!= 0x01b3) {
860 dprintk("wrong Vendor ID (0x%x)", value
);
864 value
= dib9000_i2c_read16(client
, 897);
865 if (value
!= 0x4000 && value
!= 0x4001 && value
!= 0x4002 && value
!= 0x4003 && value
!= 0x4004 && value
!= 0x4005) {
866 dprintk("wrong Device ID (0x%x)", value
);
870 /* protect this driver to be used with 7000PC */
871 if (value
== 0x4000 && dib9000_i2c_read16(client
, 769) == 0x4000) {
872 dprintk("this driver does not work with DiB7000PC");
878 dprintk("found DiB7000MA/PA/MB/PB");
881 dprintk("found DiB7000HC");
884 dprintk("found DiB7000MC");
887 dprintk("found DiB9000A");
890 dprintk("found DiB9000H");
893 dprintk("found DiB9000M");
900 static void dib9000_set_power_mode(struct dib9000_state
*state
, enum dib9000_power_mode mode
)
902 /* by default everything is going to be powered off */
903 u16 reg_903
= 0x3fff, reg_904
= 0xffff, reg_905
= 0xffff, reg_906
;
906 if (state
->revision
== 0x4003 || state
->revision
== 0x4004 || state
->revision
== 0x4005)
911 reg_906
= dib9000_read_word(state
, 906 + offset
) | 0x3; /* keep settings for RISC */
913 /* now, depending on the requested mode, we power on */
915 /* power up everything in the demod */
916 case DIB9000_POWER_ALL
:
923 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO or SRAM) */
924 case DIB9000_POWER_INTERFACE_ONLY
: /* TODO power up either SDIO or I2C or SRAM */
925 reg_905
&= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 2));
928 case DIB9000_POWER_INTERF_ANALOG_AGC
:
929 reg_903
&= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10));
930 reg_905
&= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 2));
931 reg_906
&= ~((1 << 0));
934 case DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD
:
938 reg_906
&= ~((1 << 0));
941 case DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD
:
945 reg_906
&= ~((1 << 0));
948 case DIB9000_POWER_NO
:
952 /* always power down unused parts */
953 if (!state
->platform
.host
.mobile_mode
)
954 reg_904
|= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1);
956 /* P_sdio_select_clk = 0 on MC and after */
957 if (state
->revision
!= 0x4000)
960 dib9000_write_word(state
, 903 + offset
, reg_903
);
961 dib9000_write_word(state
, 904 + offset
, reg_904
);
962 dib9000_write_word(state
, 905 + offset
, reg_905
);
963 dib9000_write_word(state
, 906 + offset
, reg_906
);
966 static int dib9000_fw_reset(struct dvb_frontend
*fe
)
968 struct dib9000_state
*state
= fe
->demodulator_priv
;
970 dib9000_write_word(state
, 1817, 0x0003);
972 dib9000_write_word(state
, 1227, 1);
973 dib9000_write_word(state
, 1227, 0);
975 switch ((state
->revision
= dib9000_identify(&state
->i2c
))) {
985 /* reset the i2c-master to use the host interface */
986 dibx000_reset_i2c_master(&state
->i2c_master
);
988 dib9000_set_power_mode(state
, DIB9000_POWER_ALL
);
990 /* unforce divstr regardless whether i2c enumeration was done or not */
991 dib9000_write_word(state
, 1794, dib9000_read_word(state
, 1794) & ~(1 << 1));
992 dib9000_write_word(state
, 1796, 0);
993 dib9000_write_word(state
, 1805, 0x805);
995 /* restart all parts */
996 dib9000_write_word(state
, 898, 0xffff);
997 dib9000_write_word(state
, 899, 0xffff);
998 dib9000_write_word(state
, 900, 0x0001);
999 dib9000_write_word(state
, 901, 0xff19);
1000 dib9000_write_word(state
, 902, 0x003c);
1002 dib9000_write_word(state
, 898, 0);
1003 dib9000_write_word(state
, 899, 0);
1004 dib9000_write_word(state
, 900, 0);
1005 dib9000_write_word(state
, 901, 0);
1006 dib9000_write_word(state
, 902, 0);
1008 dib9000_write_word(state
, 911, state
->chip
.d9
.cfg
.if_drives
);
1010 dib9000_set_power_mode(state
, DIB9000_POWER_INTERFACE_ONLY
);
1015 static int dib9000_risc_apb_access_read(struct dib9000_state
*state
, u32 address
, u16 attribute
, const u8
* tx
, u32 txlen
, u8
* b
, u32 len
)
1020 if (address
>= 1024 || !state
->platform
.risc
.fw_is_running
)
1023 /* dprintk( "APB access thru rd fw %d %x", address, attribute); */
1025 mb
[0] = (u16
) address
;
1027 dib9000_mbx_send_attr(state
, OUT_MSG_BRIDGE_APB_R
, mb
, 2, attribute
);
1028 switch (dib9000_mbx_get_message_attr(state
, IN_MSG_END_BRIDGE_APB_RW
, mb
, &s
, attribute
)) {
1031 for (i
= 0; i
< s
; i
++) {
1032 b
[i
* 2] = (mb
[i
+ 1] >> 8) & 0xff;
1033 b
[i
* 2 + 1] = (mb
[i
+ 1]) & 0xff;
1042 static int dib9000_risc_apb_access_write(struct dib9000_state
*state
, u32 address
, u16 attribute
, const u8
* b
, u32 len
)
1047 if (address
>= 1024 || !state
->platform
.risc
.fw_is_running
)
1050 /* dprintk( "APB access thru wr fw %d %x", address, attribute); */
1052 mb
[0] = (unsigned short)address
;
1053 for (i
= 0; i
< len
&& i
< 20; i
+= 2)
1054 mb
[1 + (i
/ 2)] = (b
[i
] << 8 | b
[i
+ 1]);
1056 dib9000_mbx_send_attr(state
, OUT_MSG_BRIDGE_APB_W
, mb
, 1 + len
/ 2, attribute
);
1057 return dib9000_mbx_get_message_attr(state
, IN_MSG_END_BRIDGE_APB_RW
, mb
, &s
, attribute
) == 1 ? 0 : -EINVAL
;
1060 static int dib9000_fw_memmbx_sync(struct dib9000_state
*state
, u8 i
)
1064 if (!state
->platform
.risc
.fw_is_running
)
1066 dib9000_risc_mem_write(state
, FE_MM_RW_SYNC
, &i
);
1068 dib9000_risc_mem_read(state
, FE_MM_RW_SYNC
, state
->i2c_read_buffer
, 1);
1069 } while (state
->i2c_read_buffer
[0] && index_loop
--);
1076 static int dib9000_fw_init(struct dib9000_state
*state
)
1078 struct dibGPIOFunction
*f
;
1083 if (dib9000_fw_boot(state
, NULL
, 0, state
->chip
.d9
.cfg
.microcode_B_fe_buffer
, state
->chip
.d9
.cfg
.microcode_B_fe_size
) != 0)
1086 /* initialize the firmware */
1087 for (i
= 0; i
< ARRAY_SIZE(state
->chip
.d9
.cfg
.gpio_function
); i
++) {
1088 f
= &state
->chip
.d9
.cfg
.gpio_function
[i
];
1090 switch (f
->function
) {
1091 case BOARD_GPIO_FUNCTION_COMPONENT_ON
:
1092 b
[0] = (u16
) f
->mask
;
1093 b
[1] = (u16
) f
->direction
;
1094 b
[2] = (u16
) f
->value
;
1096 case BOARD_GPIO_FUNCTION_COMPONENT_OFF
:
1097 b
[3] = (u16
) f
->mask
;
1098 b
[4] = (u16
) f
->direction
;
1099 b
[5] = (u16
) f
->value
;
1104 if (dib9000_mbx_send(state
, OUT_MSG_CONF_GPIO
, b
, 15) != 0)
1108 b
[0] = state
->chip
.d9
.cfg
.subband
.size
; /* type == 0 -> GPIO - PWM not yet supported */
1109 for (i
= 0; i
< state
->chip
.d9
.cfg
.subband
.size
; i
++) {
1110 b
[1 + i
* 4] = state
->chip
.d9
.cfg
.subband
.subband
[i
].f_mhz
;
1111 b
[2 + i
* 4] = (u16
) state
->chip
.d9
.cfg
.subband
.subband
[i
].gpio
.mask
;
1112 b
[3 + i
* 4] = (u16
) state
->chip
.d9
.cfg
.subband
.subband
[i
].gpio
.direction
;
1113 b
[4 + i
* 4] = (u16
) state
->chip
.d9
.cfg
.subband
.subband
[i
].gpio
.value
;
1115 b
[1 + i
* 4] = 0; /* fe_id */
1116 if (dib9000_mbx_send(state
, OUT_MSG_SUBBAND_SEL
, b
, 2 + 4 * i
) != 0)
1119 /* 0 - id, 1 - no_of_frontends */
1120 b
[0] = (0 << 8) | 1;
1121 /* 0 = i2c-address demod, 0 = tuner */
1122 b
[1] = (0 << 8) | (0);
1123 b
[2] = (u16
) (((state
->chip
.d9
.cfg
.xtal_clock_khz
* 1000) >> 16) & 0xffff);
1124 b
[3] = (u16
) (((state
->chip
.d9
.cfg
.xtal_clock_khz
* 1000)) & 0xffff);
1125 b
[4] = (u16
) ((state
->chip
.d9
.cfg
.vcxo_timer
>> 16) & 0xffff);
1126 b
[5] = (u16
) ((state
->chip
.d9
.cfg
.vcxo_timer
) & 0xffff);
1127 b
[6] = (u16
) ((state
->chip
.d9
.cfg
.timing_frequency
>> 16) & 0xffff);
1128 b
[7] = (u16
) ((state
->chip
.d9
.cfg
.timing_frequency
) & 0xffff);
1129 b
[29] = state
->chip
.d9
.cfg
.if_drives
;
1130 if (dib9000_mbx_send(state
, OUT_MSG_INIT_DEMOD
, b
, ARRAY_SIZE(b
)) != 0)
1133 if (dib9000_mbx_send(state
, OUT_MSG_FE_FW_DL
, NULL
, 0) != 0)
1136 if (dib9000_mbx_get_message(state
, IN_MSG_FE_FW_DL_DONE
, b
, &size
) < 0)
1139 if (size
> ARRAY_SIZE(b
)) {
1140 dprintk("error : firmware returned %dbytes needed but the used buffer has only %dbytes\n Firmware init ABORTED", size
,
1141 (int)ARRAY_SIZE(b
));
1145 for (i
= 0; i
< size
; i
+= 2) {
1146 state
->platform
.risc
.fe_mm
[i
/ 2].addr
= b
[i
+ 0];
1147 state
->platform
.risc
.fe_mm
[i
/ 2].size
= b
[i
+ 1];
1153 static void dib9000_fw_set_channel_head(struct dib9000_state
*state
)
1156 u32 freq
= state
->fe
[0]->dtv_property_cache
.frequency
/ 1000;
1157 if (state
->fe_id
% 2)
1160 b
[0] = (u8
) ((freq
>> 0) & 0xff);
1161 b
[1] = (u8
) ((freq
>> 8) & 0xff);
1162 b
[2] = (u8
) ((freq
>> 16) & 0xff);
1163 b
[3] = (u8
) ((freq
>> 24) & 0xff);
1164 b
[4] = (u8
) ((state
->fe
[0]->dtv_property_cache
.bandwidth_hz
/ 1000 >> 0) & 0xff);
1165 b
[5] = (u8
) ((state
->fe
[0]->dtv_property_cache
.bandwidth_hz
/ 1000 >> 8) & 0xff);
1166 b
[6] = (u8
) ((state
->fe
[0]->dtv_property_cache
.bandwidth_hz
/ 1000 >> 16) & 0xff);
1167 b
[7] = (u8
) ((state
->fe
[0]->dtv_property_cache
.bandwidth_hz
/ 1000 >> 24) & 0xff);
1168 b
[8] = 0x80; /* do not wait for CELL ID when doing autosearch */
1169 if (state
->fe
[0]->dtv_property_cache
.delivery_system
== SYS_DVBT
)
1171 dib9000_risc_mem_write(state
, FE_MM_W_CHANNEL_HEAD
, b
);
1174 static int dib9000_fw_get_channel(struct dvb_frontend
*fe
)
1176 struct dib9000_state
*state
= fe
->demodulator_priv
;
1177 struct dibDVBTChannel
{
1178 s8 spectrum_inversion
;
1192 struct dibDVBTChannel
*ch
;
1195 if (DibAcquireLock(&state
->platform
.risc
.mem_mbx_lock
) < 0) {
1196 dprintk("could not get the lock");
1199 if (dib9000_fw_memmbx_sync(state
, FE_SYNC_CHANNEL
) < 0) {
1204 dib9000_risc_mem_read(state
, FE_MM_R_CHANNEL_UNION
,
1205 state
->i2c_read_buffer
, sizeof(struct dibDVBTChannel
));
1206 ch
= (struct dibDVBTChannel
*)state
->i2c_read_buffer
;
1209 switch (ch
->spectrum_inversion
& 0x7) {
1211 state
->fe
[0]->dtv_property_cache
.inversion
= INVERSION_ON
;
1214 state
->fe
[0]->dtv_property_cache
.inversion
= INVERSION_OFF
;
1218 state
->fe
[0]->dtv_property_cache
.inversion
= INVERSION_AUTO
;
1223 state
->fe
[0]->dtv_property_cache
.transmission_mode
= TRANSMISSION_MODE_2K
;
1226 state
->fe
[0]->dtv_property_cache
.transmission_mode
= TRANSMISSION_MODE_4K
;
1229 state
->fe
[0]->dtv_property_cache
.transmission_mode
= TRANSMISSION_MODE_8K
;
1233 state
->fe
[0]->dtv_property_cache
.transmission_mode
= TRANSMISSION_MODE_AUTO
;
1236 switch (ch
->guard
) {
1238 state
->fe
[0]->dtv_property_cache
.guard_interval
= GUARD_INTERVAL_1_32
;
1241 state
->fe
[0]->dtv_property_cache
.guard_interval
= GUARD_INTERVAL_1_16
;
1244 state
->fe
[0]->dtv_property_cache
.guard_interval
= GUARD_INTERVAL_1_8
;
1247 state
->fe
[0]->dtv_property_cache
.guard_interval
= GUARD_INTERVAL_1_4
;
1251 state
->fe
[0]->dtv_property_cache
.guard_interval
= GUARD_INTERVAL_AUTO
;
1254 switch (ch
->constellation
) {
1256 state
->fe
[0]->dtv_property_cache
.modulation
= QAM_64
;
1259 state
->fe
[0]->dtv_property_cache
.modulation
= QAM_16
;
1262 state
->fe
[0]->dtv_property_cache
.modulation
= QPSK
;
1266 state
->fe
[0]->dtv_property_cache
.modulation
= QAM_AUTO
;
1271 state
->fe
[0]->dtv_property_cache
.hierarchy
= HIERARCHY_NONE
;
1274 state
->fe
[0]->dtv_property_cache
.hierarchy
= HIERARCHY_1
;
1278 state
->fe
[0]->dtv_property_cache
.hierarchy
= HIERARCHY_AUTO
;
1281 switch (ch
->code_rate_hp
) {
1283 state
->fe
[0]->dtv_property_cache
.code_rate_HP
= FEC_1_2
;
1286 state
->fe
[0]->dtv_property_cache
.code_rate_HP
= FEC_2_3
;
1289 state
->fe
[0]->dtv_property_cache
.code_rate_HP
= FEC_3_4
;
1292 state
->fe
[0]->dtv_property_cache
.code_rate_HP
= FEC_5_6
;
1295 state
->fe
[0]->dtv_property_cache
.code_rate_HP
= FEC_7_8
;
1299 state
->fe
[0]->dtv_property_cache
.code_rate_HP
= FEC_AUTO
;
1302 switch (ch
->code_rate_lp
) {
1304 state
->fe
[0]->dtv_property_cache
.code_rate_LP
= FEC_1_2
;
1307 state
->fe
[0]->dtv_property_cache
.code_rate_LP
= FEC_2_3
;
1310 state
->fe
[0]->dtv_property_cache
.code_rate_LP
= FEC_3_4
;
1313 state
->fe
[0]->dtv_property_cache
.code_rate_LP
= FEC_5_6
;
1316 state
->fe
[0]->dtv_property_cache
.code_rate_LP
= FEC_7_8
;
1320 state
->fe
[0]->dtv_property_cache
.code_rate_LP
= FEC_AUTO
;
1325 DibReleaseLock(&state
->platform
.risc
.mem_mbx_lock
);
1329 static int dib9000_fw_set_channel_union(struct dvb_frontend
*fe
)
1331 struct dib9000_state
*state
= fe
->demodulator_priv
;
1332 struct dibDVBTChannel
{
1333 s8 spectrum_inversion
;
1347 struct dibDVBTChannel ch
;
1349 switch (state
->fe
[0]->dtv_property_cache
.inversion
) {
1351 ch
.spectrum_inversion
= 1;
1354 ch
.spectrum_inversion
= 0;
1357 case INVERSION_AUTO
:
1358 ch
.spectrum_inversion
= -1;
1361 switch (state
->fe
[0]->dtv_property_cache
.transmission_mode
) {
1362 case TRANSMISSION_MODE_2K
:
1365 case TRANSMISSION_MODE_4K
:
1368 case TRANSMISSION_MODE_8K
:
1372 case TRANSMISSION_MODE_AUTO
:
1376 switch (state
->fe
[0]->dtv_property_cache
.guard_interval
) {
1377 case GUARD_INTERVAL_1_32
:
1380 case GUARD_INTERVAL_1_16
:
1383 case GUARD_INTERVAL_1_8
:
1386 case GUARD_INTERVAL_1_4
:
1390 case GUARD_INTERVAL_AUTO
:
1394 switch (state
->fe
[0]->dtv_property_cache
.modulation
) {
1396 ch
.constellation
= 2;
1399 ch
.constellation
= 1;
1402 ch
.constellation
= 0;
1406 ch
.constellation
= -1;
1409 switch (state
->fe
[0]->dtv_property_cache
.hierarchy
) {
1410 case HIERARCHY_NONE
:
1419 case HIERARCHY_AUTO
:
1424 switch (state
->fe
[0]->dtv_property_cache
.code_rate_HP
) {
1426 ch
.code_rate_hp
= 1;
1429 ch
.code_rate_hp
= 2;
1432 ch
.code_rate_hp
= 3;
1435 ch
.code_rate_hp
= 5;
1438 ch
.code_rate_hp
= 7;
1442 ch
.code_rate_hp
= -1;
1445 switch (state
->fe
[0]->dtv_property_cache
.code_rate_LP
) {
1447 ch
.code_rate_lp
= 1;
1450 ch
.code_rate_lp
= 2;
1453 ch
.code_rate_lp
= 3;
1456 ch
.code_rate_lp
= 5;
1459 ch
.code_rate_lp
= 7;
1463 ch
.code_rate_lp
= -1;
1467 ch
.intlv_native
= 1;
1469 dib9000_risc_mem_write(state
, FE_MM_W_CHANNEL_UNION
, (u8
*) &ch
);
1474 static int dib9000_fw_tune(struct dvb_frontend
*fe
)
1476 struct dib9000_state
*state
= fe
->demodulator_priv
;
1477 int ret
= 10, search
= state
->channel_status
.status
== CHANNEL_STATUS_PARAMETERS_UNKNOWN
;
1480 switch (state
->tune_state
) {
1481 case CT_DEMOD_START
:
1482 dib9000_fw_set_channel_head(state
);
1484 /* write the channel context - a channel is initialized to 0, so it is OK */
1485 dib9000_risc_mem_write(state
, FE_MM_W_CHANNEL_CONTEXT
, (u8
*) fe_info
);
1486 dib9000_risc_mem_write(state
, FE_MM_W_FE_INFO
, (u8
*) fe_info
);
1489 dib9000_mbx_send(state
, OUT_MSG_FE_CHANNEL_SEARCH
, NULL
, 0);
1491 dib9000_fw_set_channel_union(fe
);
1492 dib9000_mbx_send(state
, OUT_MSG_FE_CHANNEL_TUNE
, NULL
, 0);
1494 state
->tune_state
= CT_DEMOD_STEP_1
;
1496 case CT_DEMOD_STEP_1
:
1498 dib9000_risc_mem_read(state
, FE_MM_R_CHANNEL_SEARCH_STATE
, state
->i2c_read_buffer
, 1);
1500 dib9000_risc_mem_read(state
, FE_MM_R_CHANNEL_TUNE_STATE
, state
->i2c_read_buffer
, 1);
1501 i
= (s8
)state
->i2c_read_buffer
[0];
1502 switch (i
) { /* something happened */
1505 case -2: /* tps locks are "slower" than MPEG locks -> even in autosearch data is OK here */
1507 state
->status
= FE_STATUS_DEMOD_SUCCESS
;
1509 state
->tune_state
= CT_DEMOD_STOP
;
1510 state
->status
= FE_STATUS_LOCKED
;
1514 state
->status
= FE_STATUS_TUNE_FAILED
;
1515 state
->tune_state
= CT_DEMOD_STOP
;
1520 ret
= FE_CALLBACK_TIME_NEVER
;
1527 static int dib9000_fw_set_diversity_in(struct dvb_frontend
*fe
, int onoff
)
1529 struct dib9000_state
*state
= fe
->demodulator_priv
;
1530 u16 mode
= (u16
) onoff
;
1531 return dib9000_mbx_send(state
, OUT_MSG_ENABLE_DIVERSITY
, &mode
, 1);
1534 static int dib9000_fw_set_output_mode(struct dvb_frontend
*fe
, int mode
)
1536 struct dib9000_state
*state
= fe
->demodulator_priv
;
1537 u16 outreg
, smo_mode
;
1539 dprintk("setting output mode for demod %p to %d", fe
, mode
);
1542 case OUTMODE_MPEG2_PAR_GATED_CLK
:
1543 outreg
= (1 << 10); /* 0x0400 */
1545 case OUTMODE_MPEG2_PAR_CONT_CLK
:
1546 outreg
= (1 << 10) | (1 << 6); /* 0x0440 */
1548 case OUTMODE_MPEG2_SERIAL
:
1549 outreg
= (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
1551 case OUTMODE_DIVERSITY
:
1552 outreg
= (1 << 10) | (4 << 6); /* 0x0500 */
1554 case OUTMODE_MPEG2_FIFO
:
1555 outreg
= (1 << 10) | (5 << 6);
1557 case OUTMODE_HIGH_Z
:
1561 dprintk("Unhandled output_mode passed to be set for demod %p", &state
->fe
[0]);
1565 dib9000_write_word(state
, 1795, outreg
);
1568 case OUTMODE_MPEG2_PAR_GATED_CLK
:
1569 case OUTMODE_MPEG2_PAR_CONT_CLK
:
1570 case OUTMODE_MPEG2_SERIAL
:
1571 case OUTMODE_MPEG2_FIFO
:
1572 smo_mode
= (dib9000_read_word(state
, 295) & 0x0010) | (1 << 1);
1573 if (state
->chip
.d9
.cfg
.output_mpeg2_in_188_bytes
)
1574 smo_mode
|= (1 << 5);
1575 dib9000_write_word(state
, 295, smo_mode
);
1579 outreg
= to_fw_output_mode(mode
);
1580 return dib9000_mbx_send(state
, OUT_MSG_SET_OUTPUT_MODE
, &outreg
, 1);
1583 static int dib9000_tuner_xfer(struct i2c_adapter
*i2c_adap
, struct i2c_msg msg
[], int num
)
1585 struct dib9000_state
*state
= i2c_get_adapdata(i2c_adap
);
1586 u16 i
, len
, t
, index_msg
;
1588 for (index_msg
= 0; index_msg
< num
; index_msg
++) {
1589 if (msg
[index_msg
].flags
& I2C_M_RD
) { /* read */
1590 len
= msg
[index_msg
].len
;
1594 if (dib9000_read_word(state
, 790) != 0)
1595 dprintk("TunerITF: read busy");
1597 dib9000_write_word(state
, 784, (u16
) (msg
[index_msg
].addr
));
1598 dib9000_write_word(state
, 787, (len
/ 2) - 1);
1599 dib9000_write_word(state
, 786, 1); /* start read */
1602 while (dib9000_read_word(state
, 790) != (len
/ 2) && i
)
1606 dprintk("TunerITF: read failed");
1608 for (i
= 0; i
< len
; i
+= 2) {
1609 t
= dib9000_read_word(state
, 785);
1610 msg
[index_msg
].buf
[i
] = (t
>> 8) & 0xff;
1611 msg
[index_msg
].buf
[i
+ 1] = (t
) & 0xff;
1613 if (dib9000_read_word(state
, 790) != 0)
1614 dprintk("TunerITF: read more data than expected");
1617 while (dib9000_read_word(state
, 789) && i
)
1620 dprintk("TunerITF: write busy");
1622 len
= msg
[index_msg
].len
;
1626 for (i
= 0; i
< len
; i
+= 2)
1627 dib9000_write_word(state
, 785, (msg
[index_msg
].buf
[i
] << 8) | msg
[index_msg
].buf
[i
+ 1]);
1628 dib9000_write_word(state
, 784, (u16
) msg
[index_msg
].addr
);
1629 dib9000_write_word(state
, 787, (len
/ 2) - 1);
1630 dib9000_write_word(state
, 786, 0); /* start write */
1633 while (dib9000_read_word(state
, 791) > 0 && i
)
1636 dprintk("TunerITF: write failed");
1642 int dib9000_fw_set_component_bus_speed(struct dvb_frontend
*fe
, u16 speed
)
1644 struct dib9000_state
*state
= fe
->demodulator_priv
;
1646 state
->component_bus_speed
= speed
;
1649 EXPORT_SYMBOL(dib9000_fw_set_component_bus_speed
);
1651 static int dib9000_fw_component_bus_xfer(struct i2c_adapter
*i2c_adap
, struct i2c_msg msg
[], int num
)
1653 struct dib9000_state
*state
= i2c_get_adapdata(i2c_adap
);
1654 u8 type
= 0; /* I2C */
1655 u8 port
= DIBX000_I2C_INTERFACE_GPIO_3_4
;
1656 u16 scl
= state
->component_bus_speed
; /* SCL frequency */
1657 struct dib9000_fe_memory_map
*m
= &state
->platform
.risc
.fe_mm
[FE_MM_RW_COMPONENT_ACCESS_BUFFER
];
1662 p
[2] = msg
[0].addr
<< 1;
1664 p
[3] = (u8
) scl
& 0xff; /* scl */
1665 p
[4] = (u8
) (scl
>> 8);
1670 p
[9] = (u8
) (msg
[0].len
);
1671 p
[10] = (u8
) (msg
[0].len
>> 8);
1672 if ((num
> 1) && (msg
[1].flags
& I2C_M_RD
)) {
1673 p
[11] = (u8
) (msg
[1].len
);
1674 p
[12] = (u8
) (msg
[1].len
>> 8);
1680 if (DibAcquireLock(&state
->platform
.risc
.mem_mbx_lock
) < 0) {
1681 dprintk("could not get the lock");
1685 dib9000_risc_mem_write(state
, FE_MM_W_COMPONENT_ACCESS
, p
);
1688 dib9000_risc_mem_setup_cmd(state
, m
->addr
, msg
[0].len
, 0);
1689 dib9000_risc_mem_write_chunks(state
, msg
[0].buf
, msg
[0].len
);
1692 /* do the transaction */
1693 if (dib9000_fw_memmbx_sync(state
, FE_SYNC_COMPONENT_ACCESS
) < 0) {
1694 DibReleaseLock(&state
->platform
.risc
.mem_mbx_lock
);
1698 /* read back any possible result */
1699 if ((num
> 1) && (msg
[1].flags
& I2C_M_RD
))
1700 dib9000_risc_mem_read(state
, FE_MM_RW_COMPONENT_ACCESS_BUFFER
, msg
[1].buf
, msg
[1].len
);
1702 DibReleaseLock(&state
->platform
.risc
.mem_mbx_lock
);
1707 static u32
dib9000_i2c_func(struct i2c_adapter
*adapter
)
1709 return I2C_FUNC_I2C
;
1712 static struct i2c_algorithm dib9000_tuner_algo
= {
1713 .master_xfer
= dib9000_tuner_xfer
,
1714 .functionality
= dib9000_i2c_func
,
1717 static struct i2c_algorithm dib9000_component_bus_algo
= {
1718 .master_xfer
= dib9000_fw_component_bus_xfer
,
1719 .functionality
= dib9000_i2c_func
,
1722 struct i2c_adapter
*dib9000_get_tuner_interface(struct dvb_frontend
*fe
)
1724 struct dib9000_state
*st
= fe
->demodulator_priv
;
1725 return &st
->tuner_adap
;
1727 EXPORT_SYMBOL(dib9000_get_tuner_interface
);
1729 struct i2c_adapter
*dib9000_get_component_bus_interface(struct dvb_frontend
*fe
)
1731 struct dib9000_state
*st
= fe
->demodulator_priv
;
1732 return &st
->component_bus
;
1734 EXPORT_SYMBOL(dib9000_get_component_bus_interface
);
1736 struct i2c_adapter
*dib9000_get_i2c_master(struct dvb_frontend
*fe
, enum dibx000_i2c_interface intf
, int gating
)
1738 struct dib9000_state
*st
= fe
->demodulator_priv
;
1739 return dibx000_get_i2c_adapter(&st
->i2c_master
, intf
, gating
);
1741 EXPORT_SYMBOL(dib9000_get_i2c_master
);
1743 int dib9000_set_i2c_adapter(struct dvb_frontend
*fe
, struct i2c_adapter
*i2c
)
1745 struct dib9000_state
*st
= fe
->demodulator_priv
;
1747 st
->i2c
.i2c_adap
= i2c
;
1750 EXPORT_SYMBOL(dib9000_set_i2c_adapter
);
1752 static int dib9000_cfg_gpio(struct dib9000_state
*st
, u8 num
, u8 dir
, u8 val
)
1754 st
->gpio_dir
= dib9000_read_word(st
, 773);
1755 st
->gpio_dir
&= ~(1 << num
); /* reset the direction bit */
1756 st
->gpio_dir
|= (dir
& 0x1) << num
; /* set the new direction */
1757 dib9000_write_word(st
, 773, st
->gpio_dir
);
1759 st
->gpio_val
= dib9000_read_word(st
, 774);
1760 st
->gpio_val
&= ~(1 << num
); /* reset the direction bit */
1761 st
->gpio_val
|= (val
& 0x01) << num
; /* set the new value */
1762 dib9000_write_word(st
, 774, st
->gpio_val
);
1764 dprintk("gpio dir: %04x: gpio val: %04x", st
->gpio_dir
, st
->gpio_val
);
1769 int dib9000_set_gpio(struct dvb_frontend
*fe
, u8 num
, u8 dir
, u8 val
)
1771 struct dib9000_state
*state
= fe
->demodulator_priv
;
1772 return dib9000_cfg_gpio(state
, num
, dir
, val
);
1774 EXPORT_SYMBOL(dib9000_set_gpio
);
1776 int dib9000_fw_pid_filter_ctrl(struct dvb_frontend
*fe
, u8 onoff
)
1778 struct dib9000_state
*state
= fe
->demodulator_priv
;
1782 if ((state
->pid_ctrl_index
!= -2) && (state
->pid_ctrl_index
< 9)) {
1783 /* postpone the pid filtering cmd */
1784 dprintk("pid filter cmd postpone");
1785 state
->pid_ctrl_index
++;
1786 state
->pid_ctrl
[state
->pid_ctrl_index
].cmd
= DIB9000_PID_FILTER_CTRL
;
1787 state
->pid_ctrl
[state
->pid_ctrl_index
].onoff
= onoff
;
1791 if (DibAcquireLock(&state
->demod_lock
) < 0) {
1792 dprintk("could not get the lock");
1796 val
= dib9000_read_word(state
, 294 + 1) & 0xffef;
1797 val
|= (onoff
& 0x1) << 4;
1799 dprintk("PID filter enabled %d", onoff
);
1800 ret
= dib9000_write_word(state
, 294 + 1, val
);
1801 DibReleaseLock(&state
->demod_lock
);
1805 EXPORT_SYMBOL(dib9000_fw_pid_filter_ctrl
);
1807 int dib9000_fw_pid_filter(struct dvb_frontend
*fe
, u8 id
, u16 pid
, u8 onoff
)
1809 struct dib9000_state
*state
= fe
->demodulator_priv
;
1812 if (state
->pid_ctrl_index
!= -2) {
1813 /* postpone the pid filtering cmd */
1814 dprintk("pid filter postpone");
1815 if (state
->pid_ctrl_index
< 9) {
1816 state
->pid_ctrl_index
++;
1817 state
->pid_ctrl
[state
->pid_ctrl_index
].cmd
= DIB9000_PID_FILTER
;
1818 state
->pid_ctrl
[state
->pid_ctrl_index
].id
= id
;
1819 state
->pid_ctrl
[state
->pid_ctrl_index
].pid
= pid
;
1820 state
->pid_ctrl
[state
->pid_ctrl_index
].onoff
= onoff
;
1822 dprintk("can not add any more pid ctrl cmd");
1826 if (DibAcquireLock(&state
->demod_lock
) < 0) {
1827 dprintk("could not get the lock");
1830 dprintk("Index %x, PID %d, OnOff %d", id
, pid
, onoff
);
1831 ret
= dib9000_write_word(state
, 300 + 1 + id
,
1832 onoff
? (1 << 13) | pid
: 0);
1833 DibReleaseLock(&state
->demod_lock
);
1836 EXPORT_SYMBOL(dib9000_fw_pid_filter
);
1838 int dib9000_firmware_post_pll_init(struct dvb_frontend
*fe
)
1840 struct dib9000_state
*state
= fe
->demodulator_priv
;
1841 return dib9000_fw_init(state
);
1843 EXPORT_SYMBOL(dib9000_firmware_post_pll_init
);
1845 static void dib9000_release(struct dvb_frontend
*demod
)
1847 struct dib9000_state
*st
= demod
->demodulator_priv
;
1850 for (index_frontend
= 1; (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (st
->fe
[index_frontend
] != NULL
); index_frontend
++)
1851 dvb_frontend_detach(st
->fe
[index_frontend
]);
1853 DibFreeLock(&state
->platform
.risc
.mbx_if_lock
);
1854 DibFreeLock(&state
->platform
.risc
.mbx_lock
);
1855 DibFreeLock(&state
->platform
.risc
.mem_lock
);
1856 DibFreeLock(&state
->platform
.risc
.mem_mbx_lock
);
1857 DibFreeLock(&state
->demod_lock
);
1858 dibx000_exit_i2c_master(&st
->i2c_master
);
1860 i2c_del_adapter(&st
->tuner_adap
);
1861 i2c_del_adapter(&st
->component_bus
);
1866 static int dib9000_wakeup(struct dvb_frontend
*fe
)
1871 static int dib9000_sleep(struct dvb_frontend
*fe
)
1873 struct dib9000_state
*state
= fe
->demodulator_priv
;
1877 if (DibAcquireLock(&state
->demod_lock
) < 0) {
1878 dprintk("could not get the lock");
1881 for (index_frontend
= 1; (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
); index_frontend
++) {
1882 ret
= state
->fe
[index_frontend
]->ops
.sleep(state
->fe
[index_frontend
]);
1886 ret
= dib9000_mbx_send(state
, OUT_MSG_FE_SLEEP
, NULL
, 0);
1889 DibReleaseLock(&state
->demod_lock
);
1893 static int dib9000_fe_get_tune_settings(struct dvb_frontend
*fe
, struct dvb_frontend_tune_settings
*tune
)
1895 tune
->min_delay_ms
= 1000;
1899 static int dib9000_get_frontend(struct dvb_frontend
*fe
)
1901 struct dib9000_state
*state
= fe
->demodulator_priv
;
1902 u8 index_frontend
, sub_index_frontend
;
1906 if (state
->get_frontend_internal
== 0) {
1907 if (DibAcquireLock(&state
->demod_lock
) < 0) {
1908 dprintk("could not get the lock");
1913 for (index_frontend
= 1; (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
); index_frontend
++) {
1914 state
->fe
[index_frontend
]->ops
.read_status(state
->fe
[index_frontend
], &stat
);
1915 if (stat
& FE_HAS_SYNC
) {
1916 dprintk("TPS lock on the slave%i", index_frontend
);
1918 /* synchronize the cache with the other frontends */
1919 state
->fe
[index_frontend
]->ops
.get_frontend(state
->fe
[index_frontend
]);
1920 for (sub_index_frontend
= 0; (sub_index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[sub_index_frontend
] != NULL
);
1921 sub_index_frontend
++) {
1922 if (sub_index_frontend
!= index_frontend
) {
1923 state
->fe
[sub_index_frontend
]->dtv_property_cache
.modulation
=
1924 state
->fe
[index_frontend
]->dtv_property_cache
.modulation
;
1925 state
->fe
[sub_index_frontend
]->dtv_property_cache
.inversion
=
1926 state
->fe
[index_frontend
]->dtv_property_cache
.inversion
;
1927 state
->fe
[sub_index_frontend
]->dtv_property_cache
.transmission_mode
=
1928 state
->fe
[index_frontend
]->dtv_property_cache
.transmission_mode
;
1929 state
->fe
[sub_index_frontend
]->dtv_property_cache
.guard_interval
=
1930 state
->fe
[index_frontend
]->dtv_property_cache
.guard_interval
;
1931 state
->fe
[sub_index_frontend
]->dtv_property_cache
.hierarchy
=
1932 state
->fe
[index_frontend
]->dtv_property_cache
.hierarchy
;
1933 state
->fe
[sub_index_frontend
]->dtv_property_cache
.code_rate_HP
=
1934 state
->fe
[index_frontend
]->dtv_property_cache
.code_rate_HP
;
1935 state
->fe
[sub_index_frontend
]->dtv_property_cache
.code_rate_LP
=
1936 state
->fe
[index_frontend
]->dtv_property_cache
.code_rate_LP
;
1937 state
->fe
[sub_index_frontend
]->dtv_property_cache
.rolloff
=
1938 state
->fe
[index_frontend
]->dtv_property_cache
.rolloff
;
1946 /* get the channel from master chip */
1947 ret
= dib9000_fw_get_channel(fe
);
1951 /* synchronize the cache with the other frontends */
1952 for (index_frontend
= 1; (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
); index_frontend
++) {
1953 state
->fe
[index_frontend
]->dtv_property_cache
.inversion
= fe
->dtv_property_cache
.inversion
;
1954 state
->fe
[index_frontend
]->dtv_property_cache
.transmission_mode
= fe
->dtv_property_cache
.transmission_mode
;
1955 state
->fe
[index_frontend
]->dtv_property_cache
.guard_interval
= fe
->dtv_property_cache
.guard_interval
;
1956 state
->fe
[index_frontend
]->dtv_property_cache
.modulation
= fe
->dtv_property_cache
.modulation
;
1957 state
->fe
[index_frontend
]->dtv_property_cache
.hierarchy
= fe
->dtv_property_cache
.hierarchy
;
1958 state
->fe
[index_frontend
]->dtv_property_cache
.code_rate_HP
= fe
->dtv_property_cache
.code_rate_HP
;
1959 state
->fe
[index_frontend
]->dtv_property_cache
.code_rate_LP
= fe
->dtv_property_cache
.code_rate_LP
;
1960 state
->fe
[index_frontend
]->dtv_property_cache
.rolloff
= fe
->dtv_property_cache
.rolloff
;
1965 if (state
->get_frontend_internal
== 0)
1966 DibReleaseLock(&state
->demod_lock
);
1970 static int dib9000_set_tune_state(struct dvb_frontend
*fe
, enum frontend_tune_state tune_state
)
1972 struct dib9000_state
*state
= fe
->demodulator_priv
;
1973 state
->tune_state
= tune_state
;
1974 if (tune_state
== CT_DEMOD_START
)
1975 state
->status
= FE_STATUS_TUNE_PENDING
;
1980 static u32
dib9000_get_status(struct dvb_frontend
*fe
)
1982 struct dib9000_state
*state
= fe
->demodulator_priv
;
1983 return state
->status
;
1986 static int dib9000_set_channel_status(struct dvb_frontend
*fe
, struct dvb_frontend_parametersContext
*channel_status
)
1988 struct dib9000_state
*state
= fe
->demodulator_priv
;
1990 memcpy(&state
->channel_status
, channel_status
, sizeof(struct dvb_frontend_parametersContext
));
1994 static int dib9000_set_frontend(struct dvb_frontend
*fe
)
1996 struct dib9000_state
*state
= fe
->demodulator_priv
;
1997 int sleep_time
, sleep_time_slave
;
1998 u32 frontend_status
;
1999 u8 nbr_pending
, exit_condition
, index_frontend
, index_frontend_success
;
2000 struct dvb_frontend_parametersContext channel_status
;
2002 /* check that the correct parameters are set */
2003 if (state
->fe
[0]->dtv_property_cache
.frequency
== 0) {
2004 dprintk("dib9000: must specify frequency ");
2008 if (state
->fe
[0]->dtv_property_cache
.bandwidth_hz
== 0) {
2009 dprintk("dib9000: must specify bandwidth ");
2013 state
->pid_ctrl_index
= -1; /* postpone the pid filtering cmd */
2014 if (DibAcquireLock(&state
->demod_lock
) < 0) {
2015 dprintk("could not get the lock");
2019 fe
->dtv_property_cache
.delivery_system
= SYS_DVBT
;
2021 /* set the master status */
2022 if (state
->fe
[0]->dtv_property_cache
.transmission_mode
== TRANSMISSION_MODE_AUTO
||
2023 state
->fe
[0]->dtv_property_cache
.guard_interval
== GUARD_INTERVAL_AUTO
||
2024 state
->fe
[0]->dtv_property_cache
.modulation
== QAM_AUTO
||
2025 state
->fe
[0]->dtv_property_cache
.code_rate_HP
== FEC_AUTO
) {
2026 /* no channel specified, autosearch the channel */
2027 state
->channel_status
.status
= CHANNEL_STATUS_PARAMETERS_UNKNOWN
;
2029 state
->channel_status
.status
= CHANNEL_STATUS_PARAMETERS_SET
;
2031 /* set mode and status for the different frontends */
2032 for (index_frontend
= 0; (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
); index_frontend
++) {
2033 dib9000_fw_set_diversity_in(state
->fe
[index_frontend
], 1);
2035 /* synchronization of the cache */
2036 memcpy(&state
->fe
[index_frontend
]->dtv_property_cache
, &fe
->dtv_property_cache
, sizeof(struct dtv_frontend_properties
));
2038 state
->fe
[index_frontend
]->dtv_property_cache
.delivery_system
= SYS_DVBT
;
2039 dib9000_fw_set_output_mode(state
->fe
[index_frontend
], OUTMODE_HIGH_Z
);
2041 dib9000_set_channel_status(state
->fe
[index_frontend
], &state
->channel_status
);
2042 dib9000_set_tune_state(state
->fe
[index_frontend
], CT_DEMOD_START
);
2046 exit_condition
= 0; /* 0: tune pending; 1: tune failed; 2:tune success */
2047 index_frontend_success
= 0;
2049 sleep_time
= dib9000_fw_tune(state
->fe
[0]);
2050 for (index_frontend
= 1; (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
); index_frontend
++) {
2051 sleep_time_slave
= dib9000_fw_tune(state
->fe
[index_frontend
]);
2052 if (sleep_time
== FE_CALLBACK_TIME_NEVER
)
2053 sleep_time
= sleep_time_slave
;
2054 else if ((sleep_time_slave
!= FE_CALLBACK_TIME_NEVER
) && (sleep_time_slave
> sleep_time
))
2055 sleep_time
= sleep_time_slave
;
2057 if (sleep_time
!= FE_CALLBACK_TIME_NEVER
)
2058 msleep(sleep_time
/ 10);
2064 index_frontend_success
= 0;
2065 for (index_frontend
= 0; (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
); index_frontend
++) {
2066 frontend_status
= -dib9000_get_status(state
->fe
[index_frontend
]);
2067 if (frontend_status
> -FE_STATUS_TUNE_PENDING
) {
2068 exit_condition
= 2; /* tune success */
2069 index_frontend_success
= index_frontend
;
2072 if (frontend_status
== -FE_STATUS_TUNE_PENDING
)
2073 nbr_pending
++; /* some frontends are still tuning */
2075 if ((exit_condition
!= 2) && (nbr_pending
== 0))
2076 exit_condition
= 1; /* if all tune are done and no success, exit: tune failed */
2078 } while (exit_condition
== 0);
2080 /* check the tune result */
2081 if (exit_condition
== 1) { /* tune failed */
2082 dprintk("tune failed");
2083 DibReleaseLock(&state
->demod_lock
);
2084 /* tune failed; put all the pid filtering cmd to junk */
2085 state
->pid_ctrl_index
= -1;
2089 dprintk("tune success on frontend%i", index_frontend_success
);
2091 /* synchronize all the channel cache */
2092 state
->get_frontend_internal
= 1;
2093 dib9000_get_frontend(state
->fe
[0]);
2094 state
->get_frontend_internal
= 0;
2096 /* retune the other frontends with the found channel */
2097 channel_status
.status
= CHANNEL_STATUS_PARAMETERS_SET
;
2098 for (index_frontend
= 0; (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
); index_frontend
++) {
2099 /* only retune the frontends which was not tuned success */
2100 if (index_frontend
!= index_frontend_success
) {
2101 dib9000_set_channel_status(state
->fe
[index_frontend
], &channel_status
);
2102 dib9000_set_tune_state(state
->fe
[index_frontend
], CT_DEMOD_START
);
2106 sleep_time
= FE_CALLBACK_TIME_NEVER
;
2107 for (index_frontend
= 0; (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
); index_frontend
++) {
2108 if (index_frontend
!= index_frontend_success
) {
2109 sleep_time_slave
= dib9000_fw_tune(state
->fe
[index_frontend
]);
2110 if (sleep_time
== FE_CALLBACK_TIME_NEVER
)
2111 sleep_time
= sleep_time_slave
;
2112 else if ((sleep_time_slave
!= FE_CALLBACK_TIME_NEVER
) && (sleep_time_slave
> sleep_time
))
2113 sleep_time
= sleep_time_slave
;
2116 if (sleep_time
!= FE_CALLBACK_TIME_NEVER
)
2117 msleep(sleep_time
/ 10);
2122 for (index_frontend
= 0; (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
); index_frontend
++) {
2123 if (index_frontend
!= index_frontend_success
) {
2124 frontend_status
= -dib9000_get_status(state
->fe
[index_frontend
]);
2125 if ((index_frontend
!= index_frontend_success
) && (frontend_status
== -FE_STATUS_TUNE_PENDING
))
2126 nbr_pending
++; /* some frontends are still tuning */
2129 } while (nbr_pending
!= 0);
2131 /* set the output mode */
2132 dib9000_fw_set_output_mode(state
->fe
[0], state
->chip
.d9
.cfg
.output_mode
);
2133 for (index_frontend
= 1; (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
); index_frontend
++)
2134 dib9000_fw_set_output_mode(state
->fe
[index_frontend
], OUTMODE_DIVERSITY
);
2136 /* turn off the diversity for the last frontend */
2137 dib9000_fw_set_diversity_in(state
->fe
[index_frontend
- 1], 0);
2139 DibReleaseLock(&state
->demod_lock
);
2140 if (state
->pid_ctrl_index
>= 0) {
2141 u8 index_pid_filter_cmd
;
2142 u8 pid_ctrl_index
= state
->pid_ctrl_index
;
2144 state
->pid_ctrl_index
= -2;
2145 for (index_pid_filter_cmd
= 0;
2146 index_pid_filter_cmd
<= pid_ctrl_index
;
2147 index_pid_filter_cmd
++) {
2148 if (state
->pid_ctrl
[index_pid_filter_cmd
].cmd
== DIB9000_PID_FILTER_CTRL
)
2149 dib9000_fw_pid_filter_ctrl(state
->fe
[0],
2150 state
->pid_ctrl
[index_pid_filter_cmd
].onoff
);
2151 else if (state
->pid_ctrl
[index_pid_filter_cmd
].cmd
== DIB9000_PID_FILTER
)
2152 dib9000_fw_pid_filter(state
->fe
[0],
2153 state
->pid_ctrl
[index_pid_filter_cmd
].id
,
2154 state
->pid_ctrl
[index_pid_filter_cmd
].pid
,
2155 state
->pid_ctrl
[index_pid_filter_cmd
].onoff
);
2158 /* do not postpone any more the pid filtering */
2159 state
->pid_ctrl_index
= -2;
2164 static u16
dib9000_read_lock(struct dvb_frontend
*fe
)
2166 struct dib9000_state
*state
= fe
->demodulator_priv
;
2168 return dib9000_read_word(state
, 535);
2171 static int dib9000_read_status(struct dvb_frontend
*fe
, fe_status_t
* stat
)
2173 struct dib9000_state
*state
= fe
->demodulator_priv
;
2175 u16 lock
= 0, lock_slave
= 0;
2177 if (DibAcquireLock(&state
->demod_lock
) < 0) {
2178 dprintk("could not get the lock");
2181 for (index_frontend
= 1; (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
); index_frontend
++)
2182 lock_slave
|= dib9000_read_lock(state
->fe
[index_frontend
]);
2184 lock
= dib9000_read_word(state
, 535);
2188 if ((lock
& 0x8000) || (lock_slave
& 0x8000))
2189 *stat
|= FE_HAS_SIGNAL
;
2190 if ((lock
& 0x3000) || (lock_slave
& 0x3000))
2191 *stat
|= FE_HAS_CARRIER
;
2192 if ((lock
& 0x0100) || (lock_slave
& 0x0100))
2193 *stat
|= FE_HAS_VITERBI
;
2194 if (((lock
& 0x0038) == 0x38) || ((lock_slave
& 0x0038) == 0x38))
2195 *stat
|= FE_HAS_SYNC
;
2196 if ((lock
& 0x0008) || (lock_slave
& 0x0008))
2197 *stat
|= FE_HAS_LOCK
;
2199 DibReleaseLock(&state
->demod_lock
);
2204 static int dib9000_read_ber(struct dvb_frontend
*fe
, u32
* ber
)
2206 struct dib9000_state
*state
= fe
->demodulator_priv
;
2210 if (DibAcquireLock(&state
->demod_lock
) < 0) {
2211 dprintk("could not get the lock");
2214 if (DibAcquireLock(&state
->platform
.risc
.mem_mbx_lock
) < 0) {
2215 dprintk("could not get the lock");
2219 if (dib9000_fw_memmbx_sync(state
, FE_SYNC_CHANNEL
) < 0) {
2220 DibReleaseLock(&state
->platform
.risc
.mem_mbx_lock
);
2224 dib9000_risc_mem_read(state
, FE_MM_R_FE_MONITOR
,
2225 state
->i2c_read_buffer
, 16 * 2);
2226 DibReleaseLock(&state
->platform
.risc
.mem_mbx_lock
);
2228 c
= (u16
*)state
->i2c_read_buffer
;
2230 *ber
= c
[10] << 16 | c
[11];
2233 DibReleaseLock(&state
->demod_lock
);
2237 static int dib9000_read_signal_strength(struct dvb_frontend
*fe
, u16
* strength
)
2239 struct dib9000_state
*state
= fe
->demodulator_priv
;
2241 u16
*c
= (u16
*)state
->i2c_read_buffer
;
2245 if (DibAcquireLock(&state
->demod_lock
) < 0) {
2246 dprintk("could not get the lock");
2250 for (index_frontend
= 1; (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
); index_frontend
++) {
2251 state
->fe
[index_frontend
]->ops
.read_signal_strength(state
->fe
[index_frontend
], &val
);
2252 if (val
> 65535 - *strength
)
2258 if (DibAcquireLock(&state
->platform
.risc
.mem_mbx_lock
) < 0) {
2259 dprintk("could not get the lock");
2263 if (dib9000_fw_memmbx_sync(state
, FE_SYNC_CHANNEL
) < 0) {
2264 DibReleaseLock(&state
->platform
.risc
.mem_mbx_lock
);
2268 dib9000_risc_mem_read(state
, FE_MM_R_FE_MONITOR
, (u8
*) c
, 16 * 2);
2269 DibReleaseLock(&state
->platform
.risc
.mem_mbx_lock
);
2272 if (val
> 65535 - *strength
)
2278 DibReleaseLock(&state
->demod_lock
);
2282 static u32
dib9000_get_snr(struct dvb_frontend
*fe
)
2284 struct dib9000_state
*state
= fe
->demodulator_priv
;
2285 u16
*c
= (u16
*)state
->i2c_read_buffer
;
2289 if (DibAcquireLock(&state
->platform
.risc
.mem_mbx_lock
) < 0) {
2290 dprintk("could not get the lock");
2293 if (dib9000_fw_memmbx_sync(state
, FE_SYNC_CHANNEL
) < 0) {
2294 DibReleaseLock(&state
->platform
.risc
.mem_mbx_lock
);
2297 dib9000_risc_mem_read(state
, FE_MM_R_FE_MONITOR
, (u8
*) c
, 16 * 2);
2298 DibReleaseLock(&state
->platform
.risc
.mem_mbx_lock
);
2301 n
= (val
>> 4) & 0xff;
2302 exp
= ((val
& 0xf) << 2);
2304 exp
+= ((val
>> 14) & 0x3);
2305 if ((exp
& 0x20) != 0)
2309 s
= (val
>> 6) & 0xFF;
2311 if ((exp
& 0x20) != 0)
2316 u32 t
= (s
/ n
) << 16;
2317 return t
+ ((s
<< 16) - n
* t
) / n
;
2322 static int dib9000_read_snr(struct dvb_frontend
*fe
, u16
* snr
)
2324 struct dib9000_state
*state
= fe
->demodulator_priv
;
2328 if (DibAcquireLock(&state
->demod_lock
) < 0) {
2329 dprintk("could not get the lock");
2332 snr_master
= dib9000_get_snr(fe
);
2333 for (index_frontend
= 1; (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
); index_frontend
++)
2334 snr_master
+= dib9000_get_snr(state
->fe
[index_frontend
]);
2336 if ((snr_master
>> 16) != 0) {
2337 snr_master
= 10 * intlog10(snr_master
>> 16);
2338 *snr
= snr_master
/ ((1 << 24) / 10);
2342 DibReleaseLock(&state
->demod_lock
);
2347 static int dib9000_read_unc_blocks(struct dvb_frontend
*fe
, u32
* unc
)
2349 struct dib9000_state
*state
= fe
->demodulator_priv
;
2350 u16
*c
= (u16
*)state
->i2c_read_buffer
;
2353 if (DibAcquireLock(&state
->demod_lock
) < 0) {
2354 dprintk("could not get the lock");
2357 if (DibAcquireLock(&state
->platform
.risc
.mem_mbx_lock
) < 0) {
2358 dprintk("could not get the lock");
2362 if (dib9000_fw_memmbx_sync(state
, FE_SYNC_CHANNEL
) < 0) {
2363 DibReleaseLock(&state
->platform
.risc
.mem_mbx_lock
);
2367 dib9000_risc_mem_read(state
, FE_MM_R_FE_MONITOR
, (u8
*) c
, 16 * 2);
2368 DibReleaseLock(&state
->platform
.risc
.mem_mbx_lock
);
2373 DibReleaseLock(&state
->demod_lock
);
2377 int dib9000_i2c_enumeration(struct i2c_adapter
*i2c
, int no_of_demods
, u8 default_addr
, u8 first_addr
)
2381 struct i2c_device client
= {.i2c_adap
= i2c
};
2383 client
.i2c_write_buffer
= kzalloc(4 * sizeof(u8
), GFP_KERNEL
);
2384 if (!client
.i2c_write_buffer
) {
2385 dprintk("%s: not enough memory", __func__
);
2388 client
.i2c_read_buffer
= kzalloc(4 * sizeof(u8
), GFP_KERNEL
);
2389 if (!client
.i2c_read_buffer
) {
2390 dprintk("%s: not enough memory", __func__
);
2395 client
.i2c_addr
= default_addr
+ 16;
2396 dib9000_i2c_write16(&client
, 1796, 0x0);
2398 for (k
= no_of_demods
- 1; k
>= 0; k
--) {
2399 /* designated i2c address */
2400 new_addr
= first_addr
+ (k
<< 1);
2401 client
.i2c_addr
= default_addr
;
2403 dib9000_i2c_write16(&client
, 1817, 3);
2404 dib9000_i2c_write16(&client
, 1796, 0);
2405 dib9000_i2c_write16(&client
, 1227, 1);
2406 dib9000_i2c_write16(&client
, 1227, 0);
2408 client
.i2c_addr
= new_addr
;
2409 dib9000_i2c_write16(&client
, 1817, 3);
2410 dib9000_i2c_write16(&client
, 1796, 0);
2411 dib9000_i2c_write16(&client
, 1227, 1);
2412 dib9000_i2c_write16(&client
, 1227, 0);
2414 if (dib9000_identify(&client
) == 0) {
2415 client
.i2c_addr
= default_addr
;
2416 if (dib9000_identify(&client
) == 0) {
2417 dprintk("DiB9000 #%d: not identified", k
);
2423 dib9000_i2c_write16(&client
, 1795, (1 << 10) | (4 << 6));
2424 dib9000_i2c_write16(&client
, 1794, (new_addr
<< 2) | 2);
2426 dprintk("IC %d initialized (to i2c_address 0x%x)", k
, new_addr
);
2429 for (k
= 0; k
< no_of_demods
; k
++) {
2430 new_addr
= first_addr
| (k
<< 1);
2431 client
.i2c_addr
= new_addr
;
2433 dib9000_i2c_write16(&client
, 1794, (new_addr
<< 2));
2434 dib9000_i2c_write16(&client
, 1795, 0);
2438 kfree(client
.i2c_read_buffer
);
2440 kfree(client
.i2c_write_buffer
);
2444 EXPORT_SYMBOL(dib9000_i2c_enumeration
);
2446 int dib9000_set_slave_frontend(struct dvb_frontend
*fe
, struct dvb_frontend
*fe_slave
)
2448 struct dib9000_state
*state
= fe
->demodulator_priv
;
2449 u8 index_frontend
= 1;
2451 while ((index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
))
2453 if (index_frontend
< MAX_NUMBER_OF_FRONTENDS
) {
2454 dprintk("set slave fe %p to index %i", fe_slave
, index_frontend
);
2455 state
->fe
[index_frontend
] = fe_slave
;
2459 dprintk("too many slave frontend");
2462 EXPORT_SYMBOL(dib9000_set_slave_frontend
);
2464 int dib9000_remove_slave_frontend(struct dvb_frontend
*fe
)
2466 struct dib9000_state
*state
= fe
->demodulator_priv
;
2467 u8 index_frontend
= 1;
2469 while ((index_frontend
< MAX_NUMBER_OF_FRONTENDS
) && (state
->fe
[index_frontend
] != NULL
))
2471 if (index_frontend
!= 1) {
2472 dprintk("remove slave fe %p (index %i)", state
->fe
[index_frontend
- 1], index_frontend
- 1);
2473 state
->fe
[index_frontend
] = NULL
;
2477 dprintk("no frontend to be removed");
2480 EXPORT_SYMBOL(dib9000_remove_slave_frontend
);
2482 struct dvb_frontend
*dib9000_get_slave_frontend(struct dvb_frontend
*fe
, int slave_index
)
2484 struct dib9000_state
*state
= fe
->demodulator_priv
;
2486 if (slave_index
>= MAX_NUMBER_OF_FRONTENDS
)
2488 return state
->fe
[slave_index
];
2490 EXPORT_SYMBOL(dib9000_get_slave_frontend
);
2492 static struct dvb_frontend_ops dib9000_ops
;
2493 struct dvb_frontend
*dib9000_attach(struct i2c_adapter
*i2c_adap
, u8 i2c_addr
, const struct dib9000_config
*cfg
)
2495 struct dvb_frontend
*fe
;
2496 struct dib9000_state
*st
;
2497 st
= kzalloc(sizeof(struct dib9000_state
), GFP_KERNEL
);
2500 fe
= kzalloc(sizeof(struct dvb_frontend
), GFP_KERNEL
);
2506 memcpy(&st
->chip
.d9
.cfg
, cfg
, sizeof(struct dib9000_config
));
2507 st
->i2c
.i2c_adap
= i2c_adap
;
2508 st
->i2c
.i2c_addr
= i2c_addr
;
2509 st
->i2c
.i2c_write_buffer
= st
->i2c_write_buffer
;
2510 st
->i2c
.i2c_read_buffer
= st
->i2c_read_buffer
;
2512 st
->gpio_dir
= DIB9000_GPIO_DEFAULT_DIRECTIONS
;
2513 st
->gpio_val
= DIB9000_GPIO_DEFAULT_VALUES
;
2514 st
->gpio_pwm_pos
= DIB9000_GPIO_DEFAULT_PWM_POS
;
2516 DibInitLock(&st
->platform
.risc
.mbx_if_lock
);
2517 DibInitLock(&st
->platform
.risc
.mbx_lock
);
2518 DibInitLock(&st
->platform
.risc
.mem_lock
);
2519 DibInitLock(&st
->platform
.risc
.mem_mbx_lock
);
2520 DibInitLock(&st
->demod_lock
);
2521 st
->get_frontend_internal
= 0;
2523 st
->pid_ctrl_index
= -2;
2526 fe
->demodulator_priv
= st
;
2527 memcpy(&st
->fe
[0]->ops
, &dib9000_ops
, sizeof(struct dvb_frontend_ops
));
2529 /* Ensure the output mode remains at the previous default if it's
2530 * not specifically set by the caller.
2532 if ((st
->chip
.d9
.cfg
.output_mode
!= OUTMODE_MPEG2_SERIAL
) && (st
->chip
.d9
.cfg
.output_mode
!= OUTMODE_MPEG2_PAR_GATED_CLK
))
2533 st
->chip
.d9
.cfg
.output_mode
= OUTMODE_MPEG2_FIFO
;
2535 if (dib9000_identify(&st
->i2c
) == 0)
2538 dibx000_init_i2c_master(&st
->i2c_master
, DIB7000MC
, st
->i2c
.i2c_adap
, st
->i2c
.i2c_addr
);
2540 st
->tuner_adap
.dev
.parent
= i2c_adap
->dev
.parent
;
2541 strncpy(st
->tuner_adap
.name
, "DIB9000_FW TUNER ACCESS", sizeof(st
->tuner_adap
.name
));
2542 st
->tuner_adap
.algo
= &dib9000_tuner_algo
;
2543 st
->tuner_adap
.algo_data
= NULL
;
2544 i2c_set_adapdata(&st
->tuner_adap
, st
);
2545 if (i2c_add_adapter(&st
->tuner_adap
) < 0)
2548 st
->component_bus
.dev
.parent
= i2c_adap
->dev
.parent
;
2549 strncpy(st
->component_bus
.name
, "DIB9000_FW COMPONENT BUS ACCESS", sizeof(st
->component_bus
.name
));
2550 st
->component_bus
.algo
= &dib9000_component_bus_algo
;
2551 st
->component_bus
.algo_data
= NULL
;
2552 st
->component_bus_speed
= 340;
2553 i2c_set_adapdata(&st
->component_bus
, st
);
2554 if (i2c_add_adapter(&st
->component_bus
) < 0)
2555 goto component_bus_add_error
;
2557 dib9000_fw_reset(fe
);
2561 component_bus_add_error
:
2562 i2c_del_adapter(&st
->tuner_adap
);
2567 EXPORT_SYMBOL(dib9000_attach
);
2569 static struct dvb_frontend_ops dib9000_ops
= {
2570 .delsys
= { SYS_DVBT
},
2572 .name
= "DiBcom 9000",
2573 .frequency_min
= 44250000,
2574 .frequency_max
= 867250000,
2575 .frequency_stepsize
= 62500,
2576 .caps
= FE_CAN_INVERSION_AUTO
|
2577 FE_CAN_FEC_1_2
| FE_CAN_FEC_2_3
| FE_CAN_FEC_3_4
|
2578 FE_CAN_FEC_5_6
| FE_CAN_FEC_7_8
| FE_CAN_FEC_AUTO
|
2579 FE_CAN_QPSK
| FE_CAN_QAM_16
| FE_CAN_QAM_64
| FE_CAN_QAM_AUTO
|
2580 FE_CAN_TRANSMISSION_MODE_AUTO
| FE_CAN_GUARD_INTERVAL_AUTO
| FE_CAN_RECOVER
| FE_CAN_HIERARCHY_AUTO
,
2583 .release
= dib9000_release
,
2585 .init
= dib9000_wakeup
,
2586 .sleep
= dib9000_sleep
,
2588 .set_frontend
= dib9000_set_frontend
,
2589 .get_tune_settings
= dib9000_fe_get_tune_settings
,
2590 .get_frontend
= dib9000_get_frontend
,
2592 .read_status
= dib9000_read_status
,
2593 .read_ber
= dib9000_read_ber
,
2594 .read_signal_strength
= dib9000_read_signal_strength
,
2595 .read_snr
= dib9000_read_snr
,
2596 .read_ucblocks
= dib9000_read_unc_blocks
,
2599 MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
2600 MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
2601 MODULE_DESCRIPTION("Driver for the DiBcom 9000 COFDM demodulator");
2602 MODULE_LICENSE("GPL");