arch/powerpc/platforms/86xx/mpc86xx_hpcn.c

   1 /*
   2  * MPC86xx HPCN board specific routines
   3  *
   4  * Recode: ZHANG WEI <wei.zhang@freescale.com>
   5  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   6  *
   7  * Copyright 2006 Freescale Semiconductor Inc.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 #include <linux/stddef.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/kdev_t.h>
  19 #include <linux/delay.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/root_dev.h>
  22
  23 #include <asm/system.h>
  24 #include <asm/time.h>
  25 #include <asm/machdep.h>
  26 #include <asm/pci-bridge.h>
  27 #include <asm/mpc86xx.h>
  28 #include <asm/prom.h>
  29 #include <mm/mmu_decl.h>
  30 #include <asm/udbg.h>
  31 #include <asm/i8259.h>
  32
  33 #include <asm/mpic.h>
  34
  35 #include <sysdev/fsl_soc.h>
  36
  37 #include "mpc86xx.h"
  38
  39 #ifndef CONFIG_PCI
  40 unsigned long isa_io_base = 0;
  41 unsigned long isa_mem_base = 0;
  42 unsigned long pci_dram_offset = 0;
  43 #endif
  44
  45
  46 /*
  47  * Internal interrupts are all Level Sensitive, and Positive Polarity
  48  */
  49
  50 static u_char mpc86xx_hpcn_openpic_initsenses[] __initdata = {
  51         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  0: Reserved */
  52         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  1: MCM */
  53         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  2: DDR DRAM */
  54         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  3: LBIU */
  55         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  4: DMA 0 */
  56         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  5: DMA 1 */
  57         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  6: DMA 2 */
  58         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  7: DMA 3 */
  59         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  8: PCIE1 */
  60         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  9: PCIE2 */
  61         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 10: Reserved */
  62         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 11: Reserved */
  63         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 12: DUART2 */
  64         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 13: TSEC 1 Transmit */
  65         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 14: TSEC 1 Receive */
  66         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 15: TSEC 3 transmit */
  67         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 16: TSEC 3 receive */
  68         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 17: TSEC 3 error */
  69         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 18: TSEC 1 Receive/Transmit Error */
  70         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 19: TSEC 2 Transmit */
  71         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 20: TSEC 2 Receive */
  72         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 21: TSEC 4 transmit */
  73         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 22: TSEC 4 receive */
  74         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 23: TSEC 4 error */
  75         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 24: TSEC 2 Receive/Transmit Error */
  76         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 25: Unused */
  77         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 26: DUART1 */
  78         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 27: I2C */
  79         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 28: Performance Monitor */
  80         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 29: Unused */
  81         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 30: Unused */
  82         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 31: Unused */
  83         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 32: SRIO error/write-port unit */
  84         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 33: SRIO outbound doorbell */
  85         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 34: SRIO inbound doorbell */
  86         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 35: Unused */
  87         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 36: Unused */
  88         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 37: SRIO outbound message unit 1 */
  89         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 38: SRIO inbound message unit 1 */
  90         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 39: SRIO outbound message unit 2 */
  91         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 40: SRIO inbound message unit 2 */
  92         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 41: Unused */
  93         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 42: Unused */
  94         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 43: Unused */
  95         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 44: Unused */
  96         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 45: Unused */
  97         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 46: Unused */
  98         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 47: Unused */
  99         0x0,                                            /* External  0: */
 100         0x0,                                            /* External  1: */
 101         0x0,                                            /* External  2: */
 102         0x0,                                            /* External  3: */
 103         0x0,                                            /* External  4: */
 104         0x0,                                            /* External  5: */
 105         0x0,                                            /* External  6: */
 106         0x0,                                            /* External  7: */
 107         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External  8: Pixis FPGA */
 108         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* External  9: ULI 8259 INTR Cascade */
 109         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 10: Quad ETH PHY */
 110         0x0,                                            /* External 11: */
 111         0x0,
 112         0x0,
 113         0x0,
 114         0x0,
 115 };
 116
 117
 118 void __init
 119 mpc86xx_hpcn_init_irq(void)
 120 {
 121         struct mpic *mpic1;
 122         phys_addr_t openpic_paddr;
 123
 124         /* Determine the Physical Address of the OpenPIC regs */
 125         openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
 126
 127         /* Alloc mpic structure and per isu has 16 INT entries. */
 128         mpic1 = mpic_alloc(openpic_paddr,
 129                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
 130                         16, MPC86xx_OPENPIC_IRQ_OFFSET, 0, 250,
 131                         mpc86xx_hpcn_openpic_initsenses,
 132                         sizeof(mpc86xx_hpcn_openpic_initsenses),
 133                         " MPIC     ");
 134         BUG_ON(mpic1 == NULL);
 135
 136         /* 48 Internal Interrupts */
 137         mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10200);
 138         mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10400);
 139         mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10600);
 140
 141         /* 16 External interrupts */
 142         mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10000);
 143
 144         mpic_init(mpic1);
 145
 146 #ifdef CONFIG_PCI
 147         mpic_setup_cascade(MPC86xx_IRQ_EXT9, i8259_irq_cascade, NULL);
 148         i8259_init(0, I8259_OFFSET);
 149 #endif
 150 }
 151
 152
 153
 154 #ifdef CONFIG_PCI
 155 /*
 156  * interrupt routing
 157  */
 158
 159 int
 160 mpc86xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 161 {
 162         static char pci_irq_table[][4] = {
 163                 /*
 164                  *      PCI IDSEL/INTPIN->INTLINE
 165                  *       A      B      C      D
 166                  */
 167                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 17 -- PCI Slot 1 */
 168                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 18 -- PCI Slot 2 */
 169                 {0, 0, 0, 0},                   /* IDSEL 19 */
 170                 {0, 0, 0, 0},                   /* IDSEL 20 */
 171                 {0, 0, 0, 0},                   /* IDSEL 21 */
 172                 {0, 0, 0, 0},                   /* IDSEL 22 */
 173                 {0, 0, 0, 0},                   /* IDSEL 23 */
 174                 {0, 0, 0, 0},                   /* IDSEL 24 */
 175                 {0, 0, 0, 0},                   /* IDSEL 25 */
 176                 {PIRQD, PIRQA, PIRQB, PIRQC},   /* IDSEL 26 -- PCI Bridge*/
 177                 {PIRQC, 0, 0, 0},               /* IDSEL 27 -- LAN */
 178                 {PIRQE, PIRQF, PIRQH, PIRQ7},   /* IDSEL 28 -- USB 1.1 */
 179                 {PIRQE, PIRQF, PIRQG, 0},       /* IDSEL 29 -- Audio & Modem */
 180                 {PIRQH, 0, 0, 0},               /* IDSEL 30 -- LPC & PMU*/
 181                 {PIRQD, 0, 0, 0},               /* IDSEL 31 -- ATA */
 182         };
 183
 184         const long min_idsel = 17, max_idsel = 31, irqs_per_slot = 4;
 185         return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET;
 186 }
 187
 188
 189 int
 190 mpc86xx_exclude_device(u_char bus, u_char devfn)
 191 {
 192 #if !defined(CONFIG_PCI)
 193         if (bus == 0 && PCI_SLOT(devfn) == 0)
 194                 return PCIBIOS_DEVICE_NOT_FOUND;
 195 #endif
 196
 197         return PCIBIOS_SUCCESSFUL;
 198 }
 199 #endif /* CONFIG_PCI */
 200
 201
 202 static void __init
 203 mpc86xx_hpcn_setup_arch(void)
 204 {
 205         struct device_node *np;
 206
 207         if (ppc_md.progress)
 208                 ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
 209
 210         np = of_find_node_by_type(NULL, "cpu");
 211         if (np != 0) {
 212                 unsigned int *fp;
 213
 214                 fp = (int *)get_property(np, "clock-frequency", NULL);
 215                 if (fp != 0)
 216                         loops_per_jiffy = *fp / HZ;
 217                 else
 218                         loops_per_jiffy = 50000000 / HZ;
 219                 of_node_put(np);
 220         }
 221
 222 #ifdef CONFIG_PCI
 223         for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
 224                 add_bridge(np);
 225
 226         ppc_md.pci_swizzle = common_swizzle;
 227         ppc_md.pci_map_irq = mpc86xx_map_irq;
 228         ppc_md.pci_exclude_device = mpc86xx_exclude_device;
 229 #endif
 230
 231         printk("MPC86xx HPCN board from Freescale Semiconductor\n");
 232
 233 #ifdef  CONFIG_ROOT_NFS
 234         ROOT_DEV = Root_NFS;
 235 #else
 236         ROOT_DEV = Root_HDA1;
 237 #endif
 238
 239 #ifdef CONFIG_SMP
 240         mpc86xx_smp_init();
 241 #endif
 242 }
 243
 244
 245 void
 246 mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
 247 {
 248         struct device_node *root;
 249         uint memsize = total_memory;
 250         const char *model = "";
 251         uint svid = mfspr(SPRN_SVR);
 252
 253         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 254
 255         root = of_find_node_by_path("/");
 256         if (root)
 257                 model = get_property(root, "model", NULL);
 258         seq_printf(m, "Machine\t\t: %s\n", model);
 259         of_node_put(root);
 260
 261         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 262         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 263 }
 264
 265
 266 /*
 267  * Called very early, device-tree isn't unflattened
 268  */
 269 static int __init mpc86xx_hpcn_probe(void)
 270 {
 271         unsigned long root = of_get_flat_dt_root();
 272
 273         if (of_flat_dt_is_compatible(root, "mpc86xx"))
 274                 return 1;       /* Looks good */
 275
 276         return 0;
 277 }
 278
 279
 280 void
 281 mpc86xx_restart(char *cmd)
 282 {
 283         void __iomem *rstcr;
 284
 285         rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
 286
 287         local_irq_disable();
 288
 289         /* Assert reset request to Reset Control Register */
 290         out_be32(rstcr, 0x2);
 291
 292         /* not reached */
 293 }
 294
 295
 296 long __init
 297 mpc86xx_time_init(void)
 298 {
 299         unsigned int temp;
 300
 301         /* Set the time base to zero */
 302         mtspr(SPRN_TBWL, 0);
 303         mtspr(SPRN_TBWU, 0);
 304
 305         temp = mfspr(SPRN_HID0);
 306         temp |= HID0_TBEN;
 307         mtspr(SPRN_HID0, temp);
 308         asm volatile("isync");
 309
 310         return 0;
 311 }
 312
 313
 314 define_machine(mpc86xx_hpcn) {
 315         .name                   = "MPC86xx HPCN",
 316         .probe                  = mpc86xx_hpcn_probe,
 317         .setup_arch             = mpc86xx_hpcn_setup_arch,
 318         .init_IRQ               = mpc86xx_hpcn_init_irq,
 319         .show_cpuinfo           = mpc86xx_hpcn_show_cpuinfo,
 320         .get_irq                = mpic_get_irq,
 321         .restart                = mpc86xx_restart,
 322         .time_init              = mpc86xx_time_init,
 323         .calibrate_decr         = generic_calibrate_decr,
 324         .progress               = udbg_progress,
 325 };