drivers/staging/sxg/sxg.c

   1 /**************************************************************************
   2  *
   3  * Copyright (C) 2000-2008 Alacritech, Inc.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above
  12  *    copyright notice, this list of conditions and the following
  13  *    disclaimer in the documentation and/or other materials provided
  14  *    with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
  17  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ALACRITECH, INC. OR
  20  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  23  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  24  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  25  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  26  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * The views and conclusions contained in the software and documentation
  30  * are those of the authors and should not be interpreted as representing
  31  * official policies, either expressed or implied, of Alacritech, Inc.
  32  *
  33  * Parts developed by LinSysSoft Sahara team
  34  *
  35  **************************************************************************/
  36
  37 /*
  38  * FILENAME: sxg.c
  39  *
  40  * The SXG driver for Alacritech's 10Gbe products.
  41  *
  42  * NOTE: This is the standard, non-accelerated version of Alacritech's
  43  *       IS-NIC driver.
  44  */
  45
  46 #include <linux/kernel.h>
  47 #include <linux/string.h>
  48 #include <linux/errno.h>
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/ioport.h>
  52 #include <linux/slab.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/timer.h>
  55 #include <linux/pci.h>
  56 #include <linux/spinlock.h>
  57 #include <linux/init.h>
  58 #include <linux/netdevice.h>
  59 #include <linux/etherdevice.h>
  60 #include <linux/ethtool.h>
  61 #include <linux/skbuff.h>
  62 #include <linux/delay.h>
  63 #include <linux/types.h>
  64 #include <linux/dma-mapping.h>
  65 #include <linux/mii.h>
  66 #include <linux/ip.h>
  67 #include <linux/in.h>
  68 #include <linux/tcp.h>
  69 #include <linux/ipv6.h>
  70
  71 #define SLIC_GET_STATS_ENABLED          0
  72 #define LINUX_FREES_ADAPTER_RESOURCES   1
  73 #define SXG_OFFLOAD_IP_CHECKSUM         0
  74 #define SXG_POWER_MANAGEMENT_ENABLED    0
  75 #define VPCI                            0
  76 #define ATK_DEBUG                       1
  77
  78 #include "sxg_os.h"
  79 #include "sxghw.h"
  80 #include "sxghif.h"
  81 #include "sxg.h"
  82 #include "sxgdbg.h"
  83
  84 #include "sxgphycode-1.2.h"
  85 #define SXG_UCODE_DBG                   0       /* Turn on for debugging */
  86 #ifdef SXG_UCODE_DBG
  87 #include "saharadbgdownload-1.71.c"
  88 #include "saharadbgdownloadB-1.10.c"
  89 #else
  90 #include "saharadownload-1.55.c"
  91 #include "saharadownloadB-1.8.c"
  92 #endif
  93
  94 static int sxg_allocate_buffer_memory(struct adapter_t *adapter, u32 Size,
  95                                       enum sxg_buffer_type BufferType);
  96 static int sxg_allocate_rcvblock_complete(struct adapter_t *adapter,
  97                                                 void *RcvBlock,
  98                                                 dma_addr_t PhysicalAddress,
  99                                                 u32 Length);
 100 static void sxg_allocate_sgl_buffer_complete(struct adapter_t *adapter,
 101                                              struct sxg_scatter_gather *SxgSgl,
 102                                              dma_addr_t PhysicalAddress,
 103                                              u32 Length);
 104
 105 static void sxg_mcast_init_crc32(void);
 106 static int sxg_entry_open(struct net_device *dev);
 107 static int sxg_second_open(struct net_device * dev);
 108 static int sxg_entry_halt(struct net_device *dev);
 109 static int sxg_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 110 static int sxg_send_packets(struct sk_buff *skb, struct net_device *dev);
 111 static int sxg_transmit_packet(struct adapter_t *adapter, struct sk_buff *skb);
 112 static int sxg_dumb_sgl(struct sxg_x64_sgl *pSgl,
 113                                 struct sxg_scatter_gather *SxgSgl);
 114
 115 static void sxg_handle_interrupt(struct adapter_t *adapter, int *work_done,
 116                                          int budget);
 117 static void sxg_interrupt(struct adapter_t *adapter);
 118 static int sxg_poll(struct napi_struct *napi, int budget);
 119 static int sxg_process_isr(struct adapter_t *adapter, u32 MessageId);
 120 static u32 sxg_process_event_queue(struct adapter_t *adapter, u32 RssId,
 121                          int *sxg_napi_continue, int *work_done, int budget);
 122 static void sxg_complete_slow_send(struct adapter_t *adapter);
 123 static struct sk_buff *sxg_slow_receive(struct adapter_t *adapter,
 124                                         struct sxg_event *Event);
 125 static void sxg_process_rcv_error(struct adapter_t *adapter, u32 ErrorStatus);
 126 static bool sxg_mac_filter(struct adapter_t *adapter,
 127                            struct ether_header *EtherHdr, ushort length);
 128 static struct net_device_stats *sxg_get_stats(struct net_device * dev);
 129 void sxg_free_resources(struct adapter_t *adapter);
 130 void sxg_free_rcvblocks(struct adapter_t *adapter);
 131 void sxg_free_sgl_buffers(struct adapter_t *adapter);
 132 void sxg_unmap_resources(struct adapter_t *adapter);
 133 void sxg_free_mcast_addrs(struct adapter_t *adapter);
 134 void sxg_collect_statistics(struct adapter_t *adapter);
 135 static int sxg_register_interrupt(struct adapter_t *adapter);
 136 static void sxg_remove_isr(struct adapter_t *adapter);
 137 static irqreturn_t sxg_isr(int irq, void *dev_id);
 138
 139 #define XXXTODO 0
 140
 141 #if XXXTODO
 142 static int sxg_mac_set_address(struct net_device *dev, void *ptr);
 143 #endif
 144 static void sxg_mcast_set_list(struct net_device *dev);
 145
 146 static int sxg_adapter_set_hwaddr(struct adapter_t *adapter);
 147
 148 static int sxg_initialize_adapter(struct adapter_t *adapter);
 149 static void sxg_stock_rcv_buffers(struct adapter_t *adapter);
 150 static void sxg_complete_descriptor_blocks(struct adapter_t *adapter,
 151                                            unsigned char Index);
 152 int sxg_change_mtu (struct net_device *netdev, int new_mtu);
 153 static int sxg_initialize_link(struct adapter_t *adapter);
 154 static int sxg_phy_init(struct adapter_t *adapter);
 155 static void sxg_link_event(struct adapter_t *adapter);
 156 static enum SXG_LINK_STATE sxg_get_link_state(struct adapter_t *adapter);
 157 static void sxg_link_state(struct adapter_t *adapter,
 158                                 enum SXG_LINK_STATE LinkState);
 159 static int sxg_write_mdio_reg(struct adapter_t *adapter,
 160                               u32 DevAddr, u32 RegAddr, u32 Value);
 161 static int sxg_read_mdio_reg(struct adapter_t *adapter,
 162                              u32 DevAddr, u32 RegAddr, u32 *pValue);
 163 static void sxg_set_mcast_addr(struct adapter_t *adapter);
 164
 165 static unsigned int sxg_first_init = 1;
 166 static char *sxg_banner =
 167     "Alacritech SLIC Technology(tm) Server and Storage \
 168          10Gbe Accelerator (Non-Accelerated)\n";
 169
 170 static int sxg_debug = 1;
 171 static int debug = -1;
 172 static struct net_device *head_netdevice = NULL;
 173
 174 static struct sxgbase_driver sxg_global = {
 175         .dynamic_intagg = 1,
 176 };
 177 static int intagg_delay = 100;
 178 static u32 dynamic_intagg = 0;
 179
 180 char sxg_driver_name[] = "sxg_nic";
 181 #define DRV_AUTHOR      "Alacritech, Inc. Engineering"
 182 #define DRV_DESCRIPTION                                                 \
 183         "Alacritech SLIC Techonology(tm) Non-Accelerated 10Gbe Driver"
 184 #define DRV_COPYRIGHT                                                   \
 185         "Copyright 2000-2008 Alacritech, Inc.  All rights reserved."
 186
 187 MODULE_AUTHOR(DRV_AUTHOR);
 188 MODULE_DESCRIPTION(DRV_DESCRIPTION);
 189 MODULE_LICENSE("GPL");
 190
 191 module_param(dynamic_intagg, int, 0);
 192 MODULE_PARM_DESC(dynamic_intagg, "Dynamic Interrupt Aggregation Setting");
 193 module_param(intagg_delay, int, 0);
 194 MODULE_PARM_DESC(intagg_delay, "uSec Interrupt Aggregation Delay");
 195
 196 static struct pci_device_id sxg_pci_tbl[] __devinitdata = {
 197         {PCI_DEVICE(SXG_VENDOR_ID, SXG_DEVICE_ID)},
 198         {0,}
 199 };
 200
 201 MODULE_DEVICE_TABLE(pci, sxg_pci_tbl);
 202
 203 static inline void sxg_reg32_write(void __iomem *reg, u32 value, bool flush)
 204 {
 205         writel(value, reg);
 206         if (flush)
 207                 mb();
 208 }
 209
 210 static inline void sxg_reg64_write(struct adapter_t *adapter, void __iomem *reg,
 211                                    u64 value, u32 cpu)
 212 {
 213         u32 value_high = (u32) (value >> 32);
 214         u32 value_low = (u32) (value & 0x00000000FFFFFFFF);
 215         unsigned long flags;
 216
 217         spin_lock_irqsave(&adapter->Bit64RegLock, flags);
 218         writel(value_high, (void __iomem *)(&adapter->UcodeRegs[cpu].Upper));
 219         writel(value_low, reg);
 220         spin_unlock_irqrestore(&adapter->Bit64RegLock, flags);
 221 }
 222
 223 static void sxg_init_driver(void)
 224 {
 225         if (sxg_first_init) {
 226                 DBG_ERROR("sxg: %s sxg_first_init set jiffies[%lx]\n",
 227                           __func__, jiffies);
 228                 sxg_first_init = 0;
 229                 spin_lock_init(&sxg_global.driver_lock);
 230         }
 231 }
 232
 233 static void sxg_dbg_macaddrs(struct adapter_t *adapter)
 234 {
 235         DBG_ERROR("  (%s) curr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
 236                   adapter->netdev->name, adapter->currmacaddr[0],
 237                   adapter->currmacaddr[1], adapter->currmacaddr[2],
 238                   adapter->currmacaddr[3], adapter->currmacaddr[4],
 239                   adapter->currmacaddr[5]);
 240         DBG_ERROR("  (%s) mac  %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
 241                   adapter->netdev->name, adapter->macaddr[0],
 242                   adapter->macaddr[1], adapter->macaddr[2],
 243                   adapter->macaddr[3], adapter->macaddr[4],
 244                   adapter->macaddr[5]);
 245         return;
 246 }
 247
 248 /* SXG Globals */
 249 static struct sxg_driver SxgDriver;
 250
 251 #ifdef  ATKDBG
 252 static struct sxg_trace_buffer LSxgTraceBuffer;
 253 #endif /* ATKDBG */
 254 static struct sxg_trace_buffer *SxgTraceBuffer = NULL;
 255
 256 /*
 257  * MSI Related API's
 258  */
 259 int sxg_register_intr(struct adapter_t *adapter);
 260 int sxg_enable_msi_x(struct adapter_t *adapter);
 261 int sxg_add_msi_isr(struct adapter_t *adapter);
 262 void sxg_remove_msix_isr(struct adapter_t *adapter);
 263 int sxg_set_interrupt_capability(struct adapter_t *adapter);
 264
 265 int sxg_set_interrupt_capability(struct adapter_t *adapter)
 266 {
 267         int ret;
 268
 269         ret = sxg_enable_msi_x(adapter);
 270         if (ret != STATUS_SUCCESS) {
 271                 adapter->msi_enabled = FALSE;
 272                 DBG_ERROR("sxg_set_interrupt_capability MSI-X Disable\n");
 273         } else {
 274                 adapter->msi_enabled = TRUE;
 275                 DBG_ERROR("sxg_set_interrupt_capability MSI-X Enable\n");
 276         }
 277         return ret;
 278 }
 279
 280 int sxg_register_intr(struct adapter_t *adapter)
 281 {
 282         int ret = 0;
 283
 284         if (adapter->msi_enabled) {
 285                 ret = sxg_add_msi_isr(adapter);
 286         }
 287         else {
 288                 DBG_ERROR("MSI-X Enable Failed. Using Pin INT\n");
 289                 ret = sxg_register_interrupt(adapter);
 290                 if (ret != STATUS_SUCCESS) {
 291                         DBG_ERROR("sxg_register_interrupt Failed\n");
 292                 }
 293         }
 294         return ret;
 295 }
 296
 297 int sxg_enable_msi_x(struct adapter_t *adapter)
 298 {
 299         int ret;
 300
 301         adapter->nr_msix_entries = 1;
 302         adapter->msi_entries =  kmalloc(adapter->nr_msix_entries *
 303                                         sizeof(struct msix_entry),GFP_KERNEL);
 304         if (!adapter->msi_entries) {
 305                 DBG_ERROR("%s:MSI Entries memory allocation Failed\n",__func__);
 306                 return -ENOMEM;
 307         }
 308         memset(adapter->msi_entries, 0, adapter->nr_msix_entries *
 309                 sizeof(struct msix_entry));
 310
 311         ret = pci_enable_msix(adapter->pcidev, adapter->msi_entries,
 312                                 adapter->nr_msix_entries);
 313         if (ret) {
 314                 DBG_ERROR("Enabling MSI-X with %d vectors failed\n",
 315                                 adapter->nr_msix_entries);
 316                 /*Should try with less vector returned.*/
 317                 kfree(adapter->msi_entries);
 318                 return STATUS_FAILURE; /*MSI-X Enable failed.*/
 319         }
 320         return (STATUS_SUCCESS);
 321 }
 322
 323 int sxg_add_msi_isr(struct adapter_t *adapter)
 324 {
 325         int ret,i;
 326
 327         if (!adapter->intrregistered) {
 328                 for (i=0; i<adapter->nr_msix_entries; i++) {
 329                         ret = request_irq (adapter->msi_entries[i].vector,
 330                                         sxg_isr,
 331                                         IRQF_SHARED,
 332                                         adapter->netdev->name,
 333                                         adapter->netdev);
 334                         if (ret) {
 335                                 DBG_ERROR("sxg: MSI-X request_irq (%s) "
 336                                         "FAILED [%x]\n", adapter->netdev->name,
 337                                          ret);
 338                                 return (ret);
 339                         }
 340                 }
 341         }
 342         adapter->msi_enabled = TRUE;
 343         adapter->intrregistered = 1;
 344         adapter->IntRegistered = TRUE;
 345         return (STATUS_SUCCESS);
 346 }
 347
 348 void sxg_remove_msix_isr(struct adapter_t *adapter)
 349 {
 350         int i,vector;
 351         struct net_device *netdev = adapter->netdev;
 352
 353         for(i=0; i< adapter->nr_msix_entries;i++)
 354         {
 355                 vector = adapter->msi_entries[i].vector;
 356                 DBG_ERROR("%s : Freeing IRQ vector#%d\n",__FUNCTION__,vector);
 357                 free_irq(vector,netdev);
 358         }
 359 }
 360
 361
 362 static void sxg_remove_isr(struct adapter_t *adapter)
 363 {
 364         struct net_device *netdev = adapter->netdev;
 365         if (adapter->msi_enabled)
 366                 sxg_remove_msix_isr(adapter);
 367         else
 368                 free_irq(adapter->netdev->irq, netdev);
 369 }
 370
 371 void sxg_reset_interrupt_capability(struct adapter_t *adapter)
 372 {
 373         if (adapter->msi_enabled) {
 374                 pci_disable_msix(adapter->pcidev);
 375                 kfree(adapter->msi_entries);
 376                 adapter->msi_entries = NULL;
 377         }
 378         return;
 379 }
 380
 381 /*
 382  * sxg_download_microcode
 383  *
 384  * Download Microcode to Sahara adapter
 385  *
 386  * Arguments -
 387  *              adapter         - A pointer to our adapter structure
 388  *              UcodeSel        - microcode file selection
 389  *
 390  * Return
 391  *      int
 392  */
 393 static bool sxg_download_microcode(struct adapter_t *adapter,
 394                                                 enum SXG_UCODE_SEL UcodeSel)
 395 {
 396         struct sxg_hw_regs *HwRegs = adapter->HwRegs;
 397         u32 Section;
 398         u32 ThisSectionSize;
 399         u32 *Instruction = NULL;
 400         u32 BaseAddress, AddressOffset, Address;
 401         /* u32 Failure; */
 402         u32 ValueRead;
 403         u32 i;
 404         u32 numSections = 0;
 405         u32 sectionSize[16];
 406         u32 sectionStart[16];
 407
 408         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DnldUcod",
 409                   adapter, 0, 0, 0);
 410         DBG_ERROR("sxg: %s ENTER\n", __func__);
 411
 412         switch (UcodeSel) {
 413                 case SXG_UCODE_SYSTEM:      // System (operational) ucode
 414                         switch (adapter->asictype) {
 415                                 case SAHARA_REV_A:
 416                                         DBG_ERROR("%s SAHARA CARD REVISION A\n",
 417                                                  __func__);
 418                                         numSections = SNumSections;
 419                                         for (i = 0; i < numSections; i++) {
 420                                                 sectionSize[i] =
 421                                                         SSectionSize[i];
 422                                                 sectionStart[i] =
 423                                                         SSectionStart[i];
 424                                         }
 425                                         break;
 426                                 case SAHARA_REV_B:
 427                                         DBG_ERROR("%s SAHARA CARD REVISION B\n",
 428                                                  __func__);
 429                                         numSections = SBNumSections;
 430                                         for (i = 0; i < numSections; i++) {
 431                                                 sectionSize[i] =
 432                                                         SBSectionSize[i];
 433                                                 sectionStart[i] =
 434                                                         SBSectionStart[i];
 435                                         }
 436                                         break;
 437                         }
 438                         break;
 439                 default:
 440                         printk(KERN_ERR KBUILD_MODNAME
 441                                 ": Woah, big error with the microcode!\n");
 442                         break;
 443         }
 444
 445         DBG_ERROR("sxg: RESET THE CARD\n");
 446         /* First, reset the card */
 447         WRITE_REG(HwRegs->Reset, 0xDEAD, FLUSH);
 448         udelay(50);
 449
 450         /*
 451          * Download each section of the microcode as specified in
 452          * its download file.  The *download.c file is generated using
 453          * the saharaobjtoc facility which converts the metastep .obj
 454          * file to a .c file which contains a two dimentional array.
 455          */
 456         for (Section = 0; Section < numSections; Section++) {
 457                 DBG_ERROR("sxg: SECTION # %d\n", Section);
 458                 switch (UcodeSel) {
 459                 case SXG_UCODE_SYSTEM:
 460                         switch (adapter->asictype) {
 461                                 case SAHARA_REV_A:
 462                                         Instruction = (u32 *) & SaharaUCode[Section][0];
 463                                         break;
 464                                 case SAHARA_REV_B:
 465                                         Instruction = (u32 *) & SaharaUCodeB[Section][0];
 466                                         break;
 467                         }
 468                         break;
 469                 default:
 470                         ASSERT(0);
 471                         break;
 472                 }
 473
 474                 BaseAddress = sectionStart[Section];
 475                 /* Size in instructions */
 476                 ThisSectionSize = sectionSize[Section] / 12;
 477                 for (AddressOffset = 0; AddressOffset < ThisSectionSize;
 478                      AddressOffset++) {
 479                         Address = BaseAddress + AddressOffset;
 480                         ASSERT((Address & ~MICROCODE_ADDRESS_MASK) == 0);
 481                         /* Write instruction bits 31 - 0 */
 482                         WRITE_REG(HwRegs->UcodeDataLow, *Instruction, FLUSH);
 483                         /* Write instruction bits 63-32 */
 484                         WRITE_REG(HwRegs->UcodeDataMiddle, *(Instruction + 1),
 485                                   FLUSH);
 486                         /* Write instruction bits 95-64 */
 487                         WRITE_REG(HwRegs->UcodeDataHigh, *(Instruction + 2),
 488                                   FLUSH);
 489                         /* Write instruction address with the WRITE bit set */
 490                         WRITE_REG(HwRegs->UcodeAddr,
 491                                   (Address | MICROCODE_ADDRESS_WRITE), FLUSH);
 492                         /*
 493                          * Sahara bug in the ucode download logic - the write to DataLow
 494                          * for the next instruction could get corrupted.  To avoid this,
 495                          * write to DataLow again for this instruction (which may get
 496                          * corrupted, but it doesn't matter), then increment the address
 497                          * and write the data for the next instruction to DataLow.  That
 498                          * write should succeed.
 499                          */
 500                         WRITE_REG(HwRegs->UcodeDataLow, *Instruction, TRUE);
 501                         /* Advance 3 u32S to start of next instruction */
 502                         Instruction += 3;
 503                 }
 504         }
 505         /*
 506          * Now repeat the entire operation reading the instruction back and
 507          * checking for parity errors
 508          */
 509         for (Section = 0; Section < numSections; Section++) {
 510                 DBG_ERROR("sxg: check SECTION # %d\n", Section);
 511                 switch (UcodeSel) {
 512                         case SXG_UCODE_SYSTEM:
 513                                 switch (adapter->asictype) {
 514                                         case SAHARA_REV_A:
 515                                                 Instruction = (u32 *) &
 516                                                     SaharaUCode[Section][0];
 517                                                 break;
 518                                         case SAHARA_REV_B:
 519                                                 Instruction = (u32 *) &
 520                                                     SaharaUCodeB[Section][0];
 521                                                 break;
 522                                 }
 523                                 break;
 524                         default:
 525                                 ASSERT(0);
 526                                 break;
 527                 }
 528                 BaseAddress = sectionStart[Section];
 529                 /* Size in instructions */
 530                 ThisSectionSize = sectionSize[Section] / 12;
 531                 for (AddressOffset = 0; AddressOffset < ThisSectionSize;
 532                      AddressOffset++) {
 533                         Address = BaseAddress + AddressOffset;
 534                         /* Write the address with the READ bit set */
 535                         WRITE_REG(HwRegs->UcodeAddr,
 536                                   (Address | MICROCODE_ADDRESS_READ), FLUSH);
 537                         /* Read it back and check parity bit. */
 538                         READ_REG(HwRegs->UcodeAddr, ValueRead);
 539                         if (ValueRead & MICROCODE_ADDRESS_PARITY) {
 540                                 DBG_ERROR("sxg: %s PARITY ERROR\n",
 541                                           __func__);
 542
 543                                 return FALSE;   /* Parity error */
 544                         }
 545                         ASSERT((ValueRead & MICROCODE_ADDRESS_MASK) == Address);
 546                         /* Read the instruction back and compare */
 547                         READ_REG(HwRegs->UcodeDataLow, ValueRead);
 548                         if (ValueRead != *Instruction) {
 549                                 DBG_ERROR("sxg: %s MISCOMPARE LOW\n",
 550                                           __func__);
 551                                 return FALSE;   /* Miscompare */
 552                         }
 553                         READ_REG(HwRegs->UcodeDataMiddle, ValueRead);
 554                         if (ValueRead != *(Instruction + 1)) {
 555                                 DBG_ERROR("sxg: %s MISCOMPARE MIDDLE\n",
 556                                           __func__);
 557                                 return FALSE;   /* Miscompare */
 558                         }
 559                         READ_REG(HwRegs->UcodeDataHigh, ValueRead);
 560                         if (ValueRead != *(Instruction + 2)) {
 561                                 DBG_ERROR("sxg: %s MISCOMPARE HIGH\n",
 562                                           __func__);
 563                                 return FALSE;   /* Miscompare */
 564                         }
 565                         /* Advance 3 u32S to start of next instruction */
 566                         Instruction += 3;
 567                 }
 568         }
 569
 570         /* Everything OK, Go. */
 571         WRITE_REG(HwRegs->UcodeAddr, MICROCODE_ADDRESS_GO, FLUSH);
 572
 573         /*
 574          * Poll the CardUp register to wait for microcode to initialize
 575          * Give up after 10,000 attemps (500ms).
 576          */
 577         for (i = 0; i < 10000; i++) {
 578                 udelay(50);
 579                 READ_REG(adapter->UcodeRegs[0].CardUp, ValueRead);
 580                 if (ValueRead == 0xCAFE) {
 581                         DBG_ERROR("sxg: %s BOO YA 0xCAFE\n", __func__);
 582                         break;
 583                 }
 584         }
 585         if (i == 10000) {
 586                 DBG_ERROR("sxg: %s TIMEOUT\n", __func__);
 587
 588                 return FALSE;   /* Timeout */
 589         }
 590         /*
 591          * Now write the LoadSync register.  This is used to
 592          * synchronize with the card so it can scribble on the memory
 593          * that contained 0xCAFE from the "CardUp" step above
 594          */
 595         if (UcodeSel == SXG_UCODE_SYSTEM) {
 596                 WRITE_REG(adapter->UcodeRegs[0].LoadSync, 0, FLUSH);
 597         }
 598
 599         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDnldUcd",
 600                   adapter, 0, 0, 0);
 601         DBG_ERROR("sxg: %s EXIT\n", __func__);
 602
 603         return (TRUE);
 604 }
 605
 606 /*
 607  * sxg_allocate_resources - Allocate memory and locks
 608  *
 609  * Arguments -
 610  *      adapter - A pointer to our adapter structure
 611  *
 612  * Return - int
 613  */
 614 static int sxg_allocate_resources(struct adapter_t *adapter)
 615 {
 616         int status;
 617         u32 i;
 618         u32 RssIds, IsrCount;
 619         /* struct sxg_xmt_ring  *XmtRing; */
 620         /* struct sxg_rcv_ring  *RcvRing; */
 621
 622         DBG_ERROR("%s ENTER\n", __func__);
 623
 624         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocRes",
 625                   adapter, 0, 0, 0);
 626
 627         /* Windows tells us how many CPUs it plans to use for */
 628         /* RSS */
 629         RssIds = SXG_RSS_CPU_COUNT(adapter);
 630         IsrCount = adapter->msi_enabled ? RssIds : 1;
 631
 632         DBG_ERROR("%s Setup the spinlocks\n", __func__);
 633
 634         /* Allocate spinlocks and initialize listheads first. */
 635         spin_lock_init(&adapter->RcvQLock);
 636         spin_lock_init(&adapter->SglQLock);
 637         spin_lock_init(&adapter->XmtZeroLock);
 638         spin_lock_init(&adapter->Bit64RegLock);
 639         spin_lock_init(&adapter->AdapterLock);
 640         atomic_set(&adapter->pending_allocations, 0);
 641
 642         DBG_ERROR("%s Setup the lists\n", __func__);
 643
 644         InitializeListHead(&adapter->FreeRcvBuffers);
 645         InitializeListHead(&adapter->FreeRcvBlocks);
 646         InitializeListHead(&adapter->AllRcvBlocks);
 647         InitializeListHead(&adapter->FreeSglBuffers);
 648         InitializeListHead(&adapter->AllSglBuffers);
 649
 650         /*
 651          * Mark these basic allocations done.  This flags essentially
 652          * tells the SxgFreeResources routine that it can grab spinlocks
 653          * and reference listheads.
 654          */
 655         adapter->BasicAllocations = TRUE;
 656         /*
 657          * Main allocation loop.  Start with the maximum supported by
 658          * the microcode and back off if memory allocation
 659          * fails.  If we hit a minimum, fail.
 660          */
 661
 662         for (;;) {
 663                 DBG_ERROR("%s Allocate XmtRings size[%x]\n", __func__,
 664                           (unsigned int)(sizeof(struct sxg_xmt_ring) * 1));
 665
 666                 /*
 667                  * Start with big items first - receive and transmit rings.
 668                  * At the moment I'm going to keep the ring size fixed and
 669                  * adjust the TCBs if we fail.  Later we might
 670                  * consider reducing the ring size as well..
 671                  */
 672                 adapter->XmtRings = pci_alloc_consistent(adapter->pcidev,
 673                                                  sizeof(struct sxg_xmt_ring) *
 674                                                  1,
 675                                                  &adapter->PXmtRings);
 676                 DBG_ERROR("%s XmtRings[%p]\n", __func__, adapter->XmtRings);
 677
 678                 if (!adapter->XmtRings) {
 679                         goto per_tcb_allocation_failed;
 680                 }
 681                 memset(adapter->XmtRings, 0, sizeof(struct sxg_xmt_ring) * 1);
 682
 683                 DBG_ERROR("%s Allocate RcvRings size[%x]\n", __func__,
 684                           (unsigned int)(sizeof(struct sxg_rcv_ring) * 1));
 685                 adapter->RcvRings =
 686                     pci_alloc_consistent(adapter->pcidev,
 687                                          sizeof(struct sxg_rcv_ring) * 1,
 688                                          &adapter->PRcvRings);
 689                 DBG_ERROR("%s RcvRings[%p]\n", __func__, adapter->RcvRings);
 690                 if (!adapter->RcvRings) {
 691                         goto per_tcb_allocation_failed;
 692                 }
 693                 memset(adapter->RcvRings, 0, sizeof(struct sxg_rcv_ring) * 1);
 694                 adapter->ucode_stats = kzalloc(sizeof(struct sxg_ucode_stats), GFP_ATOMIC);
 695                 adapter->pucode_stats = pci_map_single(adapter->pcidev,
 696                                                 adapter->ucode_stats,
 697                                                 sizeof(struct sxg_ucode_stats),
 698                                                 PCI_DMA_FROMDEVICE);
 699 //              memset(adapter->ucode_stats, 0, sizeof(struct sxg_ucode_stats));
 700                 break;
 701
 702               per_tcb_allocation_failed:
 703                 /* an allocation failed.  Free any successful allocations. */
 704                 if (adapter->XmtRings) {
 705                         pci_free_consistent(adapter->pcidev,
 706                                             sizeof(struct sxg_xmt_ring) * 1,
 707                                             adapter->XmtRings,
 708                                             adapter->PXmtRings);
 709                         adapter->XmtRings = NULL;
 710                 }
 711                 if (adapter->RcvRings) {
 712                         pci_free_consistent(adapter->pcidev,
 713                                             sizeof(struct sxg_rcv_ring) * 1,
 714                                             adapter->RcvRings,
 715                                             adapter->PRcvRings);
 716                         adapter->RcvRings = NULL;
 717                 }
 718                 /* Loop around and try again.... */
 719                 if (adapter->ucode_stats) {
 720                         pci_unmap_single(adapter->pcidev,
 721                                         sizeof(struct sxg_ucode_stats),
 722                                         adapter->pucode_stats, PCI_DMA_FROMDEVICE);
 723                         adapter->ucode_stats = NULL;
 724                 }
 725
 726         }
 727
 728         DBG_ERROR("%s Initialize RCV ZERO and XMT ZERO rings\n", __func__);
 729         /* Initialize rcv zero and xmt zero rings */
 730         SXG_INITIALIZE_RING(adapter->RcvRingZeroInfo, SXG_RCV_RING_SIZE);
 731         SXG_INITIALIZE_RING(adapter->XmtRingZeroInfo, SXG_XMT_RING_SIZE);
 732
 733         /* Sanity check receive data structure format */
 734         /* ASSERT((adapter->ReceiveBufferSize == SXG_RCV_DATA_BUFFER_SIZE) ||
 735                (adapter->ReceiveBufferSize == SXG_RCV_JUMBO_BUFFER_SIZE)); */
 736         ASSERT(sizeof(struct sxg_rcv_descriptor_block) ==
 737                SXG_RCV_DESCRIPTOR_BLOCK_SIZE);
 738
 739         /*
 740          * Allocate receive data buffers.  We allocate a block of buffers and
 741          * a corresponding descriptor block at once.  See sxghw.h:SXG_RCV_BLOCK
 742          */
 743         for (i = 0; i < SXG_INITIAL_RCV_DATA_BUFFERS;
 744                                 i += SXG_RCV_DESCRIPTORS_PER_BLOCK) {
 745                         status = sxg_allocate_buffer_memory(adapter,
 746                                 SXG_RCV_BLOCK_SIZE(SXG_RCV_DATA_HDR_SIZE),
 747                                            SXG_BUFFER_TYPE_RCV);
 748                         if (status != STATUS_SUCCESS)
 749                                 return status;
 750         }
 751         /*
 752          * NBL resource allocation can fail in the 'AllocateComplete' routine,
 753          * which doesn't return status.  Make sure we got the number of buffers
 754          * we requested
 755          */
 756         if (adapter->FreeRcvBufferCount < SXG_INITIAL_RCV_DATA_BUFFERS) {
 757                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF6",
 758                           adapter, adapter->FreeRcvBufferCount, SXG_MAX_ENTRIES,
 759                           0);
 760                 return (STATUS_RESOURCES);
 761         }
 762
 763         DBG_ERROR("%s Allocate EventRings size[%x]\n", __func__,
 764                   (unsigned int)(sizeof(struct sxg_event_ring) * RssIds));
 765
 766         /* Allocate event queues. */
 767         adapter->EventRings = pci_alloc_consistent(adapter->pcidev,
 768                                            sizeof(struct sxg_event_ring) *
 769                                            RssIds,
 770                                            &adapter->PEventRings);
 771
 772         if (!adapter->EventRings) {
 773                 /* Caller will call SxgFreeAdapter to clean up above
 774                  * allocations */
 775                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF8",
 776                           adapter, SXG_MAX_ENTRIES, 0, 0);
 777                 status = STATUS_RESOURCES;
 778                 goto per_tcb_allocation_failed;
 779         }
 780         memset(adapter->EventRings, 0, sizeof(struct sxg_event_ring) * RssIds);
 781
 782         DBG_ERROR("%s Allocate ISR size[%x]\n", __func__, IsrCount);
 783         /* Allocate ISR */
 784         adapter->Isr = pci_alloc_consistent(adapter->pcidev,
 785                                             IsrCount, &adapter->PIsr);
 786         if (!adapter->Isr) {
 787                 /* Caller will call SxgFreeAdapter to clean up above
 788                  * allocations */
 789                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF9",
 790                           adapter, SXG_MAX_ENTRIES, 0, 0);
 791                 status = STATUS_RESOURCES;
 792                 goto per_tcb_allocation_failed;
 793         }
 794         memset(adapter->Isr, 0, sizeof(u32) * IsrCount);
 795
 796         DBG_ERROR("%s Allocate shared XMT ring zero index location size[%x]\n",
 797                   __func__, (unsigned int)sizeof(u32));
 798
 799         /* Allocate shared XMT ring zero index location */
 800         adapter->XmtRingZeroIndex = pci_alloc_consistent(adapter->pcidev,
 801                                                          sizeof(u32),
 802                                                          &adapter->
 803                                                          PXmtRingZeroIndex);
 804         if (!adapter->XmtRingZeroIndex) {
 805                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF10",
 806                           adapter, SXG_MAX_ENTRIES, 0, 0);
 807                 status = STATUS_RESOURCES;
 808                 goto per_tcb_allocation_failed;
 809         }
 810         memset(adapter->XmtRingZeroIndex, 0, sizeof(u32));
 811
 812         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlcResS",
 813                   adapter, SXG_MAX_ENTRIES, 0, 0);
 814
 815         return status;
 816 }
 817
 818 /*
 819  * sxg_config_pci -
 820  *
 821  * Set up PCI Configuration space
 822  *
 823  * Arguments -
 824  *              pcidev                  - A pointer to our adapter structure
 825  */
 826 static void sxg_config_pci(struct pci_dev *pcidev)
 827 {
 828         u16 pci_command;
 829         u16 new_command;
 830
 831         pci_read_config_word(pcidev, PCI_COMMAND, &pci_command);
 832         DBG_ERROR("sxg: %s  PCI command[%4.4x]\n", __func__, pci_command);
 833         /* Set the command register */
 834         new_command = pci_command | (
 835                                      /* Memory Space Enable */
 836                                      PCI_COMMAND_MEMORY |
 837                                      /* Bus master enable */
 838                                      PCI_COMMAND_MASTER |
 839                                      /* Memory write and invalidate */
 840                                      PCI_COMMAND_INVALIDATE |
 841                                      /* Parity error response */
 842                                      PCI_COMMAND_PARITY |
 843                                      /* System ERR */
 844                                      PCI_COMMAND_SERR |
 845                                      /* Fast back-to-back */
 846                                      PCI_COMMAND_FAST_BACK);
 847         if (pci_command != new_command) {
 848                 DBG_ERROR("%s -- Updating PCI COMMAND register %4.4x->%4.4x.\n",
 849                           __func__, pci_command, new_command);
 850                 pci_write_config_word(pcidev, PCI_COMMAND, new_command);
 851         }
 852 }
 853
 854 /*
 855  * sxg_read_config
 856  *      @adapter : Pointer to the adapter structure for the card
 857  * This function will read the configuration data from EEPROM/FLASH
 858  */
 859 static inline int sxg_read_config(struct adapter_t *adapter)
 860 {
 861         /* struct sxg_config    data; */
 862         struct sw_cfg_data      *data;
 863         dma_addr_t              p_addr;
 864         unsigned long           status;
 865         unsigned long           i;
 866
 867         data = pci_alloc_consistent(adapter->pcidev,
 868                                         sizeof(struct sw_cfg_data), &p_addr);
 869         if(!data) {
 870                 /*
 871                  * We cant get even this much memory. Raise a hell
 872                  * Get out of here
 873                  */
 874                 printk(KERN_ERR"%s : Could not allocate memory for reading \
 875                                  EEPROM\n", __FUNCTION__);
 876                 return -ENOMEM;
 877         }
 878
 879         WRITE_REG(adapter->UcodeRegs[0].ConfigStat, SXG_CFG_TIMEOUT, TRUE);
 880
 881         WRITE_REG64(adapter, adapter->UcodeRegs[0].Config, p_addr, 0);
 882         for(i=0; i<1000; i++) {
 883                 READ_REG(adapter->UcodeRegs[0].ConfigStat, status);
 884                 if (status != SXG_CFG_TIMEOUT)
 885                         break;
 886                 mdelay(1);                      /* Do we really need this */
 887         }
 888
 889         switch(status) {
 890         /* Config read from EEPROM succeeded */
 891         case SXG_CFG_LOAD_EEPROM:
 892         /* Config read from Flash succeeded */
 893         case SXG_CFG_LOAD_FLASH:
 894         /* Copy the MAC address to adapter structure */
 895                 /* TODO: We are not doing the remaining part : FRU,
 896                  * etc
 897                  */
 898                 memcpy(adapter->macaddr, data->MacAddr[0].MacAddr,
 899                               sizeof(struct sxg_config_mac));
 900                 break;
 901         case SXG_CFG_TIMEOUT:
 902         case SXG_CFG_LOAD_INVALID:
 903         case SXG_CFG_LOAD_ERROR:
 904         default:        /* Fix default handler later */
 905                 printk(KERN_WARNING"%s  : We could not read the config \
 906                         word. Status = %ld\n", __FUNCTION__, status);
 907                 break;
 908         }
 909         pci_free_consistent(adapter->pcidev, sizeof(struct sw_cfg_data), data,
 910                                 p_addr);
 911         if (adapter->netdev) {
 912                 memcpy(adapter->netdev->dev_addr, adapter->currmacaddr, 6);
 913                 memcpy(adapter->netdev->perm_addr, adapter->currmacaddr, 6);
 914         }
 915         sxg_dbg_macaddrs(adapter);
 916
 917         return status;
 918 }
 919
 920 static int sxg_entry_probe(struct pci_dev *pcidev,
 921                            const struct pci_device_id *pci_tbl_entry)
 922 {
 923         static int did_version = 0;
 924         int err;
 925         struct net_device *netdev;
 926         struct adapter_t *adapter;
 927         void __iomem *memmapped_ioaddr;
 928         u32 status = 0;
 929         ulong mmio_start = 0;
 930         ulong mmio_len = 0;
 931         unsigned char revision_id;
 932
 933         DBG_ERROR("sxg: %s 2.6 VERSION ENTER jiffies[%lx] cpu %d\n",
 934                   __func__, jiffies, smp_processor_id());
 935
 936         /* Initialize trace buffer */
 937 #ifdef ATKDBG
 938         SxgTraceBuffer = &LSxgTraceBuffer;
 939         SXG_TRACE_INIT(SxgTraceBuffer, TRACE_NOISY);
 940 #endif
 941
 942         sxg_global.dynamic_intagg = dynamic_intagg;
 943
 944         err = pci_enable_device(pcidev);
 945
 946         DBG_ERROR("Call pci_enable_device(%p)  status[%x]\n", pcidev, err);
 947         if (err) {
 948                 return err;
 949         }
 950
 951         if (sxg_debug > 0 && did_version++ == 0) {
 952                 printk(KERN_INFO "%s\n", sxg_banner);
 953                 printk(KERN_INFO "%s\n", SXG_DRV_VERSION);
 954         }
 955
 956         pci_read_config_byte(pcidev, PCI_REVISION_ID, &revision_id);
 957
 958         if (!(err = pci_set_dma_mask(pcidev, DMA_64BIT_MASK))) {
 959                 DBG_ERROR("pci_set_dma_mask(DMA_64BIT_MASK) successful\n");
 960         } else {
 961                 if ((err = pci_set_dma_mask(pcidev, DMA_32BIT_MASK))) {
 962                         DBG_ERROR
 963                             ("No usable DMA configuration, aborting  err[%x]\n",
 964                              err);
 965                         return err;
 966                 }
 967                 DBG_ERROR("pci_set_dma_mask(DMA_32BIT_MASK) successful\n");
 968         }
 969
 970         DBG_ERROR("Call pci_request_regions\n");
 971
 972         err = pci_request_regions(pcidev, sxg_driver_name);
 973         if (err) {
 974                 DBG_ERROR("pci_request_regions FAILED err[%x]\n", err);
 975                 return err;
 976         }
 977
 978         DBG_ERROR("call pci_set_master\n");
 979         pci_set_master(pcidev);
 980
 981         DBG_ERROR("call alloc_etherdev\n");
 982         netdev = alloc_etherdev(sizeof(struct adapter_t));
 983         if (!netdev) {
 984                 err = -ENOMEM;
 985                 goto err_out_exit_sxg_probe;
 986         }
 987         DBG_ERROR("alloc_etherdev for slic netdev[%p]\n", netdev);
 988
 989         SET_NETDEV_DEV(netdev, &pcidev->dev);
 990
 991         pci_set_drvdata(pcidev, netdev);
 992         adapter = netdev_priv(netdev);
 993         if (revision_id == 1) {
 994                 adapter->asictype = SAHARA_REV_A;
 995         } else if (revision_id == 2) {
 996                 adapter->asictype = SAHARA_REV_B;
 997         } else {
 998                 ASSERT(0);
 999                 DBG_ERROR("%s Unexpected revision ID %x\n", __FUNCTION__, revision_id);
1000                 goto err_out_exit_sxg_probe;
1001         }
1002         adapter->netdev = netdev;
1003         adapter->pcidev = pcidev;
1004
1005         mmio_start = pci_resource_start(pcidev, 0);
1006         mmio_len = pci_resource_len(pcidev, 0);
1007
1008         DBG_ERROR("sxg: call ioremap(mmio_start[%lx], mmio_len[%lx])\n",
1009                   mmio_start, mmio_len);
1010
1011         memmapped_ioaddr = ioremap(mmio_start, mmio_len);
1012         DBG_ERROR("sxg: %s MEMMAPPED_IOADDR [%p]\n", __func__,
1013                   memmapped_ioaddr);
1014         if (!memmapped_ioaddr) {
1015                 DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n",
1016                           __func__, mmio_len, mmio_start);
1017                 goto err_out_free_mmio_region_0;
1018         }
1019
1020         DBG_ERROR("sxg: %s found Alacritech SXG PCI, MMIO at %p, start[%lx] \
1021               len[%lx], IRQ %d.\n", __func__, memmapped_ioaddr, mmio_start,
1022                                               mmio_len, pcidev->irq);
1023
1024         adapter->HwRegs = (void *)memmapped_ioaddr;
1025         adapter->base_addr = memmapped_ioaddr;
1026
1027         mmio_start = pci_resource_start(pcidev, 2);
1028         mmio_len = pci_resource_len(pcidev, 2);
1029
1030         DBG_ERROR("sxg: call ioremap(mmio_start[%lx], mmio_len[%lx])\n",
1031                   mmio_start, mmio_len);
1032
1033         memmapped_ioaddr = ioremap(mmio_start, mmio_len);
1034         DBG_ERROR("sxg: %s MEMMAPPED_IOADDR [%p]\n", __func__,
1035                   memmapped_ioaddr);
1036         if (!memmapped_ioaddr) {
1037                 DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n",
1038                           __func__, mmio_len, mmio_start);
1039                 goto err_out_free_mmio_region_2;
1040         }
1041
1042         DBG_ERROR("sxg: %s found Alacritech SXG PCI, MMIO at %p, "
1043                   "start[%lx] len[%lx], IRQ %d.\n", __func__,
1044                   memmapped_ioaddr, mmio_start, mmio_len, pcidev->irq);
1045
1046         adapter->UcodeRegs = (void *)memmapped_ioaddr;
1047
1048         adapter->State = SXG_STATE_INITIALIZING;
1049         /*
1050          * Maintain a list of all adapters anchored by
1051          * the global SxgDriver structure.
1052          */
1053         adapter->Next = SxgDriver.Adapters;
1054         SxgDriver.Adapters = adapter;
1055         adapter->AdapterID = ++SxgDriver.AdapterID;
1056
1057         /* Initialize CRC table used to determine multicast hash */
1058         sxg_mcast_init_crc32();
1059
1060         adapter->JumboEnabled = FALSE;
1061         adapter->RssEnabled = FALSE;
1062         if (adapter->JumboEnabled) {
1063                 adapter->FrameSize = JUMBOMAXFRAME;
1064                 adapter->ReceiveBufferSize = SXG_RCV_JUMBO_BUFFER_SIZE;
1065         } else {
1066                 adapter->FrameSize = ETHERMAXFRAME;
1067                 adapter->ReceiveBufferSize = SXG_RCV_DATA_BUFFER_SIZE;
1068         }
1069
1070         /*
1071          *    status = SXG_READ_EEPROM(adapter);
1072          *    if (!status) {
1073          *        goto sxg_init_bad;
1074          *    }
1075          */
1076
1077         DBG_ERROR("sxg: %s ENTER sxg_config_pci\n", __func__);
1078         sxg_config_pci(pcidev);
1079         DBG_ERROR("sxg: %s EXIT sxg_config_pci\n", __func__);
1080
1081         DBG_ERROR("sxg: %s ENTER sxg_init_driver\n", __func__);
1082         sxg_init_driver();
1083         DBG_ERROR("sxg: %s EXIT sxg_init_driver\n", __func__);
1084
1085         adapter->vendid = pci_tbl_entry->vendor;
1086         adapter->devid = pci_tbl_entry->device;
1087         adapter->subsysid = pci_tbl_entry->subdevice;
1088         adapter->slotnumber = ((pcidev->devfn >> 3) & 0x1F);
1089         adapter->functionnumber = (pcidev->devfn & 0x7);
1090         adapter->memorylength = pci_resource_len(pcidev, 0);
1091         adapter->irq = pcidev->irq;
1092         adapter->next_netdevice = head_netdevice;
1093         head_netdevice = netdev;
1094         adapter->port = 0;      /*adapter->functionnumber; */
1095
1096         /* Allocate memory and other resources */
1097         DBG_ERROR("sxg: %s ENTER sxg_allocate_resources\n", __func__);
1098         status = sxg_allocate_resources(adapter);
1099         DBG_ERROR("sxg: %s EXIT sxg_allocate_resources status %x\n",
1100                   __func__, status);
1101         if (status != STATUS_SUCCESS) {
1102                 goto err_out_unmap;
1103         }
1104
1105         DBG_ERROR("sxg: %s ENTER sxg_download_microcode\n", __func__);
1106         if (sxg_download_microcode(adapter, SXG_UCODE_SYSTEM)) {
1107                 DBG_ERROR("sxg: %s ENTER sxg_adapter_set_hwaddr\n",
1108                           __func__);
1109                 sxg_read_config(adapter);
1110                 status = sxg_adapter_set_hwaddr(adapter);
1111         } else {
1112                 adapter->state = ADAPT_FAIL;
1113                 adapter->linkstate = LINK_DOWN;
1114                 DBG_ERROR("sxg_download_microcode FAILED status[%x]\n", status);
1115         }
1116
1117         netdev->base_addr = (unsigned long)adapter->base_addr;
1118         netdev->irq = adapter->irq;
1119         netdev->open = sxg_entry_open;
1120         netdev->stop = sxg_entry_halt;
1121         netdev->hard_start_xmit = sxg_send_packets;
1122         netdev->do_ioctl = sxg_ioctl;
1123         netdev->change_mtu = sxg_change_mtu;
1124 #if XXXTODO
1125         netdev->set_mac_address = sxg_mac_set_address;
1126 #endif
1127         netdev->get_stats = sxg_get_stats;
1128         netdev->set_multicast_list = sxg_mcast_set_list;
1129         SET_ETHTOOL_OPS(netdev, &sxg_nic_ethtool_ops);
1130         netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1131         err = sxg_set_interrupt_capability(adapter);
1132         if (err != STATUS_SUCCESS)
1133                 DBG_ERROR("Cannot enable MSI-X capability\n");
1134
1135         strcpy(netdev->name, "eth%d");
1136         /*  strcpy(netdev->name, pci_name(pcidev)); */
1137         if ((err = register_netdev(netdev))) {
1138                 DBG_ERROR("Cannot register net device, aborting. %s\n",
1139                           netdev->name);
1140                 goto err_out_unmap;
1141         }
1142
1143         netif_napi_add(netdev, &adapter->napi,
1144                 sxg_poll, SXG_NETDEV_WEIGHT);
1145         DBG_ERROR
1146             ("sxg: %s addr 0x%lx, irq %d, MAC addr \
1147                 %02X:%02X:%02X:%02X:%02X:%02X\n",
1148              netdev->name, netdev->base_addr, pcidev->irq, netdev->dev_addr[0],
1149              netdev->dev_addr[1], netdev->dev_addr[2], netdev->dev_addr[3],
1150              netdev->dev_addr[4], netdev->dev_addr[5]);
1151
1152         /* sxg_init_bad: */
1153         ASSERT(status == FALSE);
1154         /* sxg_free_adapter(adapter); */
1155
1156         DBG_ERROR("sxg: %s EXIT status[%x] jiffies[%lx] cpu %d\n", __func__,
1157                   status, jiffies, smp_processor_id());
1158         return status;
1159
1160       err_out_unmap:
1161         sxg_free_resources(adapter);
1162
1163       err_out_free_mmio_region_2:
1164
1165         mmio_start = pci_resource_start(pcidev, 2);
1166         mmio_len = pci_resource_len(pcidev, 2);
1167         release_mem_region(mmio_start, mmio_len);
1168
1169       err_out_free_mmio_region_0:
1170
1171         mmio_start = pci_resource_start(pcidev, 0);
1172         mmio_len = pci_resource_len(pcidev, 0);
1173
1174         release_mem_region(mmio_start, mmio_len);
1175
1176       err_out_exit_sxg_probe:
1177
1178         DBG_ERROR("%s EXIT jiffies[%lx] cpu %d\n", __func__, jiffies,
1179                   smp_processor_id());
1180
1181         pci_disable_device(pcidev);
1182         DBG_ERROR("sxg: %s deallocate device\n", __FUNCTION__);
1183         kfree(netdev);
1184         printk("Exit %s, Sxg driver loading failed..\n", __FUNCTION__);
1185
1186         return -ENODEV;
1187 }
1188
1189 /*
1190  * LINE BASE Interrupt routines..
1191  *
1192  * sxg_disable_interrupt
1193  *
1194  * DisableInterrupt Handler
1195  *
1196  * Arguments:
1197  *
1198  *   adapter:   Our adapter structure
1199  *
1200  * Return Value:
1201  *      None.
1202  */
1203 static void sxg_disable_interrupt(struct adapter_t *adapter)
1204 {
1205         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DisIntr",
1206                   adapter, adapter->InterruptsEnabled, 0, 0);
1207         /* For now, RSS is disabled with line based interrupts */
1208         ASSERT(adapter->RssEnabled == FALSE);
1209         /* Turn off interrupts by writing to the icr register. */
1210         WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_DISABLE), TRUE);
1211
1212         adapter->InterruptsEnabled = 0;
1213
1214         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDisIntr",
1215                   adapter, adapter->InterruptsEnabled, 0, 0);
1216 }
1217
1218 /*
1219  * sxg_enable_interrupt
1220  *
1221  * EnableInterrupt Handler
1222  *
1223  * Arguments:
1224  *
1225  *   adapter:   Our adapter structure
1226  *
1227  * Return Value:
1228  *      None.
1229  */
1230 static void sxg_enable_interrupt(struct adapter_t *adapter)
1231 {
1232         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "EnIntr",
1233                   adapter, adapter->InterruptsEnabled, 0, 0);
1234         /* For now, RSS is disabled with line based interrupts */
1235         ASSERT(adapter->RssEnabled == FALSE);
1236         /* Turn on interrupts by writing to the icr register. */
1237         WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_ENABLE), TRUE);
1238
1239         adapter->InterruptsEnabled = 1;
1240
1241         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XEnIntr",
1242                   adapter, 0, 0, 0);
1243 }
1244
1245 /*
1246  * sxg_isr - Process an line-based interrupt
1247  *
1248  * Arguments:
1249  *              Context         - Our adapter structure
1250  *              QueueDefault    - Output parameter to queue to default CPU
1251  *              TargetCpus      - Output bitmap to schedule DPC's
1252  *
1253  * Return Value: TRUE if our interrupt
1254  */
1255 static irqreturn_t sxg_isr(int irq, void *dev_id)
1256 {
1257         struct net_device *dev = (struct net_device *) dev_id;
1258         struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
1259
1260         if(adapter->state != ADAPT_UP)
1261                 return IRQ_NONE;
1262         adapter->Stats.NumInts++;
1263         if (adapter->Isr[0] == 0) {
1264                 /*
1265                  * The SLIC driver used to experience a number of spurious
1266                  * interrupts due to the delay associated with the masking of
1267                  * the interrupt (we'd bounce back in here).  If we see that
1268                  * again with Sahara,add a READ_REG of the Icr register after
1269                  * the WRITE_REG below.
1270                  */
1271                 adapter->Stats.FalseInts++;
1272                 return IRQ_NONE;
1273         }
1274         /*
1275          * Move the Isr contents and clear the value in
1276          * shared memory, and mask interrupts
1277          */
1278         /* ASSERT(adapter->IsrDpcsPending == 0); */
1279 #if XXXTODO                     /* RSS Stuff */
1280         /*
1281          * If RSS is enabled and the ISR specifies SXG_ISR_EVENT, then
1282          * schedule DPC's based on event queues.
1283          */
1284         if (adapter->RssEnabled && (adapter->IsrCopy[0] & SXG_ISR_EVENT)) {
1285                 for (i = 0;
1286                      i < adapter->RssSystemInfo->ProcessorInfo.RssCpuCount;
1287                      i++) {
1288                         struct sxg_event_ring *EventRing =
1289                                                 &adapter->EventRings[i];
1290                         struct sxg_event *Event =
1291                             &EventRing->Ring[adapter->NextEvent[i]];
1292                         unsigned char Cpu =
1293                             adapter->RssSystemInfo->RssIdToCpu[i];
1294                         if (Event->Status & EVENT_STATUS_VALID) {
1295                                 adapter->IsrDpcsPending++;
1296                                 CpuMask |= (1 << Cpu);
1297                         }
1298                 }
1299         }
1300         /*
1301          * Now, either schedule the CPUs specified by the CpuMask,
1302          * or queue default
1303          */
1304         if (CpuMask) {
1305                 *QueueDefault = FALSE;
1306         } else {
1307                 adapter->IsrDpcsPending = 1;
1308                 *QueueDefault = TRUE;
1309         }
1310         *TargetCpus = CpuMask;
1311 #endif
1312         sxg_interrupt(adapter);
1313
1314         return IRQ_HANDLED;
1315 }
1316
1317 static void sxg_interrupt(struct adapter_t *adapter)
1318 {
1319         WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_MASK), TRUE);
1320
1321         if (napi_schedule_prep(&adapter->napi)) {
1322                 __napi_schedule(&adapter->napi);
1323         }
1324 }
1325
1326 static void sxg_handle_interrupt(struct adapter_t *adapter, int *work_done,
1327                                          int budget)
1328 {
1329         /* unsigned char           RssId   = 0; */
1330         u32 NewIsr;
1331         int sxg_napi_continue = 1;
1332         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "HndlIntr",
1333                   adapter, adapter->IsrCopy[0], 0, 0);
1334         /* For now, RSS is disabled with line based interrupts */
1335         ASSERT(adapter->RssEnabled == FALSE);
1336
1337         adapter->IsrCopy[0] = adapter->Isr[0];
1338         adapter->Isr[0] = 0;
1339
1340         /* Always process the event queue. */
1341         while (sxg_napi_continue)
1342         {
1343                 sxg_process_event_queue(adapter,
1344                                 (adapter->RssEnabled ? /*RssId */ 0 : 0),
1345                                  &sxg_napi_continue, work_done, budget);
1346         }
1347
1348 #if XXXTODO                     /* RSS stuff */
1349         if (--adapter->IsrDpcsPending) {
1350                 /* We're done. */
1351                 ASSERT(adapter->RssEnabled);
1352                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DPCsPend",
1353                           adapter, 0, 0, 0);
1354                 return;
1355         }
1356 #endif
1357         /* Last (or only) DPC processes the ISR and clears the interrupt. */
1358         NewIsr = sxg_process_isr(adapter, 0);
1359         /* Reenable interrupts */
1360         adapter->IsrCopy[0] = 0;
1361         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ClearIsr",
1362                   adapter, NewIsr, 0, 0);
1363
1364         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XHndlInt",
1365                   adapter, 0, 0, 0);
1366 }
1367 static int sxg_poll(struct napi_struct *napi, int budget)
1368 {
1369         struct adapter_t *adapter = container_of(napi, struct adapter_t, napi);
1370         int work_done = 0;
1371
1372         sxg_handle_interrupt(adapter, &work_done, budget);
1373
1374         if (work_done < budget) {
1375                 napi_complete(napi);
1376                 WRITE_REG(adapter->UcodeRegs[0].Isr, 0, TRUE);
1377         }
1378         return work_done;
1379 }
1380
1381 /*
1382  * sxg_process_isr - Process an interrupt.  Called from the line-based and
1383  *                      message based interrupt DPC routines
1384  *
1385  * Arguments:
1386  *              adapter                 - Our adapter structure
1387  *              Queue                   - The ISR that needs processing
1388  *
1389  * Return Value:
1390  *      None
1391  */
1392 static int sxg_process_isr(struct adapter_t *adapter, u32 MessageId)
1393 {
1394         u32 Isr = adapter->IsrCopy[MessageId];
1395         u32 NewIsr = 0;
1396
1397         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ProcIsr",
1398                   adapter, Isr, 0, 0);
1399
1400         /* Error */
1401         if (Isr & SXG_ISR_ERR) {
1402                 if (Isr & SXG_ISR_PDQF) {
1403                         adapter->Stats.PdqFull++;
1404                         DBG_ERROR("%s: SXG_ISR_ERR  PDQF!!\n", __func__);
1405                 }
1406                 /* No host buffer */
1407                 if (Isr & SXG_ISR_RMISS) {
1408                         /*
1409                          * There is a bunch of code in the SLIC driver which
1410                          * attempts to process more receive events per DPC
1411                          * if we start to fall behind.  We'll probablyd
1412                          * need to do something similar here, but hold
1413                          * off for now.  I don't want to make the code more
1414                          * complicated than strictly needed.
1415                          */
1416                         adapter->stats.rx_missed_errors++;
1417                         if (adapter->stats.rx_missed_errors< 5) {
1418                                 DBG_ERROR("%s: SXG_ISR_ERR  RMISS!!\n",
1419                                           __func__);
1420                         }
1421                 }
1422                 /* Card crash */
1423                 if (Isr & SXG_ISR_DEAD) {
1424                         /*
1425                          * Set aside the crash info and set the adapter state
1426                          * to RESET
1427                          */
1428                         adapter->CrashCpu = (unsigned char)
1429                                 ((Isr & SXG_ISR_CPU) >> SXG_ISR_CPU_SHIFT);
1430                         adapter->CrashLocation = (ushort) (Isr & SXG_ISR_CRASH);
1431                         adapter->Dead = TRUE;
1432                         DBG_ERROR("%s: ISR_DEAD %x, CPU: %d\n", __func__,
1433                                   adapter->CrashLocation, adapter->CrashCpu);
1434                 }
1435                 /* Event ring full */
1436                 if (Isr & SXG_ISR_ERFULL) {
1437                         /*
1438                          * Same issue as RMISS, really.  This means the
1439                          * host is falling behind the card.  Need to increase
1440                          * event ring size, process more events per interrupt,
1441                          * and/or reduce/remove interrupt aggregation.
1442                          */
1443                         adapter->Stats.EventRingFull++;
1444                         DBG_ERROR("%s: SXG_ISR_ERR  EVENT RING FULL!!\n",
1445                                   __func__);
1446                 }
1447                 /* Transmit drop - no DRAM buffers or XMT error */
1448                 if (Isr & SXG_ISR_XDROP) {
1449                         DBG_ERROR("%s: SXG_ISR_ERR  XDROP!!\n", __func__);
1450                 }
1451         }
1452         /* Slowpath send completions */
1453         if (Isr & SXG_ISR_SPSEND) {
1454                 sxg_complete_slow_send(adapter);
1455         }
1456         /* Dump */
1457         if (Isr & SXG_ISR_UPC) {
1458                 /* Maybe change when debug is added.. */
1459 //              ASSERT(adapter->DumpCmdRunning);
1460                 adapter->DumpCmdRunning = FALSE;
1461         }
1462         /* Link event */
1463         if (Isr & SXG_ISR_LINK) {
1464                 sxg_link_event(adapter);
1465         }
1466         /* Debug - breakpoint hit */
1467         if (Isr & SXG_ISR_BREAK) {
1468                 /*
1469                  * At the moment AGDB isn't written to support interactive
1470                  * debug sessions.  When it is, this interrupt will be used to
1471                  * signal AGDB that it has hit a breakpoint.  For now, ASSERT.
1472                  */
1473                 ASSERT(0);
1474         }
1475         /* Heartbeat response */
1476         if (Isr & SXG_ISR_PING) {
1477                 adapter->PingOutstanding = FALSE;
1478         }
1479         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XProcIsr",
1480                   adapter, Isr, NewIsr, 0);
1481
1482         return (NewIsr);
1483 }
1484
1485 /*
1486  * sxg_rcv_checksum - Set the checksum for received packet
1487  *
1488  * Arguements:
1489  *              @adapter - Adapter structure on which packet is received
1490  *              @skb - Packet which is receieved
1491  *              @Event - Event read from hardware
1492  */
1493
1494 void sxg_rcv_checksum(struct adapter_t *adapter, struct sk_buff *skb,
1495                          struct sxg_event *Event)
1496 {
1497         skb->ip_summed = CHECKSUM_NONE;
1498         if (likely(adapter->flags & SXG_RCV_IP_CSUM_ENABLED)) {
1499                 if (likely(adapter->flags & SXG_RCV_TCP_CSUM_ENABLED)
1500                         && (Event->Status & EVENT_STATUS_TCPIP)) {
1501                         if(!(Event->Status & EVENT_STATUS_TCPBAD))
1502                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1503                 if(!(Event->Status & EVENT_STATUS_IPBAD))
1504                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1505                 } else if(Event->Status & EVENT_STATUS_IPONLY) {
1506                         if(!(Event->Status & EVENT_STATUS_IPBAD))
1507                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1508                 }
1509         }
1510 }
1511
1512 /*
1513  * sxg_process_event_queue - Process our event queue
1514  *
1515  * Arguments:
1516  *              - adapter       - Adapter structure
1517  *              - RssId         - The event queue requiring processing
1518  *
1519  * Return Value:
1520  *      None.
1521  */
1522 static u32 sxg_process_event_queue(struct adapter_t *adapter, u32 RssId,
1523                          int *sxg_napi_continue, int *work_done, int budget)
1524 {
1525         struct sxg_event_ring *EventRing = &adapter->EventRings[RssId];
1526         struct sxg_event *Event = &EventRing->Ring[adapter->NextEvent[RssId]];
1527         u32 EventsProcessed = 0, Batches = 0;
1528         struct sk_buff *skb;
1529 #ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
1530         struct sk_buff *prev_skb = NULL;
1531         struct sk_buff *IndicationList[SXG_RCV_ARRAYSIZE];
1532         u32 Index;
1533         struct sxg_rcv_data_buffer_hdr *RcvDataBufferHdr;
1534 #endif
1535         u32 ReturnStatus = 0;
1536         int sxg_rcv_data_buffers = SXG_RCV_DATA_BUFFERS;
1537
1538         ASSERT((adapter->State == SXG_STATE_RUNNING) ||
1539                (adapter->State == SXG_STATE_PAUSING) ||
1540                (adapter->State == SXG_STATE_PAUSED) ||
1541                (adapter->State == SXG_STATE_HALTING));
1542         /*
1543          * We may still have unprocessed events on the queue if
1544          * the card crashed.  Don't process them.
1545          */
1546         if (adapter->Dead) {
1547                 return (0);
1548         }
1549         /*
1550          *  In theory there should only be a single processor that
1551          * accesses this queue, and only at interrupt-DPC time.  So/
1552          * we shouldn't need a lock for any of this.
1553          */
1554         while (Event->Status & EVENT_STATUS_VALID) {
1555                 (*sxg_napi_continue) = 1;
1556                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "Event",
1557                           Event, Event->Code, Event->Status,
1558                           adapter->NextEvent);
1559                 switch (Event->Code) {
1560                 case EVENT_CODE_BUFFERS:
1561                         /* struct sxg_ring_info Head & Tail == unsigned char */
1562                         ASSERT(!(Event->CommandIndex & 0xFF00));
1563                         sxg_complete_descriptor_blocks(adapter,
1564                                                        Event->CommandIndex);
1565                         break;
1566                 case EVENT_CODE_SLOWRCV:
1567                         (*work_done)++;
1568                         --adapter->RcvBuffersOnCard;
1569                         if ((skb = sxg_slow_receive(adapter, Event))) {
1570                                 u32 rx_bytes;
1571 #ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
1572                                 /* Add it to our indication list */
1573                                 SXG_ADD_RCV_PACKET(adapter, skb, prev_skb,
1574                                                    IndicationList, num_skbs);
1575                                 /*
1576                                  * Linux, we just pass up each skb to the
1577                                  * protocol above at this point, there is no
1578                                  * capability of an indication list.
1579                                  */
1580 #else
1581                                 /* CHECK skb_pull(skb, INIC_RCVBUF_HEADSIZE); */
1582                                 /* (rcvbuf->length & IRHDDR_FLEN_MSK); */
1583                                 rx_bytes = Event->Length;
1584                                 adapter->stats.rx_packets++;
1585                                 adapter->stats.rx_bytes += rx_bytes;
1586                                 sxg_rcv_checksum(adapter, skb, Event);
1587                                 skb->dev = adapter->netdev;
1588                                 netif_receive_skb(skb);
1589 #endif
1590                         }
1591                         break;
1592                 default:
1593                         DBG_ERROR("%s: ERROR  Invalid EventCode %d\n",
1594                                   __func__, Event->Code);
1595                 /* ASSERT(0); */
1596                 }
1597                 /*
1598                  * See if we need to restock card receive buffers.
1599                  * There are two things to note here:
1600                  *  First - This test is not SMP safe.  The
1601                  *    adapter->BuffersOnCard field is protected via atomic
1602                  *    interlocked calls, but we do not protect it with respect
1603                  *    to these tests.  The only way to do that is with a lock,
1604                  *    and I don't want to grab a lock every time we adjust the
1605                  *    BuffersOnCard count.  Instead, we allow the buffer
1606                  *    replenishment to be off once in a while. The worst that
1607                  *    can happen is the card is given on more-or-less descriptor
1608                  *    block than the arbitrary value we've chosen. No big deal
1609                  *    In short DO NOT ADD A LOCK HERE, OR WHERE RcvBuffersOnCard
1610                  *    is adjusted.
1611                  *  Second - We expect this test to rarely
1612                  *    evaluate to true.  We attempt to refill descriptor blocks
1613                  *    as they are returned to us (sxg_complete_descriptor_blocks)
1614                  *    so The only time this should evaluate to true is when
1615                  *    sxg_complete_descriptor_blocks failed to allocate
1616                  *    receive buffers.
1617                  */
1618                 if (adapter->JumboEnabled)
1619                         sxg_rcv_data_buffers = SXG_JUMBO_RCV_DATA_BUFFERS;
1620
1621                 if (adapter->RcvBuffersOnCard < sxg_rcv_data_buffers) {
1622                         sxg_stock_rcv_buffers(adapter);
1623                 }
1624                 /*
1625                  * It's more efficient to just set this to zero.
1626                  * But clearing the top bit saves potential debug info...
1627                  */
1628                 Event->Status &= ~EVENT_STATUS_VALID;
1629                 /* Advance to the next event */
1630                 SXG_ADVANCE_INDEX(adapter->NextEvent[RssId], EVENT_RING_SIZE);
1631                 Event = &EventRing->Ring[adapter->NextEvent[RssId]];
1632                 EventsProcessed++;
1633                 if (EventsProcessed == EVENT_RING_BATCH) {
1634                         /* Release a batch of events back to the card */
1635                         WRITE_REG(adapter->UcodeRegs[RssId].EventRelease,
1636                                   EVENT_RING_BATCH, FALSE);
1637                         EventsProcessed = 0;
1638                         /*
1639                          * If we've processed our batch limit, break out of the
1640                          * loop and return SXG_ISR_EVENT to arrange for us to
1641                          * be called again
1642                          */
1643                         if (Batches++ == EVENT_BATCH_LIMIT) {
1644                                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer,
1645                                           TRACE_NOISY, "EvtLimit", Batches,
1646                                           adapter->NextEvent, 0, 0);
1647                                 ReturnStatus = SXG_ISR_EVENT;
1648                                 break;
1649                         }
1650                 }
1651                 if (*work_done >= budget) {
1652                         WRITE_REG(adapter->UcodeRegs[RssId].EventRelease,
1653                                   EventsProcessed, FALSE);
1654                         EventsProcessed = 0;
1655                         (*sxg_napi_continue) = 0;
1656                         break;
1657                 }
1658         }
1659         if (!(Event->Status & EVENT_STATUS_VALID))
1660                 (*sxg_napi_continue) = 0;
1661
1662 #ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
1663         /* Indicate any received dumb-nic frames */
1664         SXG_INDICATE_PACKETS(adapter, IndicationList, num_skbs);
1665 #endif
1666         /* Release events back to the card. */
1667         if (EventsProcessed) {
1668                 WRITE_REG(adapter->UcodeRegs[RssId].EventRelease,
1669                           EventsProcessed, FALSE);
1670         }
1671         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XPrcEvnt",
1672                   Batches, EventsProcessed, adapter->NextEvent, num_skbs);
1673
1674         return (ReturnStatus);
1675 }
1676
1677 /*
1678  * sxg_complete_slow_send - Complete slowpath or dumb-nic sends
1679  *
1680  * Arguments -
1681  *      adapter         - A pointer to our adapter structure
1682  * Return
1683  *      None
1684  */
1685 static void sxg_complete_slow_send(struct adapter_t *adapter)
1686 {
1687         struct sxg_xmt_ring *XmtRing = &adapter->XmtRings[0];
1688         struct sxg_ring_info *XmtRingInfo = &adapter->XmtRingZeroInfo;
1689         u32 *ContextType;
1690         struct sxg_cmd *XmtCmd;
1691         unsigned long flags = 0;
1692         unsigned long sgl_flags = 0;
1693         unsigned int processed_count = 0;
1694
1695         /*
1696          * NOTE - This lock is dropped and regrabbed in this loop.
1697          * This means two different processors can both be running/
1698          * through this loop. Be *very* careful.
1699          */
1700         spin_lock_irqsave(&adapter->XmtZeroLock, flags);
1701
1702         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnds",
1703                   adapter, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
1704
1705         while ((XmtRingInfo->Tail != *adapter->XmtRingZeroIndex)
1706                 && processed_count++ < SXG_COMPLETE_SLOW_SEND_LIMIT)  {
1707                 /*
1708                  * Locate the current Cmd (ring descriptor entry), and
1709                  * associated SGL, and advance the tail
1710                  */
1711                 SXG_RETURN_CMD(XmtRing, XmtRingInfo, XmtCmd, ContextType);
1712                 ASSERT(ContextType);
1713                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnd",
1714                           XmtRingInfo->Head, XmtRingInfo->Tail, XmtCmd, 0);
1715                 /* Clear the SGL field. */
1716                 XmtCmd->Sgl = 0;
1717
1718                 switch (*ContextType) {
1719                 case SXG_SGL_DUMB:
1720                         {
1721                                 struct sk_buff *skb;
1722                                 struct sxg_scatter_gather *SxgSgl =
1723                                         (struct sxg_scatter_gather *)ContextType;
1724                                 dma64_addr_t FirstSgeAddress;
1725                                 u32 FirstSgeLength;
1726
1727                                 /* Dumb-nic send.  Command context is the dumb-nic SGL */
1728                                 skb = (struct sk_buff *)ContextType;
1729                                 skb = SxgSgl->DumbPacket;
1730                                 FirstSgeAddress = XmtCmd->Buffer.FirstSgeAddress;
1731                                 FirstSgeLength = XmtCmd->Buffer.FirstSgeLength;
1732                                 /* Complete the send */
1733                                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer,
1734                                           TRACE_IMPORTANT, "DmSndCmp", skb, 0,
1735                                           0, 0);
1736                                 ASSERT(adapter->Stats.XmtQLen);
1737                                 /*
1738                                  * Now drop the lock and complete the send
1739                                  * back to Microsoft.  We need to drop the lock
1740                                  * because Microsoft can come back with a
1741                                  * chimney send, which results in a double trip
1742                                  * in SxgTcpOuput
1743                                  */
1744                                 spin_unlock_irqrestore(
1745                                         &adapter->XmtZeroLock, flags);
1746
1747                                 SxgSgl->DumbPacket = NULL;
1748                                 SXG_COMPLETE_DUMB_SEND(adapter, skb,
1749                                                         FirstSgeAddress,
1750                                                         FirstSgeLength);
1751                                 SXG_FREE_SGL_BUFFER(adapter, SxgSgl, NULL);
1752                                 /* and reacquire.. */
1753                                 spin_lock_irqsave(&adapter->XmtZeroLock, flags);
1754                         }
1755                         break;
1756                 default:
1757                         ASSERT(0);
1758                 }
1759         }
1760         spin_unlock_irqrestore(&adapter->XmtZeroLock, flags);
1761         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnd",
1762                   adapter, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
1763 }
1764
1765 /*
1766  * sxg_slow_receive
1767  *
1768  * Arguments -
1769  *      adapter         - A pointer to our adapter structure
1770  *      Event           - Receive event
1771  *
1772  * Return - skb
1773  */
1774 static struct sk_buff *sxg_slow_receive(struct adapter_t *adapter,
1775                                                 struct sxg_event *Event)
1776 {
1777         u32 BufferSize = adapter->ReceiveBufferSize;
1778         struct sxg_rcv_data_buffer_hdr *RcvDataBufferHdr;
1779         struct sk_buff *Packet;
1780         static int read_counter = 0;
1781
1782         RcvDataBufferHdr = (struct sxg_rcv_data_buffer_hdr *) Event->HostHandle;
1783         if(read_counter++ & 0x100)
1784         {
1785                 sxg_collect_statistics(adapter);
1786                 read_counter = 0;
1787         }
1788         ASSERT(RcvDataBufferHdr);
1789         ASSERT(RcvDataBufferHdr->State == SXG_BUFFER_ONCARD);
1790         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "SlowRcv", Event,
1791                   RcvDataBufferHdr, RcvDataBufferHdr->State,
1792                   /*RcvDataBufferHdr->VirtualAddress*/ 0);
1793         /* Drop rcv frames in non-running state */
1794         switch (adapter->State) {
1795         case SXG_STATE_RUNNING:
1796                 break;
1797         case SXG_STATE_PAUSING:
1798         case SXG_STATE_PAUSED:
1799         case SXG_STATE_HALTING:
1800                 goto drop;
1801         default:
1802                 ASSERT(0);
1803                 goto drop;
1804         }
1805
1806         /*
1807          * memcpy(SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr),
1808          *              RcvDataBufferHdr->VirtualAddress, Event->Length);
1809          */
1810
1811         /* Change buffer state to UPSTREAM */
1812         RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM;
1813         if (Event->Status & EVENT_STATUS_RCVERR) {
1814                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RcvError",
1815                           Event, Event->Status, Event->HostHandle, 0);
1816                 sxg_process_rcv_error(adapter, *(u32 *)
1817                                       SXG_RECEIVE_DATA_LOCATION
1818                                       (RcvDataBufferHdr));
1819                 goto drop;
1820         }
1821 #if XXXTODO                     /* VLAN stuff */
1822         /* If there's a VLAN tag, extract it and validate it */
1823         if (((struct ether_header *)
1824                 (SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr)))->EtherType
1825                                                         == ETHERTYPE_VLAN) {
1826                 if (SxgExtractVlanHeader(adapter, RcvDataBufferHdr, Event) !=
1827                     STATUS_SUCCESS) {
1828                         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY,
1829                                   "BadVlan", Event,
1830                                   SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr),
1831                                   Event->Length, 0);
1832                         goto drop;
1833                 }
1834         }
1835 #endif
1836         /* Dumb-nic frame.  See if it passes our mac filter and update stats */
1837
1838         if (!sxg_mac_filter(adapter,
1839             (struct ether_header *)(SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr)),
1840             Event->Length)) {
1841                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RcvFiltr",
1842                             Event, SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr),
1843                             Event->Length, 0);
1844           goto drop;
1845         }
1846
1847         Packet = RcvDataBufferHdr->SxgDumbRcvPacket;
1848         SXG_ADJUST_RCV_PACKET(Packet, RcvDataBufferHdr, Event);
1849         Packet->protocol = eth_type_trans(Packet, adapter->netdev);
1850
1851         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "DumbRcv",
1852                   RcvDataBufferHdr, Packet, Event->Length, 0);
1853         /* Lastly adjust the receive packet length. */
1854         RcvDataBufferHdr->SxgDumbRcvPacket = NULL;
1855         RcvDataBufferHdr->PhysicalAddress = (dma_addr_t)NULL;
1856         SXG_ALLOCATE_RCV_PACKET(adapter, RcvDataBufferHdr, BufferSize);
1857         if (RcvDataBufferHdr->skb)
1858         {
1859                 spin_lock(&adapter->RcvQLock);
1860                 SXG_FREE_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
1861                 // adapter->RcvBuffersOnCard ++;
1862                 spin_unlock(&adapter->RcvQLock);
1863         }
1864         return (Packet);
1865
1866       drop:
1867         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DropRcv",
1868                   RcvDataBufferHdr, Event->Length, 0, 0);
1869         adapter->stats.rx_dropped++;
1870 //      adapter->Stats.RcvDiscards++;
1871         spin_lock(&adapter->RcvQLock);
1872         SXG_FREE_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
1873         spin_unlock(&adapter->RcvQLock);
1874         return (NULL);
1875 }
1876
1877 /*
1878  * sxg_process_rcv_error - process receive error and update
1879  * stats
1880  *
1881  * Arguments:
1882  *              adapter         - Adapter structure
1883  *              ErrorStatus     - 4-byte receive error status
1884  *
1885  * Return Value         : None
1886  */
1887 static void sxg_process_rcv_error(struct adapter_t *adapter, u32 ErrorStatus)
1888 {
1889         u32 Error;
1890
1891         adapter->stats.rx_errors++;
1892
1893         if (ErrorStatus & SXG_RCV_STATUS_TRANSPORT_ERROR) {
1894                 Error = ErrorStatus & SXG_RCV_STATUS_TRANSPORT_MASK;
1895                 switch (Error) {
1896                 case SXG_RCV_STATUS_TRANSPORT_CSUM:
1897                         adapter->Stats.TransportCsum++;
1898                         break;
1899                 case SXG_RCV_STATUS_TRANSPORT_UFLOW:
1900                         adapter->Stats.TransportUflow++;
1901                         break;
1902                 case SXG_RCV_STATUS_TRANSPORT_HDRLEN:
1903                         adapter->Stats.TransportHdrLen++;
1904                         break;
1905                 }
1906         }
1907         if (ErrorStatus & SXG_RCV_STATUS_NETWORK_ERROR) {
1908                 Error = ErrorStatus & SXG_RCV_STATUS_NETWORK_MASK;
1909                 switch (Error) {
1910                 case SXG_RCV_STATUS_NETWORK_CSUM:
1911                         adapter->Stats.NetworkCsum++;
1912                         break;
1913                 case SXG_RCV_STATUS_NETWORK_UFLOW:
1914                         adapter->Stats.NetworkUflow++;
1915                         break;
1916                 case SXG_RCV_STATUS_NETWORK_HDRLEN:
1917                         adapter->Stats.NetworkHdrLen++;
1918                         break;
1919                 }
1920         }
1921         if (ErrorStatus & SXG_RCV_STATUS_PARITY) {
1922                 adapter->Stats.Parity++;
1923         }
1924         if (ErrorStatus & SXG_RCV_STATUS_LINK_ERROR) {
1925                 Error = ErrorStatus & SXG_RCV_STATUS_LINK_MASK;
1926                 switch (Error) {
1927                 case SXG_RCV_STATUS_LINK_PARITY:
1928                         adapter->Stats.LinkParity++;
1929                         break;
1930                 case SXG_RCV_STATUS_LINK_EARLY:
1931                         adapter->Stats.LinkEarly++;
1932                         break;
1933                 case SXG_RCV_STATUS_LINK_BUFOFLOW:
1934                         adapter->Stats.LinkBufOflow++;
1935                         break;
1936                 case SXG_RCV_STATUS_LINK_CODE:
1937                         adapter->Stats.LinkCode++;
1938                         break;
1939                 case SXG_RCV_STATUS_LINK_DRIBBLE:
1940                         adapter->Stats.LinkDribble++;
1941                         break;
1942                 case SXG_RCV_STATUS_LINK_CRC:
1943                         adapter->Stats.LinkCrc++;
1944                         break;
1945                 case SXG_RCV_STATUS_LINK_OFLOW:
1946                         adapter->Stats.LinkOflow++;
1947                         break;
1948                 case SXG_RCV_STATUS_LINK_UFLOW:
1949                         adapter->Stats.LinkUflow++;
1950                         break;
1951                 }
1952         }
1953 }
1954
1955 /*
1956  * sxg_mac_filter
1957  *
1958  * Arguments:
1959  *              adapter         - Adapter structure
1960  *              pether          - Ethernet header
1961  *              length          - Frame length
1962  *
1963  * Return Value : TRUE if the frame is to be allowed
1964  */
1965 static bool sxg_mac_filter(struct adapter_t *adapter,
1966                 struct ether_header *EtherHdr, ushort length)
1967 {
1968         bool EqualAddr;
1969         struct net_device *dev = adapter->netdev;
1970
1971         if (SXG_MULTICAST_PACKET(EtherHdr)) {
1972                 if (SXG_BROADCAST_PACKET(EtherHdr)) {
1973                         /* broadcast */
1974                         if (adapter->MacFilter & MAC_BCAST) {
1975                                 adapter->Stats.DumbRcvBcastPkts++;
1976                                 adapter->Stats.DumbRcvBcastBytes += length;
1977                                 return (TRUE);
1978                         }
1979                 } else {
1980                         /* multicast */
1981                         if (adapter->MacFilter & MAC_ALLMCAST) {
1982                                 adapter->Stats.DumbRcvMcastPkts++;
1983                                 adapter->Stats.DumbRcvMcastBytes += length;
1984                                 return (TRUE);
1985                         }
1986                         if (adapter->MacFilter & MAC_MCAST) {
1987                                 struct dev_mc_list *mclist = dev->mc_list;
1988                                 while (mclist) {
1989                                         ETHER_EQ_ADDR(mclist->da_addr,
1990                                                       EtherHdr->ether_dhost,
1991                                                       EqualAddr);
1992                                         if (EqualAddr) {
1993                                                 adapter->Stats.
1994                                                     DumbRcvMcastPkts++;
1995                                                 adapter->Stats.
1996                                                     DumbRcvMcastBytes += length;
1997                                                 return (TRUE);
1998                                         }
1999                                         mclist = mclist->next;
2000                                 }
2001                         }
2002                 }
2003         } else if (adapter->MacFilter & MAC_DIRECTED) {
2004                 /*
2005                  * Not broadcast or multicast.  Must be directed at us or
2006                  * the card is in promiscuous mode.  Either way, consider it
2007                  * ours if MAC_DIRECTED is set
2008                  */
2009                 adapter->Stats.DumbRcvUcastPkts++;
2010                 adapter->Stats.DumbRcvUcastBytes += length;
2011                 return (TRUE);
2012         }
2013         if (adapter->MacFilter & MAC_PROMISC) {
2014                 /* Whatever it is, keep it. */
2015                 return (TRUE);
2016         }
2017         return (FALSE);
2018 }
2019
2020 static int sxg_register_interrupt(struct adapter_t *adapter)
2021 {
2022         if (!adapter->intrregistered) {
2023                 int retval;
2024
2025                 DBG_ERROR
2026                     ("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x] %x\n",
2027                      __func__, adapter, adapter->netdev->irq, NR_IRQS);
2028
2029                 spin_unlock_irqrestore(&sxg_global.driver_lock,
2030                                        sxg_global.flags);
2031
2032                 retval = request_irq(adapter->netdev->irq,
2033                                      &sxg_isr,
2034                                      IRQF_SHARED,
2035                                      adapter->netdev->name, adapter->netdev);
2036
2037                 spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags);
2038
2039                 if (retval) {
2040                         DBG_ERROR("sxg: request_irq (%s) FAILED [%x]\n",
2041                                   adapter->netdev->name, retval);
2042                         return (retval);
2043                 }
2044                 adapter->intrregistered = 1;
2045                 adapter->IntRegistered = TRUE;
2046                 /* Disable RSS with line-based interrupts */
2047                 adapter->RssEnabled = FALSE;
2048                 DBG_ERROR("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x]\n",
2049                           __func__, adapter, adapter->netdev->irq);
2050         }
2051         return (STATUS_SUCCESS);
2052 }
2053
2054 static void sxg_deregister_interrupt(struct adapter_t *adapter)
2055 {
2056         DBG_ERROR("sxg: %s ENTER adapter[%p]\n", __func__, adapter);
2057 #if XXXTODO
2058         slic_init_cleanup(adapter);
2059 #endif
2060         memset(&adapter->stats, 0, sizeof(struct net_device_stats));
2061         adapter->error_interrupts = 0;
2062         adapter->rcv_interrupts = 0;
2063         adapter->xmit_interrupts = 0;
2064         adapter->linkevent_interrupts = 0;
2065         adapter->upr_interrupts = 0;
2066         adapter->num_isrs = 0;
2067         adapter->xmit_completes = 0;
2068         adapter->rcv_broadcasts = 0;
2069         adapter->rcv_multicasts = 0;
2070         adapter->rcv_unicasts = 0;
2071         DBG_ERROR("sxg: %s EXIT\n", __func__);
2072 }
2073
2074 /*
2075  *  sxg_if_init
2076  *
2077  *  Perform initialization of our slic interface.
2078  *
2079  */
2080 static int sxg_if_init(struct adapter_t *adapter)
2081 {
2082         struct net_device *dev = adapter->netdev;
2083         int status = 0;
2084
2085         DBG_ERROR("sxg: %s (%s) ENTER states[%d:%d] flags[%x]\n",
2086                   __func__, adapter->netdev->name,
2087                   adapter->state,
2088                   adapter->linkstate, dev->flags);
2089
2090         /* adapter should be down at this point */
2091         if (adapter->state != ADAPT_DOWN) {
2092                 DBG_ERROR("sxg_if_init adapter->state != ADAPT_DOWN\n");
2093                 return (-EIO);
2094         }
2095         ASSERT(adapter->linkstate == LINK_DOWN);
2096
2097         adapter->devflags_prev = dev->flags;
2098         adapter->MacFilter = MAC_DIRECTED;
2099         if (dev->flags) {
2100                 DBG_ERROR("sxg: %s (%s) Set MAC options: ", __func__,
2101                           adapter->netdev->name);
2102                 if (dev->flags & IFF_BROADCAST) {
2103                         adapter->MacFilter |= MAC_BCAST;
2104                         DBG_ERROR("BCAST ");
2105                 }
2106                 if (dev->flags & IFF_PROMISC) {
2107                         adapter->MacFilter |= MAC_PROMISC;
2108                         DBG_ERROR("PROMISC ");
2109                 }
2110                 if (dev->flags & IFF_ALLMULTI) {
2111                         adapter->MacFilter |= MAC_ALLMCAST;
2112                         DBG_ERROR("ALL_MCAST ");
2113                 }
2114                 if (dev->flags & IFF_MULTICAST) {
2115                         adapter->MacFilter |= MAC_MCAST;
2116                         DBG_ERROR("MCAST ");
2117                 }
2118                 DBG_ERROR("\n");
2119         }
2120         status = sxg_register_intr(adapter);
2121         if (status != STATUS_SUCCESS) {
2122                 DBG_ERROR("sxg_if_init: sxg_register_intr FAILED %x\n",
2123                           status);
2124                 sxg_deregister_interrupt(adapter);
2125                 return (status);
2126         }
2127
2128         adapter->state = ADAPT_UP;
2129
2130         /*    clear any pending events, then enable interrupts */
2131         DBG_ERROR("sxg: %s ENABLE interrupts(slic)\n", __func__);
2132
2133         return (STATUS_SUCCESS);
2134 }
2135
2136 void sxg_set_interrupt_aggregation(struct adapter_t *adapter)
2137 {
2138         /*
2139          * Top bit disables aggregation on xmt (SXG_AGG_XMT_DISABLE).
2140          * Make sure Max is less than 0x8000.
2141          */
2142         adapter->max_aggregation = SXG_MAX_AGG_DEFAULT;
2143         adapter->min_aggregation = SXG_MIN_AGG_DEFAULT;
2144         WRITE_REG(adapter->UcodeRegs[0].Aggregation,
2145                 ((adapter->max_aggregation << SXG_MAX_AGG_SHIFT) |
2146                         adapter->min_aggregation),
2147                         TRUE);
2148 }
2149
2150 static int sxg_entry_open(struct net_device *dev)
2151 {
2152         struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
2153         int status;
2154         static int turn;
2155         int sxg_initial_rcv_data_buffers = SXG_INITIAL_RCV_DATA_BUFFERS;
2156         int i;
2157
2158         if (adapter->JumboEnabled == TRUE) {
2159                 sxg_initial_rcv_data_buffers =
2160                                         SXG_INITIAL_JUMBO_RCV_DATA_BUFFERS;
2161                 SXG_INITIALIZE_RING(adapter->RcvRingZeroInfo,
2162                                         SXG_JUMBO_RCV_RING_SIZE);
2163         }
2164
2165         /*
2166         * Allocate receive data buffers.  We allocate a block of buffers and
2167         * a corresponding descriptor block at once.  See sxghw.h:SXG_RCV_BLOCK
2168         */
2169
2170         for (i = 0; i < sxg_initial_rcv_data_buffers;
2171                         i += SXG_RCV_DESCRIPTORS_PER_BLOCK)
2172         {
2173                 status = sxg_allocate_buffer_memory(adapter,
2174                 SXG_RCV_BLOCK_SIZE(SXG_RCV_DATA_HDR_SIZE),
2175                                         SXG_BUFFER_TYPE_RCV);
2176                 if (status != STATUS_SUCCESS)
2177                         return status;
2178         }
2179         /*
2180          * NBL resource allocation can fail in the 'AllocateComplete' routine,
2181          * which doesn't return status.  Make sure we got the number of buffers
2182          * we requested
2183          */
2184
2185         if (adapter->FreeRcvBufferCount < sxg_initial_rcv_data_buffers) {
2186                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF6",
2187                         adapter, adapter->FreeRcvBufferCount, SXG_MAX_ENTRIES,
2188                         0);
2189                 return (STATUS_RESOURCES);
2190         }
2191         /*
2192          * The microcode expects it to be downloaded on every open.
2193          */
2194         DBG_ERROR("sxg: %s ENTER sxg_download_microcode\n", __FUNCTION__);
2195         if (sxg_download_microcode(adapter, SXG_UCODE_SYSTEM)) {
2196                 DBG_ERROR("sxg: %s ENTER sxg_adapter_set_hwaddr\n",
2197                                 __FUNCTION__);
2198                 sxg_read_config(adapter);
2199         } else {
2200                 adapter->state = ADAPT_FAIL;
2201                 adapter->linkstate = LINK_DOWN;
2202                 DBG_ERROR("sxg_download_microcode FAILED status[%x]\n",
2203                                 status);
2204         }
2205         msleep(5);
2206
2207         if (turn) {
2208                 sxg_second_open(adapter->netdev);
2209
2210                 return STATUS_SUCCESS;
2211         }
2212
2213         turn++;
2214
2215         ASSERT(adapter);
2216         DBG_ERROR("sxg: %s adapter->activated[%d]\n", __func__,
2217                   adapter->activated);
2218         DBG_ERROR
2219             ("sxg: %s (%s): [jiffies[%lx] cpu %d] dev[%p] adapt[%p] port[%d]\n",
2220              __func__, adapter->netdev->name, jiffies, smp_processor_id(),
2221              adapter->netdev, adapter, adapter->port);
2222
2223         netif_stop_queue(adapter->netdev);
2224
2225         spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags);
2226         if (!adapter->activated) {
2227                 sxg_global.num_sxg_ports_active++;
2228                 adapter->activated = 1;
2229         }
2230         /* Initialize the adapter */
2231         DBG_ERROR("sxg: %s ENTER sxg_initialize_adapter\n", __func__);
2232         status = sxg_initialize_adapter(adapter);
2233         DBG_ERROR("sxg: %s EXIT sxg_initialize_adapter status[%x]\n",
2234                   __func__, status);
2235
2236         if (status == STATUS_SUCCESS) {
2237                 DBG_ERROR("sxg: %s ENTER sxg_if_init\n", __func__);
2238                 status = sxg_if_init(adapter);
2239                 DBG_ERROR("sxg: %s EXIT sxg_if_init status[%x]\n", __func__,
2240                           status);
2241         }
2242
2243         if (status != STATUS_SUCCESS) {
2244                 if (adapter->activated) {
2245                         sxg_global.num_sxg_ports_active--;
2246                         adapter->activated = 0;
2247                 }
2248                 spin_unlock_irqrestore(&sxg_global.driver_lock,
2249                                        sxg_global.flags);
2250                 return (status);
2251         }
2252         DBG_ERROR("sxg: %s ENABLE ALL INTERRUPTS\n", __func__);
2253         sxg_set_interrupt_aggregation(adapter);
2254         napi_enable(&adapter->napi);
2255
2256         /* Enable interrupts */
2257         SXG_ENABLE_ALL_INTERRUPTS(adapter);
2258
2259         DBG_ERROR("sxg: %s EXIT\n", __func__);
2260
2261         spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags);
2262         return STATUS_SUCCESS;
2263 }
2264
2265 int sxg_second_open(struct net_device * dev)
2266 {
2267         struct adapter_t *adapter = (struct adapter_t*) netdev_priv(dev);
2268         int status = 0;
2269
2270         spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags);
2271         netif_start_queue(adapter->netdev);
2272         adapter->state = ADAPT_UP;
2273         adapter->linkstate = LINK_UP;
2274
2275         status = sxg_initialize_adapter(adapter);
2276         sxg_set_interrupt_aggregation(adapter);
2277         napi_enable(&adapter->napi);
2278         /* Re-enable interrupts */
2279         SXG_ENABLE_ALL_INTERRUPTS(adapter);
2280
2281         netif_carrier_on(dev);
2282         sxg_register_interrupt(adapter);
2283         spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags);
2284         return (STATUS_SUCCESS);
2285
2286 }
2287
2288 static void __devexit sxg_entry_remove(struct pci_dev *pcidev)
2289 {
2290         u32 mmio_start = 0;
2291         u32 mmio_len = 0;
2292
2293         struct net_device *dev = pci_get_drvdata(pcidev);
2294         struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
2295
2296         flush_scheduled_work();
2297
2298         /* Deallocate Resources */
2299         unregister_netdev(dev);
2300         sxg_reset_interrupt_capability(adapter);
2301         sxg_free_resources(adapter);
2302
2303         ASSERT(adapter);
2304
2305         mmio_start = pci_resource_start(pcidev, 0);
2306         mmio_len = pci_resource_len(pcidev, 0);
2307
2308         DBG_ERROR("sxg: %s rel_region(0) start[%x] len[%x]\n", __FUNCTION__,
2309                   mmio_start, mmio_len);
2310         release_mem_region(mmio_start, mmio_len);
2311
2312         mmio_start = pci_resource_start(pcidev, 2);
2313         mmio_len = pci_resource_len(pcidev, 2);
2314
2315         DBG_ERROR("sxg: %s rel_region(2) start[%x] len[%x]\n", __FUNCTION__,
2316                   mmio_start, mmio_len);
2317         release_mem_region(mmio_start, mmio_len);
2318
2319         pci_disable_device(pcidev);
2320
2321         DBG_ERROR("sxg: %s deallocate device\n", __func__);
2322         kfree(dev);
2323         DBG_ERROR("sxg: %s EXIT\n", __func__);
2324 }
2325
2326 static int sxg_entry_halt(struct net_device *dev)
2327 {
2328         struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
2329         struct sxg_hw_regs *HwRegs = adapter->HwRegs;
2330         int i;
2331         u32 RssIds, IsrCount;
2332         unsigned long flags;
2333
2334         RssIds = SXG_RSS_CPU_COUNT(adapter);
2335         IsrCount = adapter->msi_enabled ? RssIds : 1;
2336
2337         napi_disable(&adapter->napi);
2338         spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags);
2339         DBG_ERROR("sxg: %s (%s) ENTER\n", __func__, dev->name);
2340
2341         WRITE_REG(adapter->UcodeRegs[0].RcvCmd, 0, true);
2342         netif_stop_queue(adapter->netdev);
2343         adapter->state = ADAPT_DOWN;
2344         adapter->linkstate = LINK_DOWN;
2345         adapter->devflags_prev = 0;
2346         DBG_ERROR("sxg: %s (%s) set adapter[%p] state to ADAPT_DOWN(%d)\n",
2347                   __func__, dev->name, adapter, adapter->state);
2348
2349         /* Disable interrupts */
2350         SXG_DISABLE_ALL_INTERRUPTS(adapter);
2351
2352         netif_carrier_off(dev);
2353         spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags);
2354
2355         sxg_deregister_interrupt(adapter);
2356         WRITE_REG(HwRegs->Reset, 0xDEAD, FLUSH);
2357         mdelay(5000);
2358         spin_lock(&adapter->RcvQLock);
2359         /* Free all the blocks and the buffers, moved from remove() routine */
2360         if (!(IsListEmpty(&adapter->AllRcvBlocks))) {
2361                 sxg_free_rcvblocks(adapter);
2362         }
2363
2364
2365         InitializeListHead(&adapter->FreeRcvBuffers);
2366         InitializeListHead(&adapter->FreeRcvBlocks);
2367         InitializeListHead(&adapter->AllRcvBlocks);
2368         InitializeListHead(&adapter->FreeSglBuffers);
2369         InitializeListHead(&adapter->AllSglBuffers);
2370
2371         adapter->FreeRcvBufferCount = 0;
2372         adapter->FreeRcvBlockCount = 0;
2373         adapter->AllRcvBlockCount = 0;
2374         adapter->RcvBuffersOnCard = 0;
2375         adapter->PendingRcvCount = 0;
2376
2377         memset(adapter->RcvRings, 0, sizeof(struct sxg_rcv_ring) * 1);
2378         memset(adapter->EventRings, 0, sizeof(struct sxg_event_ring) * RssIds);
2379         memset(adapter->Isr, 0, sizeof(u32) * IsrCount);
2380         for (i = 0; i < SXG_MAX_RING_SIZE; i++)
2381                 adapter->RcvRingZeroInfo.Context[i] = NULL;
2382         SXG_INITIALIZE_RING(adapter->RcvRingZeroInfo, SXG_RCV_RING_SIZE);
2383         SXG_INITIALIZE_RING(adapter->XmtRingZeroInfo, SXG_XMT_RING_SIZE);
2384
2385         spin_unlock(&adapter->RcvQLock);
2386
2387         spin_lock_irqsave(&adapter->XmtZeroLock, flags);
2388         adapter->AllSglBufferCount = 0;
2389         adapter->FreeSglBufferCount = 0;
2390         adapter->PendingXmtCount = 0;
2391         memset(adapter->XmtRings, 0, sizeof(struct sxg_xmt_ring) * 1);
2392         memset(adapter->XmtRingZeroIndex, 0, sizeof(u32));
2393         spin_unlock_irqrestore(&adapter->XmtZeroLock, flags);
2394
2395         for (i = 0; i < SXG_MAX_RSS; i++) {
2396                 adapter->NextEvent[i] = 0;
2397         }
2398         atomic_set(&adapter->pending_allocations, 0);
2399         adapter->intrregistered = 0;
2400         sxg_remove_isr(adapter);
2401         DBG_ERROR("sxg: %s (%s) EXIT\n", __FUNCTION__, dev->name);
2402         return (STATUS_SUCCESS);
2403 }
2404
2405 static int sxg_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2406 {
2407         ASSERT(rq);
2408 /*      DBG_ERROR("sxg: %s cmd[%x] rq[%p] dev[%p]\n", __func__, cmd, rq, dev);*/
2409         switch (cmd) {
2410         case SIOCSLICSETINTAGG:
2411                 {
2412                         /* struct adapter_t *adapter = (struct adapter_t *)
2413                          * netdev_priv(dev);
2414                          */
2415                         u32 data[7];
2416                         u32 intagg;
2417
2418                         if (copy_from_user(data, rq->ifr_data, 28)) {
2419                                 DBG_ERROR("copy_from_user FAILED  getting \
2420                                          initial params\n");
2421                                 return -EFAULT;
2422                         }
2423                         intagg = data[0];
2424                         printk(KERN_EMERG
2425                                "%s: set interrupt aggregation to %d\n",
2426                                __func__, intagg);
2427                         return 0;
2428                 }
2429
2430         default:
2431                 /* DBG_ERROR("sxg: %s UNSUPPORTED[%x]\n", __func__, cmd); */
2432                 return -EOPNOTSUPP;
2433         }
2434         return 0;
2435 }
2436
2437 #define NORMAL_ETHFRAME     0
2438
2439 /*
2440  * sxg_send_packets - Send a skb packet
2441  *
2442  * Arguments:
2443  *                      skb - The packet to send
2444  *                      dev - Our linux net device that refs our adapter
2445  *
2446  * Return:
2447  *              0   regardless of outcome    XXXTODO refer to e1000 driver
2448  */
2449 static int sxg_send_packets(struct sk_buff *skb, struct net_device *dev)
2450 {
2451         struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
2452         u32 status = STATUS_SUCCESS;
2453
2454         /*
2455          * DBG_ERROR("sxg: %s ENTER sxg_send_packets skb[%p]\n", __FUNCTION__,
2456          *        skb);
2457          */
2458
2459         /* Check the adapter state */
2460         switch (adapter->State) {
2461         case SXG_STATE_INITIALIZING:
2462         case SXG_STATE_HALTED:
2463         case SXG_STATE_SHUTDOWN:
2464                 ASSERT(0);      /* unexpected */
2465                 /* fall through */
2466         case SXG_STATE_RESETTING:
2467         case SXG_STATE_SLEEP:
2468         case SXG_STATE_BOOTDIAG:
2469         case SXG_STATE_DIAG:
2470         case SXG_STATE_HALTING:
2471                 status = STATUS_FAILURE;
2472                 break;
2473         case SXG_STATE_RUNNING:
2474                 if (adapter->LinkState != SXG_LINK_UP) {
2475                         status = STATUS_FAILURE;
2476                 }
2477                 break;
2478         default:
2479                 ASSERT(0);
2480                 status = STATUS_FAILURE;
2481         }
2482         if (status != STATUS_SUCCESS) {
2483                 goto xmit_fail;
2484         }
2485         /* send a packet */
2486         status = sxg_transmit_packet(adapter, skb);
2487         if (status == STATUS_SUCCESS) {
2488                 goto xmit_done;
2489         }
2490
2491       xmit_fail:
2492         /* reject & complete all the packets if they cant be sent */
2493         if (status != STATUS_SUCCESS) {
2494 #if XXXTODO
2495         /* sxg_send_packets_fail(adapter, skb, status); */
2496 #else
2497                 SXG_DROP_DUMB_SEND(adapter, skb);
2498                 adapter->stats.tx_dropped++;
2499                 return NETDEV_TX_BUSY;
2500 #endif
2501         }
2502         DBG_ERROR("sxg: %s EXIT sxg_send_packets status[%x]\n", __func__,
2503                   status);
2504
2505       xmit_done:
2506         return NETDEV_TX_OK;
2507 }
2508
2509 /*
2510  * sxg_transmit_packet
2511  *
2512  * This function transmits a single packet.
2513  *
2514  * Arguments -
2515  *              adapter                 - Pointer to our adapter structure
2516  *      skb             - The packet to be sent
2517  *
2518  * Return - STATUS of send
2519  */
2520 static int sxg_transmit_packet(struct adapter_t *adapter, struct sk_buff *skb)
2521 {
2522         struct sxg_x64_sgl         *pSgl;
2523         struct sxg_scatter_gather  *SxgSgl;
2524         unsigned long sgl_flags;
2525         /* void *SglBuffer; */
2526         /* u32 SglBufferLength; */
2527
2528         /*
2529          * The vast majority of work is done in the shared
2530          * sxg_dumb_sgl routine.
2531          */
2532         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbSend",
2533                   adapter, skb, 0, 0);
2534
2535         /* Allocate a SGL buffer */
2536         SXG_GET_SGL_BUFFER(adapter, SxgSgl, 0);
2537         if (!SxgSgl) {
2538                 adapter->Stats.NoSglBuf++;
2539                 adapter->stats.tx_errors++;
2540                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "SndPktF1",
2541                           adapter, skb, 0, 0);
2542                 return (STATUS_RESOURCES);
2543         }
2544         ASSERT(SxgSgl->adapter == adapter);
2545         /*SglBuffer = SXG_SGL_BUFFER(SxgSgl);
2546         SglBufferLength = SXG_SGL_BUF_SIZE; */
2547         SxgSgl->VlanTag.VlanTci = 0;
2548         SxgSgl->VlanTag.VlanTpid = 0;
2549         SxgSgl->Type = SXG_SGL_DUMB;
2550         SxgSgl->DumbPacket = skb;
2551         pSgl = NULL;
2552
2553         /* Call the common sxg_dumb_sgl routine to complete the send. */
2554         return (sxg_dumb_sgl(pSgl, SxgSgl));
2555 }
2556
2557 /*
2558  * sxg_dumb_sgl
2559  *
2560  * Arguments:
2561  *              pSgl     -
2562  *              SxgSgl   - struct sxg_scatter_gather
2563  *
2564  * Return Value:
2565  *      Status of send operation.
2566  */
2567 static int sxg_dumb_sgl(struct sxg_x64_sgl *pSgl,
2568                                 struct sxg_scatter_gather *SxgSgl)
2569 {
2570         struct adapter_t *adapter = SxgSgl->adapter;
2571         struct sk_buff *skb = SxgSgl->DumbPacket;
2572         /* For now, all dumb-nic sends go on RSS queue zero */
2573         struct sxg_xmt_ring *XmtRing = &adapter->XmtRings[0];
2574         struct sxg_ring_info *XmtRingInfo = &adapter->XmtRingZeroInfo;
2575         struct sxg_cmd *XmtCmd = NULL;
2576         /* u32 Index = 0; */
2577         u32 DataLength = skb->len;
2578         /* unsigned int BufLen; */
2579         /* u32 SglOffset; */
2580         u64 phys_addr;
2581         unsigned long flags;
2582         unsigned long queue_id=0;
2583
2584         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbSgl",
2585                   pSgl, SxgSgl, 0, 0);
2586
2587         /* Set aside a pointer to the sgl */
2588         SxgSgl->pSgl = pSgl;
2589
2590         /* Sanity check that our SGL format is as we expect. */
2591         ASSERT(sizeof(struct sxg_x64_sge) == sizeof(struct sxg_x64_sge));
2592         /* Shouldn't be a vlan tag on this frame */
2593         ASSERT(SxgSgl->VlanTag.VlanTci == 0);
2594         ASSERT(SxgSgl->VlanTag.VlanTpid == 0);
2595
2596         /*
2597          * From here below we work with the SGL placed in our
2598          * buffer.
2599          */
2600
2601         SxgSgl->Sgl.NumberOfElements = 1;
2602         /*
2603          * Set ucode Queue ID based on bottom bits of destination TCP port.
2604          * This Queue ID splits slowpath/dumb-nic packet processing across
2605          * multiple threads on the card to improve performance.  It is split
2606          * using the TCP port to avoid out-of-order packets that can result
2607          * from multithreaded processing.  We use the destination port because
2608          * we expect to be run on a server, so in nearly all cases the local
2609          * port is likely to be constant (well-known server port) and the
2610          * remote port is likely to be random.  The exception to this is iSCSI,
2611          * in which case we use the sport instead.  Note
2612          * that original attempt at XOR'ing source and dest port resulted in
2613          * poor balance on NTTTCP/iometer applications since they tend to
2614          * line up (even-even, odd-odd..).
2615          */
2616
2617         if (skb->protocol == htons(ETH_P_IP)) {
2618                 struct iphdr *ip;
2619
2620                 ip = ip_hdr(skb);
2621                 if ((ip->protocol == IPPROTO_TCP)&&(DataLength >= sizeof(
2622                                                         struct tcphdr))){
2623                         queue_id = ((ntohs(tcp_hdr(skb)->dest) == ISCSI_PORT) ?
2624                                         (ntohs (tcp_hdr(skb)->source) &
2625                                                 SXG_LARGE_SEND_QUEUE_MASK):
2626                                                 (ntohs(tcp_hdr(skb)->dest) &
2627                                                 SXG_LARGE_SEND_QUEUE_MASK));
2628                 }
2629         } else if (skb->protocol == htons(ETH_P_IPV6)) {
2630                 if ((ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) && (DataLength >=
2631                                                  sizeof(struct tcphdr)) ) {
2632                         queue_id = ((ntohs(tcp_hdr(skb)->dest) == ISCSI_PORT) ?
2633                                         (ntohs (tcp_hdr(skb)->source) &
2634                                         SXG_LARGE_SEND_QUEUE_MASK):
2635                                         (ntohs(tcp_hdr(skb)->dest) &
2636                                         SXG_LARGE_SEND_QUEUE_MASK));
2637                 }
2638         }
2639
2640         /* Grab the spinlock and acquire a command */
2641         spin_lock_irqsave(&adapter->XmtZeroLock, flags);
2642         SXG_GET_CMD(XmtRing, XmtRingInfo, XmtCmd, SxgSgl);
2643         if (XmtCmd == NULL) {
2644                 /*
2645                  * Call sxg_complete_slow_send to see if we can
2646                  * free up any XmtRingZero entries and then try again
2647                  */
2648
2649                 spin_unlock_irqrestore(&adapter->XmtZeroLock, flags);
2650                 sxg_complete_slow_send(adapter);
2651                 spin_lock_irqsave(&adapter->XmtZeroLock, flags);
2652                 SXG_GET_CMD(XmtRing, XmtRingInfo, XmtCmd, SxgSgl);
2653                 if (XmtCmd == NULL) {
2654                         adapter->Stats.XmtZeroFull++;
2655                         goto abortcmd;
2656                 }
2657         }
2658         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbCmd",
2659                   XmtCmd, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
2660         /* Update stats */
2661         adapter->stats.tx_packets++;
2662         adapter->stats.tx_bytes += DataLength;
2663 #if XXXTODO                     /* Stats stuff */
2664         if (SXG_MULTICAST_PACKET(EtherHdr)) {
2665                 if (SXG_BROADCAST_PACKET(EtherHdr)) {
2666                         adapter->Stats.DumbXmtBcastPkts++;
2667                         adapter->Stats.DumbXmtBcastBytes += DataLength;
2668                 } else {
2669                         adapter->Stats.DumbXmtMcastPkts++;
2670                         adapter->Stats.DumbXmtMcastBytes += DataLength;
2671                 }
2672         } else {
2673                 adapter->Stats.DumbXmtUcastPkts++;
2674                 adapter->Stats.DumbXmtUcastBytes += DataLength;
2675         }
2676 #endif
2677         /*
2678          * Fill in the command
2679          * Copy out the first SGE to the command and adjust for offset
2680          */
2681         phys_addr = pci_map_single(adapter->pcidev, skb->data, skb->len,
2682                            PCI_DMA_TODEVICE);
2683
2684         /*
2685          * SAHARA SGL WORKAROUND
2686          * See if the SGL straddles a 64k boundary.  If so, skip to
2687          * the start of the next 64k boundary and continue
2688          */
2689
2690         if ((adapter->asictype == SAHARA_REV_A) &&
2691                 (SXG_INVALID_SGL(phys_addr,skb->data_len)))
2692         {
2693                 spin_unlock_irqrestore(&adapter->XmtZeroLock, flags);
2694                 /* Silently drop this packet */
2695                 printk(KERN_EMERG"Dropped a packet for 64k boundary problem\n");
2696                 return STATUS_SUCCESS;
2697         }
2698         memset(XmtCmd, '\0', sizeof(*XmtCmd));
2699         XmtCmd->Buffer.FirstSgeAddress = phys_addr;
2700         XmtCmd->Buffer.FirstSgeLength = DataLength;
2701         XmtCmd->Buffer.SgeOffset = 0;
2702         XmtCmd->Buffer.TotalLength = DataLength;
2703         XmtCmd->SgEntries = 1;
2704         XmtCmd->Flags = 0;
2705
2706         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2707                 /*
2708                  * We need to set the Checkum in IP  header to 0. This is
2709                  * required by hardware.
2710                  */
2711                 ip_hdr(skb)->check = 0x0;
2712                 XmtCmd->CsumFlags.Flags |= SXG_SLOWCMD_CSUM_IP;
2713                 XmtCmd->CsumFlags.Flags |= SXG_SLOWCMD_CSUM_TCP;
2714                 /* Dont know if length will require a change in case of VLAN */
2715                 XmtCmd->CsumFlags.MacLen = ETH_HLEN;
2716                 XmtCmd->CsumFlags.IpHl = skb_network_header_len(skb) >>
2717                                                         SXG_NW_HDR_LEN_SHIFT;
2718         }
2719         /*
2720          * Advance transmit cmd descripter by 1.
2721          * NOTE - See comments in SxgTcpOutput where we write
2722          * to the XmtCmd register regarding CPU ID values and/or
2723          * multiple commands.
2724          * Top 16 bits specify queue_id.  See comments about queue_id above
2725          */
2726         /* Four queues at the moment */
2727         ASSERT((queue_id & ~SXG_LARGE_SEND_QUEUE_MASK) == 0);
2728         WRITE_REG(adapter->UcodeRegs[0].XmtCmd, ((queue_id << 16) | 1), TRUE);
2729         adapter->Stats.XmtQLen++;       /* Stats within lock */
2730         spin_unlock_irqrestore(&adapter->XmtZeroLock, flags);
2731         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDumSgl2",
2732                   XmtCmd, pSgl, SxgSgl, 0);
2733         return  STATUS_SUCCESS;
2734
2735       abortcmd:
2736         /*
2737          * NOTE - Only jump to this label AFTER grabbing the
2738          * XmtZeroLock, and DO NOT DROP IT between the
2739          * command allocation and the following abort.
2740          */
2741         if (XmtCmd) {
2742                 SXG_ABORT_CMD(XmtRingInfo);
2743         }
2744         spin_unlock_irqrestore(&adapter->XmtZeroLock, flags);
2745
2746 /*
2747  * failsgl:
2748  *      Jump to this label if failure occurs before the
2749  *      XmtZeroLock is grabbed
2750  */
2751         adapter->stats.tx_errors++;
2752         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "DumSGFal",
2753                   pSgl, SxgSgl, XmtRingInfo->Head, XmtRingInfo->Tail);
2754         /* SxgSgl->DumbPacket is the skb */
2755         // SXG_COMPLETE_DUMB_SEND(adapter, SxgSgl->DumbPacket);
2756
2757         return STATUS_FAILURE;
2758 }
2759
2760 /*
2761  * Link management functions
2762  *
2763  * sxg_initialize_link - Initialize the link stuff
2764  *
2765  * Arguments -
2766  *      adapter         - A pointer to our adapter structure
2767  *
2768  * Return
2769  *      status
2770  */
2771 static int sxg_initialize_link(struct adapter_t *adapter)
2772 {
2773         struct sxg_hw_regs *HwRegs = adapter->HwRegs;
2774         u32 Value;
2775         u32 ConfigData;
2776         u32 MaxFrame;
2777         u32 AxgMacReg1;
2778         int status;
2779
2780         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitLink",
2781                   adapter, 0, 0, 0);
2782
2783         /* Reset PHY and XGXS module */
2784         WRITE_REG(HwRegs->LinkStatus, LS_SERDES_POWER_DOWN, TRUE);
2785
2786         /* Reset transmit configuration register */
2787         WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_RESET, TRUE);
2788
2789         /* Reset receive configuration register */
2790         WRITE_REG(HwRegs->RcvConfig, RCV_CONFIG_RESET, TRUE);
2791
2792         /* Reset all MAC modules */
2793         WRITE_REG(HwRegs->MacConfig0, AXGMAC_CFG0_SUB_RESET, TRUE);
2794
2795         /*
2796          * Link address 0
2797          * XXXTODO - This assumes the MAC address (0a:0b:0c:0d:0e:0f)
2798          * is stored with the first nibble (0a) in the byte 0
2799          * of the Mac address.  Possibly reverse?
2800          */
2801         Value = *(u32 *) adapter->macaddr;
2802         WRITE_REG(HwRegs->LinkAddress0Low, Value, TRUE);
2803         /* also write the MAC address to the MAC.  Endian is reversed. */
2804         WRITE_REG(HwRegs->MacAddressLow, ntohl(Value), TRUE);
2805         Value = (*(u16 *) & adapter->macaddr[4] & 0x0000FFFF);
2806         WRITE_REG(HwRegs->LinkAddress0High, Value | LINK_ADDRESS_ENABLE, TRUE);
2807         /* endian swap for the MAC (put high bytes in bits [31:16], swapped) */
2808         Value = ntohl(Value);
2809         WRITE_REG(HwRegs->MacAddressHigh, Value, TRUE);
2810         /* Link address 1 */
2811         WRITE_REG(HwRegs->LinkAddress1Low, 0, TRUE);
2812         WRITE_REG(HwRegs->LinkAddress1High, 0, TRUE);
2813         /* Link address 2 */
2814         WRITE_REG(HwRegs->LinkAddress2Low, 0, TRUE);
2815         WRITE_REG(HwRegs->LinkAddress2High, 0, TRUE);
2816         /* Link address 3 */
2817         WRITE_REG(HwRegs->LinkAddress3Low, 0, TRUE);
2818         WRITE_REG(HwRegs->LinkAddress3High, 0, TRUE);
2819
2820         /* Enable MAC modules */
2821         WRITE_REG(HwRegs->MacConfig0, 0, TRUE);
2822
2823         /* Configure MAC */
2824         AxgMacReg1 = (  /* Enable XMT */
2825                         AXGMAC_CFG1_XMT_EN |
2826                         /* Enable receive */
2827                         AXGMAC_CFG1_RCV_EN |
2828                         /* short frame detection */
2829                         AXGMAC_CFG1_SHORT_ASSERT |
2830                         /* Verify frame length */
2831                         AXGMAC_CFG1_CHECK_LEN |
2832                         /* Generate FCS */
2833                         AXGMAC_CFG1_GEN_FCS |
2834                         /* Pad frames to 64 bytes */
2835                         AXGMAC_CFG1_PAD_64);
2836
2837         if (adapter->XmtFcEnabled) {
2838                 AxgMacReg1 |=  AXGMAC_CFG1_XMT_PAUSE;  /* Allow sending of pause */
2839         }
2840         if (adapter->RcvFcEnabled) {
2841                 AxgMacReg1 |=  AXGMAC_CFG1_RCV_PAUSE;  /* Enable detection of pause */
2842         }
2843
2844         WRITE_REG(HwRegs->MacConfig1, AxgMacReg1, TRUE);
2845
2846         /* Set AXGMAC max frame length if jumbo.  Not needed for standard MTU */
2847         if (adapter->JumboEnabled) {
2848                 WRITE_REG(HwRegs->MacMaxFrameLen, AXGMAC_MAXFRAME_JUMBO, TRUE);
2849         }
2850         /*
2851          * AMIIM Configuration Register -
2852          * The value placed in the AXGMAC_AMIIM_CFG_HALF_CLOCK portion
2853          * (bottom bits) of this register is used to determine the MDC frequency
2854          * as specified in the A-XGMAC Design Document. This value must not be
2855          * zero.  The following value (62 or 0x3E) is based on our MAC transmit
2856          * clock frequency (MTCLK) of 312.5 MHz. Given a maximum MDIO clock
2857          * frequency of 2.5 MHz (see the PHY spec), we get:
2858          *      312.5/(2*(X+1)) < 2.5  ==> X = 62.
2859          * This value happens to be the default value for this register, so we
2860          * really don't have to do this.
2861          */
2862         if (adapter->asictype == SAHARA_REV_B) {
2863                 WRITE_REG(HwRegs->MacAmiimConfig, 0x0000001F, TRUE);
2864         } else {
2865                 WRITE_REG(HwRegs->MacAmiimConfig, 0x0000003E, TRUE);
2866         }
2867
2868         /* Power up and enable PHY and XAUI/XGXS/Serdes logic */
2869         WRITE_REG(HwRegs->LinkStatus,
2870                    (LS_PHY_CLR_RESET |
2871                     LS_XGXS_ENABLE |
2872                     LS_XGXS_CTL |
2873                     LS_PHY_CLK_EN |
2874                     LS_ATTN_ALARM),
2875                     TRUE);
2876         DBG_ERROR("After Power Up and enable PHY in sxg_initialize_link\n");
2877
2878         /*
2879          * Per information given by Aeluros, wait 100 ms after removing reset.
2880          * It's not enough to wait for the self-clearing reset bit in reg 0 to
2881          * clear.
2882          */
2883         mdelay(100);
2884
2885         /* Verify the PHY has come up by checking that the Reset bit has
2886          * cleared.
2887          */
2888         status = sxg_read_mdio_reg(adapter,
2889                                 MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
2890                                 PHY_PMA_CONTROL1, /* PMA/PMD control register */
2891                                 &Value);
2892         DBG_ERROR("After sxg_read_mdio_reg Value[%x] fail=%x\n", Value,
2893                                          (Value & PMA_CONTROL1_RESET));
2894         if (status != STATUS_SUCCESS)
2895                 return (STATUS_FAILURE);
2896         if (Value & PMA_CONTROL1_RESET) /* reset complete if bit is 0 */
2897                 return (STATUS_FAILURE);
2898
2899         /* The SERDES should be initialized by now - confirm */
2900         READ_REG(HwRegs->LinkStatus, Value);
2901         if (Value & LS_SERDES_DOWN)     /* verify SERDES is initialized */
2902                 return (STATUS_FAILURE);
2903
2904         /* The XAUI link should also be up - confirm */
2905         if (!(Value & LS_XAUI_LINK_UP)) /* verify XAUI link is up */
2906                 return (STATUS_FAILURE);
2907
2908         /* Initialize the PHY */
2909         status = sxg_phy_init(adapter);
2910         if (status != STATUS_SUCCESS)
2911                 return (STATUS_FAILURE);
2912
2913         /* Enable the Link Alarm */
2914
2915         /* MIIM_DEV_PHY_PMA             - PHY PMA/PMD module
2916          * LASI_CONTROL                 - LASI control register
2917          * LASI_CTL_LS_ALARM_ENABLE     - enable link alarm bit
2918          */
2919         status = sxg_write_mdio_reg(adapter, MIIM_DEV_PHY_PMA,
2920                                     LASI_CONTROL,
2921                                     LASI_CTL_LS_ALARM_ENABLE);
2922         if (status != STATUS_SUCCESS)
2923                 return (STATUS_FAILURE);
2924
2925         /* XXXTODO - temporary - verify bit is set */
2926
2927         /* MIIM_DEV_PHY_PMA             - PHY PMA/PMD module
2928          * LASI_CONTROL                 - LASI control register
2929          */
2930         status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA,
2931                                    LASI_CONTROL,
2932                                    &Value);
2933
2934         if (status != STATUS_SUCCESS)
2935                 return (STATUS_FAILURE);
2936         if (!(Value & LASI_CTL_LS_ALARM_ENABLE)) {
2937                 DBG_ERROR("Error!  LASI Control Alarm Enable bit not set!\n");
2938         }
2939         /* Enable receive */
2940         MaxFrame = adapter->JumboEnabled ? JUMBOMAXFRAME : ETHERMAXFRAME;
2941         ConfigData = (RCV_CONFIG_ENABLE |
2942                       RCV_CONFIG_ENPARSE |
2943                       RCV_CONFIG_RCVBAD |
2944                       RCV_CONFIG_RCVPAUSE |
2945                       RCV_CONFIG_TZIPV6 |
2946                       RCV_CONFIG_TZIPV4 |
2947                       RCV_CONFIG_HASH_16 |
2948                       RCV_CONFIG_SOCKET | RCV_CONFIG_BUFSIZE(MaxFrame));
2949
2950         if (adapter->asictype == SAHARA_REV_B) {
2951                 ConfigData |= (RCV_CONFIG_HIPRICTL  |
2952                                 RCV_CONFIG_NEWSTATUSFMT);
2953         }
2954         WRITE_REG(HwRegs->RcvConfig, ConfigData, TRUE);
2955
2956         WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_ENABLE, TRUE);
2957
2958         /* Mark the link as down.  We'll get a link event when it comes up. */
2959         sxg_link_state(adapter, SXG_LINK_DOWN);
2960
2961         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XInitLnk",
2962                   adapter, 0, 0, 0);
2963         return (STATUS_SUCCESS);
2964 }
2965
2966 /*
2967  * sxg_phy_init - Initialize the PHY
2968  *
2969  * Arguments -
2970  *      adapter         - A pointer to our adapter structure
2971  *
2972  * Return
2973  *      status
2974  */
2975 static int sxg_phy_init(struct adapter_t *adapter)
2976 {
2977         u32 Value;
2978         struct phy_ucode *p;
2979         int status;
2980
2981         DBG_ERROR("ENTER %s\n", __func__);
2982
2983         /* MIIM_DEV_PHY_PMA - PHY PMA/PMD module
2984          * 0xC205 - PHY ID register (?)
2985          * &Value - XXXTODO - add def
2986          */
2987         status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA,
2988                                    0xC205,
2989                                    &Value);
2990         if (status != STATUS_SUCCESS)
2991                 return (STATUS_FAILURE);
2992
2993         if (Value == 0x0012) {
2994                 /* 0x0012 == AEL2005C PHY(?) - XXXTODO - add def */
2995                 DBG_ERROR("AEL2005C PHY detected.  Downloading PHY \
2996                                  microcode.\n");
2997
2998                 /* Initialize AEL2005C PHY and download PHY microcode */
2999                 for (p = PhyUcode; p->Addr != 0xFFFF; p++) {
3000                         if (p->Addr == 0) {
3001                                 /* if address == 0, data == sleep time in ms */
3002                                 mdelay(p->Data);
3003                         } else {
3004                         /* write the given data to the specified address */
3005                                 status = sxg_write_mdio_reg(adapter,
3006                                                         MIIM_DEV_PHY_PMA,
3007                                                         /* PHY address */
3008                                                             p->Addr,
3009                                                         /* PHY data */
3010                                                             p->Data);
3011                                 if (status != STATUS_SUCCESS)
3012                                         return (STATUS_FAILURE);
3013                         }
3014                 }
3015         }
3016         DBG_ERROR("EXIT %s\n", __func__);
3017
3018         return (STATUS_SUCCESS);
3019 }
3020
3021 /*
3022  * sxg_link_event - Process a link event notification from the card
3023  *
3024  * Arguments -
3025  *      adapter         - A pointer to our adapter structure
3026  *
3027  * Return
3028  *      None
3029  */
3030 static void sxg_link_event(struct adapter_t *adapter)
3031 {
3032         struct sxg_hw_regs *HwRegs = adapter->HwRegs;
3033         struct net_device *netdev = adapter->netdev;
3034         enum SXG_LINK_STATE LinkState;
3035         int status;
3036         u32 Value;
3037
3038         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "LinkEvnt",
3039                   adapter, 0, 0, 0);
3040         DBG_ERROR("ENTER %s\n", __func__);
3041
3042         /* Check the Link Status register.  We should have a Link Alarm. */
3043         READ_REG(HwRegs->LinkStatus, Value);
3044         if (Value & LS_LINK_ALARM) {
3045                 /*
3046                  * We got a Link Status alarm.  First, pause to let the
3047                  * link state settle (it can bounce a number of times)
3048                  */
3049                 mdelay(10);
3050
3051                 /* Now clear the alarm by reading the LASI status register. */
3052                 /* MIIM_DEV_PHY_PMA - PHY PMA/PMD module */
3053                 status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA,
3054                                         /* LASI status register */
3055                                            LASI_STATUS,
3056                                            &Value);
3057                 if (status != STATUS_SUCCESS) {
3058                         DBG_ERROR("Error reading LASI Status MDIO register!\n");
3059                         sxg_link_state(adapter, SXG_LINK_DOWN);
3060                 /* ASSERT(0); */
3061                 }
3062                 /*
3063                  * We used to assert that the LASI_LS_ALARM bit was set, as
3064                  * it should be.  But there appears to be cases during
3065                  * initialization (when the PHY is reset and re-initialized)
3066                  * when we get a link alarm, but the status bit is 0 when we
3067                  * read it.  Rather than trying to assure this never happens
3068                  * (and nver being certain), just ignore it.
3069
3070                  * ASSERT(Value & LASI_STATUS_LS_ALARM);
3071                  */
3072
3073                 /* Now get and set the link state */
3074                 LinkState = sxg_get_link_state(adapter);
3075                 sxg_link_state(adapter, LinkState);
3076                 DBG_ERROR("SXG: Link Alarm occurred.  Link is %s\n",
3077                           ((LinkState == SXG_LINK_UP) ? "UP" : "DOWN"));
3078                 if (LinkState == SXG_LINK_UP)
3079                         netif_carrier_on(netdev);
3080                 else
3081                         netif_carrier_off(netdev);
3082         } else {
3083                 /*
3084                  * XXXTODO - Assuming Link Attention is only being generated
3085                  * for the Link Alarm pin (and not for a XAUI Link Status change)
3086                  * , then it's impossible to get here.  Yet we've gotten here
3087                  * twice (under extreme conditions - bouncing the link up and
3088                  * down many times a second). Needs further investigation.
3089                  */
3090                 DBG_ERROR("SXG: sxg_link_event: Can't get here!\n");
3091                 DBG_ERROR("SXG: Link Status == 0x%08X.\n", Value);
3092                 /* ASSERT(0); */
3093         }
3094         DBG_ERROR("EXIT %s\n", __func__);
3095
3096 }
3097
3098 /*
3099  * sxg_get_link_state - Determine if the link is up or down
3100  *
3101  * Arguments -
3102  *      adapter         - A pointer to our adapter structure
3103  *
3104  * Return
3105  *      Link State
3106  */
3107 static enum SXG_LINK_STATE sxg_get_link_state(struct adapter_t *adapter)
3108 {
3109         int status;
3110         u32 Value;
3111
3112         DBG_ERROR("ENTER %s\n", __func__);
3113
3114         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "GetLink",
3115                   adapter, 0, 0, 0);
3116
3117         /*
3118          * Per the Xenpak spec (and the IEEE 10Gb spec?), the link is up if
3119          * the following 3 bits (from 3 different MDIO registers) are all true.
3120          */
3121
3122         /* MIIM_DEV_PHY_PMA -  PHY PMA/PMD module */
3123         status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA,
3124                                 /* PMA/PMD Receive Signal Detect register */
3125                                    PHY_PMA_RCV_DET,
3126                                    &Value);
3127         if (status != STATUS_SUCCESS)
3128                 goto bad;
3129
3130         /* If PMA/PMD receive signal detect is 0, then the link is down */
3131         if (!(Value & PMA_RCV_DETECT))
3132                 return (SXG_LINK_DOWN);
3133
3134         /* MIIM_DEV_PHY_PCS - PHY PCS module */
3135         status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PCS,
3136                                 /* PCS 10GBASE-R Status 1 register */
3137                                    PHY_PCS_10G_STATUS1,
3138                                    &Value);
3139         if (status != STATUS_SUCCESS)
3140                 goto bad;
3141
3142         /* If PCS is not locked to receive blocks, then the link is down */
3143         if (!(Value & PCS_10B_BLOCK_LOCK))
3144                 return (SXG_LINK_DOWN);
3145
3146         status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_XS,/* PHY XS module */
3147                                 /* XS Lane Status register */
3148                                    PHY_XS_LANE_STATUS,
3149                                    &Value);
3150         if (status != STATUS_SUCCESS)
3151                 goto bad;
3152
3153         /* If XS transmit lanes are not aligned, then the link is down */
3154         if (!(Value & XS_LANE_ALIGN))
3155                 return (SXG_LINK_DOWN);
3156
3157         /* All 3 bits are true, so the link is up */
3158         DBG_ERROR("EXIT %s\n", __func__);
3159
3160         return (SXG_LINK_UP);
3161
3162       bad:
3163         /* An error occurred reading an MDIO register. This shouldn't happen. */
3164         DBG_ERROR("Error reading an MDIO register!\n");
3165         ASSERT(0);
3166         return (SXG_LINK_DOWN);
3167 }
3168
3169 static void sxg_indicate_link_state(struct adapter_t *adapter,
3170                                     enum SXG_LINK_STATE LinkState)
3171 {
3172         if (adapter->LinkState == SXG_LINK_UP) {
3173                 DBG_ERROR("%s: LINK now UP, call netif_start_queue\n",
3174                           __func__);
3175                 netif_start_queue(adapter->netdev);
3176         } else {
3177                 DBG_ERROR("%s: LINK now DOWN, call netif_stop_queue\n",
3178                           __func__);
3179                 netif_stop_queue(adapter->netdev);
3180         }
3181 }
3182
3183 /*
3184  * sxg_change_mtu - Change the Maximum Transfer Unit
3185  *  * @returns 0 on success, negative on failure
3186  */
3187 int sxg_change_mtu (struct net_device *netdev, int new_mtu)
3188 {
3189         struct adapter_t *adapter = (struct adapter_t *) netdev_priv(netdev);
3190
3191         if (!((new_mtu == SXG_DEFAULT_MTU) || (new_mtu == SXG_JUMBO_MTU)))
3192                 return -EINVAL;
3193
3194         if(new_mtu == netdev->mtu)
3195                 return 0;
3196
3197         netdev->mtu = new_mtu;
3198
3199         if (new_mtu == SXG_JUMBO_MTU) {
3200                 adapter->JumboEnabled = TRUE;
3201                 adapter->FrameSize = JUMBOMAXFRAME;
3202                 adapter->ReceiveBufferSize = SXG_RCV_JUMBO_BUFFER_SIZE;
3203         } else {
3204                 adapter->JumboEnabled = FALSE;
3205                 adapter->FrameSize = ETHERMAXFRAME;
3206                 adapter->ReceiveBufferSize = SXG_RCV_DATA_BUFFER_SIZE;
3207         }
3208
3209         sxg_entry_halt(netdev);
3210         sxg_entry_open(netdev);
3211         return 0;
3212 }
3213
3214 /*
3215  * sxg_link_state - Set the link state and if necessary, indicate.
3216  *      This routine the central point of processing for all link state changes.
3217  *      Nothing else in the driver should alter the link state or perform
3218  *      link state indications
3219  *
3220  * Arguments -
3221  *      adapter         - A pointer to our adapter structure
3222  *      LinkState       - The link state
3223  *
3224  * Return
3225  *      None
3226  */
3227 static void sxg_link_state(struct adapter_t *adapter,
3228                                 enum SXG_LINK_STATE LinkState)
3229 {
3230         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "LnkINDCT",
3231                   adapter, LinkState, adapter->LinkState, adapter->State);
3232
3233         DBG_ERROR("ENTER %s\n", __func__);
3234
3235         /*
3236          * Hold the adapter lock during this routine.  Maybe move
3237          * the lock to the caller.
3238          */
3239         /* IMP TODO : Check if we can survive without taking this lock */
3240 //      spin_lock(&adapter->AdapterLock);
3241         if (LinkState == adapter->LinkState) {
3242                 /* Nothing changed.. */
3243 //              spin_unlock(&adapter->AdapterLock);
3244                 DBG_ERROR("EXIT #0 %s. Link status = %d\n",
3245                                          __func__, LinkState);
3246                 return;
3247         }
3248         /* Save the adapter state */
3249         adapter->LinkState = LinkState;
3250
3251         /* Drop the lock and indicate link state */
3252 //      spin_unlock(&adapter->AdapterLock);
3253         DBG_ERROR("EXIT #1 %s\n", __func__);
3254
3255         sxg_indicate_link_state(adapter, LinkState);
3256 }
3257
3258 /*
3259  * sxg_write_mdio_reg - Write to a register on the MDIO bus
3260  *
3261  * Arguments -
3262  *      adapter         - A pointer to our adapter structure
3263  *  DevAddr     - MDIO device number being addressed
3264  *  RegAddr     - register address for the specified MDIO device
3265  *  Value               - value to write to the MDIO register
3266  *
3267  * Return
3268  *      status
3269  */
3270 static int sxg_write_mdio_reg(struct adapter_t *adapter,
3271                               u32 DevAddr, u32 RegAddr, u32 Value)
3272 {
3273         struct sxg_hw_regs *HwRegs = adapter->HwRegs;
3274         /* Address operation (written to MIIM field reg) */
3275         u32 AddrOp;
3276         /* Write operation (written to MIIM field reg) */
3277         u32 WriteOp;
3278         u32 Cmd;/* Command (written to MIIM command reg) */
3279         u32 ValueRead;
3280         u32 Timeout;
3281
3282         /* DBG_ERROR("ENTER %s\n", __func__); */
3283
3284         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "WrtMDIO",
3285                   adapter, 0, 0, 0);
3286
3287         /* Ensure values don't exceed field width */
3288         DevAddr &= 0x001F;      /* 5-bit field */
3289         RegAddr &= 0xFFFF;      /* 16-bit field */
3290         Value &= 0xFFFF;        /* 16-bit field */
3291
3292         /* Set MIIM field register bits for an MIIM address operation */
3293         AddrOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
3294             (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
3295             (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
3296             (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) | RegAddr;
3297
3298         /* Set MIIM field register bits for an MIIM write operation */
3299         WriteOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
3300             (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
3301             (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
3302             (MIIM_OP_WRITE << AXGMAC_AMIIM_FIELD_OP_SHIFT) | Value;
3303
3304         /* Set MIIM command register bits to execute an MIIM command */
3305         Cmd = AXGMAC_AMIIM_CMD_START | AXGMAC_AMIIM_CMD_10G_OPERATION;
3306
3307         /* Reset the command register command bit (in case it's not 0) */
3308         WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
3309
3310         /* MIIM write to set the address of the specified MDIO register */
3311         WRITE_REG(HwRegs->MacAmiimField, AddrOp, TRUE);
3312
3313         /* Write to MIIM Command Register to execute to address operation */
3314         WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
3315
3316         /* Poll AMIIM Indicator register to wait for completion */
3317         Timeout = SXG_LINK_TIMEOUT;
3318         do {
3319                 udelay(100);    /* Timeout in 100us units */
3320                 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
3321                 if (--Timeout == 0) {
3322                         return (STATUS_FAILURE);
3323                 }
3324         } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
3325
3326         /* Reset the command register command bit */
3327         WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
3328
3329         /* MIIM write to set up an MDIO write operation */
3330         WRITE_REG(HwRegs->MacAmiimField, WriteOp, TRUE);
3331
3332         /* Write to MIIM Command Register to execute the write operation */
3333         WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
3334
3335         /* Poll AMIIM Indicator register to wait for completion */
3336         Timeout = SXG_LINK_TIMEOUT;
3337         do {
3338                 udelay(100);    /* Timeout in 100us units */
3339                 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
3340                 if (--Timeout == 0) {
3341                         return (STATUS_FAILURE);
3342                 }
3343         } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
3344
3345         /* DBG_ERROR("EXIT %s\n", __func__); */
3346
3347         return (STATUS_SUCCESS);
3348 }
3349
3350 /*
3351  * sxg_read_mdio_reg - Read a register on the MDIO bus
3352  *
3353  * Arguments -
3354  *      adapter         - A pointer to our adapter structure
3355  *  DevAddr     - MDIO device number being addressed
3356  *  RegAddr     - register address for the specified MDIO device
3357  *  pValue      - pointer to where to put data read from the MDIO register
3358  *
3359  * Return
3360  *      status
3361  */
3362 static int sxg_read_mdio_reg(struct adapter_t *adapter,
3363                              u32 DevAddr, u32 RegAddr, u32 *pValue)
3364 {
3365         struct sxg_hw_regs *HwRegs = adapter->HwRegs;
3366         u32 AddrOp;     /* Address operation (written to MIIM field reg) */
3367         u32 ReadOp;     /* Read operation (written to MIIM field reg) */
3368         u32 Cmd;        /* Command (written to MIIM command reg) */
3369         u32 ValueRead;
3370         u32 Timeout;
3371
3372         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "WrtMDIO",
3373                   adapter, 0, 0, 0);
3374         DBG_ERROR("ENTER %s\n", __FUNCTION__);
3375
3376         /* Ensure values don't exceed field width */
3377         DevAddr &= 0x001F;      /* 5-bit field */
3378         RegAddr &= 0xFFFF;      /* 16-bit field */
3379
3380         /* Set MIIM field register bits for an MIIM address operation */
3381         AddrOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
3382             (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
3383             (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
3384             (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) | RegAddr;
3385
3386         /* Set MIIM field register bits for an MIIM read operation */
3387         ReadOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
3388             (DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
3389             (MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
3390             (MIIM_OP_READ << AXGMAC_AMIIM_FIELD_OP_SHIFT);
3391
3392         /* Set MIIM command register bits to execute an MIIM command */
3393         Cmd = AXGMAC_AMIIM_CMD_START | AXGMAC_AMIIM_CMD_10G_OPERATION;
3394
3395         /* Reset the command register command bit (in case it's not 0) */
3396         WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
3397
3398         /* MIIM write to set the address of the specified MDIO register */
3399         WRITE_REG(HwRegs->MacAmiimField, AddrOp, TRUE);
3400
3401         /* Write to MIIM Command Register to execute to address operation */
3402         WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
3403
3404         /* Poll AMIIM Indicator register to wait for completion */
3405         Timeout = SXG_LINK_TIMEOUT;
3406         do {
3407                 udelay(100);    /* Timeout in 100us units */
3408                 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
3409                 if (--Timeout == 0) {
3410             DBG_ERROR("EXIT %s with STATUS_FAILURE 1\n", __FUNCTION__);
3411
3412                         return (STATUS_FAILURE);
3413                 }
3414         } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
3415
3416         /* Reset the command register command bit */
3417         WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
3418
3419         /* MIIM write to set up an MDIO register read operation */
3420         WRITE_REG(HwRegs->MacAmiimField, ReadOp, TRUE);
3421
3422         /* Write to MIIM Command Register to execute the read operation */
3423         WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
3424
3425         /* Poll AMIIM Indicator register to wait for completion */
3426         Timeout = SXG_LINK_TIMEOUT;
3427         do {
3428                 udelay(100);    /* Timeout in 100us units */
3429                 READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
3430                 if (--Timeout == 0) {
3431             DBG_ERROR("EXIT %s with STATUS_FAILURE 2\n", __FUNCTION__);
3432
3433                         return (STATUS_FAILURE);
3434                 }
3435         } while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
3436
3437         /* Read the MDIO register data back from the field register */
3438         READ_REG(HwRegs->MacAmiimField, *pValue);
3439         *pValue &= 0xFFFF;      /* data is in the lower 16 bits */
3440
3441         DBG_ERROR("EXIT %s\n", __FUNCTION__);
3442
3443         return (STATUS_SUCCESS);
3444 }
3445
3446 /*
3447  * Functions to obtain the CRC corresponding to the destination mac address.
3448  * This is a standard ethernet CRC in that it is a 32-bit, reflected CRC using
3449  * the polynomial:
3450  *   x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5
3451  *    + x^4 + x^2 + x^1.
3452  *
3453  * After the CRC for the 6 bytes is generated (but before the value is
3454  * complemented), we must then transpose the value and return bits 30-23.
3455  */
3456 static u32 sxg_crc_table[256];/* Table of CRC's for all possible byte values */
3457 static u32 sxg_crc_init;        /* Is table initialized */
3458
3459 /* Contruct the CRC32 table */
3460 static void sxg_mcast_init_crc32(void)
3461 {
3462         u32 c;                  /*  CRC shit reg */
3463         u32 e = 0;              /*  Poly X-or pattern */
3464         int i;                  /*  counter */
3465         int k;                  /*  byte being shifted into crc  */
3466
3467         static int p[] = { 0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26 };
3468
3469         for (i = 0; i < sizeof(p) / sizeof(int); i++) {
3470                 e |= 1L << (31 - p[i]);
3471         }
3472
3473         for (i = 1; i < 256; i++) {
3474                 c = i;
3475                 for (k = 8; k; k--) {
3476                         c = c & 1 ? (c >> 1) ^ e : c >> 1;
3477                 }
3478                 sxg_crc_table[i] = c;
3479         }
3480 }
3481
3482 /*
3483  *  Return the MAC hast as described above.
3484  */
3485 static unsigned char sxg_mcast_get_mac_hash(char *macaddr)
3486 {
3487         u32 crc;
3488         char *p;
3489         int i;
3490         unsigned char machash = 0;
3491
3492         if (!sxg_crc_init) {
3493                 sxg_mcast_init_crc32();
3494                 sxg_crc_init = 1;
3495         }
3496
3497         crc = 0xFFFFFFFF;       /* Preload shift register, per crc-32 spec */
3498         for (i = 0, p = macaddr; i < 6; ++p, ++i) {
3499                 crc = (crc >> 8) ^ sxg_crc_table[(crc ^ *p) & 0xFF];
3500         }
3501
3502         /* Return bits 1-8, transposed */
3503         for (i = 1; i < 9; i++) {
3504                 machash |= (((crc >> i) & 1) << (8 - i));
3505         }
3506
3507         return (machash);
3508 }
3509
3510 static void sxg_mcast_set_mask(struct adapter_t *adapter)
3511 {
3512         struct sxg_ucode_regs *sxg_regs = adapter->UcodeRegs;
3513
3514         DBG_ERROR("%s ENTER (%s) MacFilter[%x] mask[%llx]\n", __FUNCTION__,
3515                   adapter->netdev->name, (unsigned int)adapter->MacFilter,
3516                   adapter->MulticastMask);
3517
3518         if (adapter->MacFilter & (MAC_ALLMCAST | MAC_PROMISC)) {
3519                 /*
3520                  * Turn on all multicast addresses. We have to do this for
3521                  * promiscuous mode as well as ALLMCAST mode.  It saves the
3522                  * Microcode from having keep state about the MAC configuration
3523                  */
3524                 /* DBG_ERROR("sxg: %s MacFilter = MAC_ALLMCAST | MAC_PROMISC\n \
3525                  *                              SLUT MODE!!!\n",__func__);
3526                  */
3527                 WRITE_REG(sxg_regs->McastLow, 0xFFFFFFFF, FLUSH);
3528                 WRITE_REG(sxg_regs->McastHigh, 0xFFFFFFFF, FLUSH);
3529                 /* DBG_ERROR("%s (%s) WRITE to slic_regs slic_mcastlow&high \
3530                  * 0xFFFFFFFF\n",__func__, adapter->netdev->name);
3531                  */
3532
3533         } else {
3534                 /*
3535                  * Commit our multicast mast to the SLIC by writing to the
3536                  * multicast address mask registers
3537                  */
3538                 DBG_ERROR("%s (%s) WRITE mcastlow[%lx] mcasthigh[%lx]\n",
3539                           __func__, adapter->netdev->name,
3540                           ((ulong) (adapter->MulticastMask & 0xFFFFFFFF)),
3541                           ((ulong)
3542                            ((adapter->MulticastMask >> 32) & 0xFFFFFFFF)));
3543
3544                 WRITE_REG(sxg_regs->McastLow,
3545                           (u32) (adapter->MulticastMask & 0xFFFFFFFF), FLUSH);
3546                 WRITE_REG(sxg_regs->McastHigh,
3547                           (u32) ((adapter->
3548                                   MulticastMask >> 32) & 0xFFFFFFFF), FLUSH);
3549         }
3550 }
3551
3552 static void sxg_mcast_set_bit(struct adapter_t *adapter, char *address)
3553 {
3554         unsigned char crcpoly;
3555
3556         /* Get the CRC polynomial for the mac address */
3557         crcpoly = sxg_mcast_get_mac_hash(address);
3558
3559         /*
3560          * We only have space on the SLIC for 64 entries.  Lop
3561          * off the top two bits. (2^6 = 64)
3562          */
3563         crcpoly &= 0x3F;
3564
3565         /* OR in the new bit into our 64 bit mask. */
3566         adapter->MulticastMask |= (u64) 1 << crcpoly;
3567 }
3568
3569 /*
3570  *   Function takes MAC addresses from dev_mc_list and generates the Mask
3571  */
3572
3573 static void sxg_set_mcast_addr(struct adapter_t *adapter)
3574 {
3575         struct dev_mc_list *mclist;
3576         struct net_device *dev = adapter->netdev;
3577         int i;
3578
3579         if (adapter->MacFilter & (MAC_ALLMCAST | MAC_MCAST)) {
3580                for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
3581                              i++, mclist = mclist->next) {
3582                         sxg_mcast_set_bit(adapter,mclist->da_addr);
3583                 }
3584         }
3585         sxg_mcast_set_mask(adapter);
3586 }
3587
3588 static void sxg_mcast_set_list(struct net_device *dev)
3589 {
3590         struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
3591
3592         ASSERT(adapter);
3593         if (dev->flags & IFF_PROMISC)
3594                 adapter->MacFilter |= MAC_PROMISC;
3595         if (dev->flags & IFF_MULTICAST)
3596                 adapter->MacFilter |= MAC_MCAST;
3597         if (dev->flags & IFF_ALLMULTI)
3598                 adapter->MacFilter |= MAC_ALLMCAST;
3599
3600         //XXX handle other flags as well
3601         sxg_set_mcast_addr(adapter);
3602 }
3603
3604 void sxg_free_sgl_buffers(struct adapter_t *adapter)
3605 {
3606         struct list_entry               *ple;
3607         struct sxg_scatter_gather       *Sgl;
3608
3609         while(!(IsListEmpty(&adapter->AllSglBuffers))) {
3610                 ple = RemoveHeadList(&adapter->AllSglBuffers);
3611                 Sgl = container_of(ple, struct sxg_scatter_gather, AllList);
3612                 kfree(Sgl);
3613                 adapter->AllSglBufferCount--;
3614         }
3615 }
3616
3617 void sxg_free_rcvblocks(struct adapter_t *adapter)
3618 {
3619         u32                             i;
3620         void                            *temp_RcvBlock;
3621         struct list_entry               *ple;
3622         struct sxg_rcv_block_hdr        *RcvBlockHdr;
3623         struct sxg_rcv_data_buffer_hdr  *RcvDataBufferHdr;
3624         ASSERT((adapter->state == SXG_STATE_INITIALIZING) ||
3625                     (adapter->state == SXG_STATE_HALTING));
3626         while(!(IsListEmpty(&adapter->AllRcvBlocks))) {
3627
3628                  ple = RemoveHeadList(&adapter->AllRcvBlocks);
3629                  RcvBlockHdr = container_of(ple, struct sxg_rcv_block_hdr, AllList);
3630
3631                 if(RcvBlockHdr->VirtualAddress) {
3632                         temp_RcvBlock = RcvBlockHdr->VirtualAddress;
3633
3634                         for(i=0; i< SXG_RCV_DESCRIPTORS_PER_BLOCK;
3635                              i++, temp_RcvBlock += SXG_RCV_DATA_HDR_SIZE) {
3636                                 RcvDataBufferHdr =
3637                                         (struct sxg_rcv_data_buffer_hdr *)temp_RcvBlock;
3638                                 SXG_FREE_RCV_PACKET(RcvDataBufferHdr);
3639                         }
3640                 }
3641
3642                 pci_free_consistent(adapter->pcidev,
3643                                          SXG_RCV_BLOCK_SIZE(SXG_RCV_DATA_HDR_SIZE),
3644                                          RcvBlockHdr->VirtualAddress,
3645                                          RcvBlockHdr->PhysicalAddress);
3646                 adapter->AllRcvBlockCount--;
3647         }
3648         ASSERT(adapter->AllRcvBlockCount == 0);
3649         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFrRBlk",
3650                         adapter, 0, 0, 0);
3651 }
3652 void sxg_free_mcast_addrs(struct adapter_t *adapter)
3653 {
3654         struct sxg_multicast_address    *address;
3655         while(adapter->MulticastAddrs) {
3656                 address = adapter->MulticastAddrs;
3657                 adapter->MulticastAddrs = address->Next;
3658                 kfree(address);
3659          }
3660
3661         adapter->MulticastMask= 0;
3662 }
3663
3664 void sxg_unmap_resources(struct adapter_t *adapter)
3665 {
3666         if(adapter->HwRegs) {
3667                 iounmap((void *)adapter->HwRegs);
3668          }
3669         if(adapter->UcodeRegs) {
3670                 iounmap((void *)adapter->UcodeRegs);
3671         }
3672
3673         ASSERT(adapter->AllRcvBlockCount == 0);
3674         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFrRBlk",
3675                            adapter, 0, 0, 0);
3676 }
3677
3678
3679
3680 /*
3681  * sxg_free_resources - Free everything allocated in SxgAllocateResources
3682  *
3683  * Arguments -
3684  *      adapter         - A pointer to our adapter structure
3685  *
3686  * Return
3687  *      none
3688  */
3689 void sxg_free_resources(struct adapter_t *adapter)
3690 {
3691         u32 RssIds, IsrCount;
3692         RssIds = SXG_RSS_CPU_COUNT(adapter);
3693         IsrCount = adapter->msi_enabled ? RssIds : 1;
3694
3695         if (adapter->BasicAllocations == FALSE) {
3696                 /*
3697                  * No allocations have been made, including spinlocks,
3698                  * or listhead initializations.  Return.
3699                  */
3700                 return;
3701         }
3702
3703         if (!(IsListEmpty(&adapter->AllRcvBlocks))) {
3704                 sxg_free_rcvblocks(adapter);
3705         }
3706         if (!(IsListEmpty(&adapter->AllSglBuffers))) {
3707                 sxg_free_sgl_buffers(adapter);
3708         }
3709
3710         if (adapter->XmtRingZeroIndex) {
3711                 pci_free_consistent(adapter->pcidev,
3712                                     sizeof(u32),
3713                                     adapter->XmtRingZeroIndex,
3714                                     adapter->PXmtRingZeroIndex);
3715         }
3716         if (adapter->Isr) {
3717                 pci_free_consistent(adapter->pcidev,
3718                                     sizeof(u32) * IsrCount,
3719                                     adapter->Isr, adapter->PIsr);
3720         }
3721
3722         if (adapter->EventRings) {
3723                 pci_free_consistent(adapter->pcidev,
3724                                     sizeof(struct sxg_event_ring) * RssIds,
3725                                     adapter->EventRings, adapter->PEventRings);
3726         }
3727         if (adapter->RcvRings) {
3728                 pci_free_consistent(adapter->pcidev,
3729                                    sizeof(struct sxg_rcv_ring) * 1,
3730                                    adapter->RcvRings,
3731                                    adapter->PRcvRings);
3732                 adapter->RcvRings = NULL;
3733         }
3734
3735         if(adapter->XmtRings) {
3736                 pci_free_consistent(adapter->pcidev,
3737                                             sizeof(struct sxg_xmt_ring) * 1,
3738                                             adapter->XmtRings,
3739                                             adapter->PXmtRings);
3740                         adapter->XmtRings = NULL;
3741         }
3742
3743         if (adapter->ucode_stats) {
3744                 pci_unmap_single(adapter->pcidev,
3745                                 sizeof(struct sxg_ucode_stats),
3746                                  adapter->pucode_stats, PCI_DMA_FROMDEVICE);
3747                 adapter->ucode_stats = NULL;
3748         }
3749
3750
3751         /* Unmap register spaces */
3752         sxg_unmap_resources(adapter);
3753
3754         sxg_free_mcast_addrs(adapter);
3755
3756         adapter->BasicAllocations = FALSE;
3757
3758 }
3759
3760 /*
3761  * sxg_allocate_complete -
3762  *
3763  * This routine is called when a memory allocation has completed.
3764  *
3765  * Arguments -
3766  *      struct adapter_t *      - Our adapter structure
3767  *      VirtualAddress  - Memory virtual address
3768  *      PhysicalAddress - Memory physical address
3769  *      Length          - Length of memory allocated (or 0)
3770  *      Context         - The type of buffer allocated
3771  *
3772  * Return
3773  *      None.
3774  */
3775 static int sxg_allocate_complete(struct adapter_t *adapter,
3776                                   void *VirtualAddress,
3777                                   dma_addr_t PhysicalAddress,
3778                                   u32 Length, enum sxg_buffer_type Context)
3779 {
3780         int status = 0;
3781         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocCmp",
3782                   adapter, VirtualAddress, Length, Context);
3783         ASSERT(atomic_read(&adapter->pending_allocations));
3784         atomic_dec(&adapter->pending_allocations);
3785
3786         switch (Context) {
3787
3788         case SXG_BUFFER_TYPE_RCV:
3789                 status = sxg_allocate_rcvblock_complete(adapter,
3790                                                VirtualAddress,
3791                                                PhysicalAddress, Length);
3792                 break;
3793         case SXG_BUFFER_TYPE_SGL:
3794                 sxg_allocate_sgl_buffer_complete(adapter, (struct sxg_scatter_gather *)
3795                                                  VirtualAddress,
3796                                                  PhysicalAddress, Length);
3797                 break;
3798         }
3799         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlocCmp",
3800                   adapter, VirtualAddress, Length, Context);
3801
3802         return status;
3803 }
3804
3805 /*
3806  * sxg_allocate_buffer_memory - Shared memory allocation routine used for
3807  *              synchronous and asynchronous buffer allocations
3808  *
3809  * Arguments -
3810  *      adapter         - A pointer to our adapter structure
3811  *      Size            - block size to allocate
3812  *      BufferType      - Type of buffer to allocate
3813  *
3814  * Return
3815  *      int
3816  */
3817 static int sxg_allocate_buffer_memory(struct adapter_t *adapter,
3818                                       u32 Size, enum sxg_buffer_type BufferType)
3819 {
3820         int status;
3821         void *Buffer;
3822         dma_addr_t pBuffer;
3823
3824         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocMem",
3825                   adapter, Size, BufferType, 0);
3826         /*
3827          * Grab the adapter lock and check the state. If we're in anything other
3828          * than INITIALIZING or RUNNING state, fail.  This is to prevent
3829          * allocations in an improper driver state
3830          */
3831
3832         atomic_inc(&adapter->pending_allocations);
3833
3834         if(BufferType != SXG_BUFFER_TYPE_SGL)
3835                 Buffer = pci_alloc_consistent(adapter->pcidev, Size, &pBuffer);
3836         else {
3837                 Buffer = kzalloc(Size, GFP_ATOMIC);
3838                 pBuffer = (dma_addr_t)NULL;
3839         }
3840         if (Buffer == NULL) {
3841                 /*
3842                  * Decrement the AllocationsPending count while holding
3843                  * the lock.  Pause processing relies on this
3844                  */
3845                 atomic_dec(&adapter->pending_allocations);
3846                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlcMemF1",
3847                           adapter, Size, BufferType, 0);
3848                 return (STATUS_RESOURCES);
3849         }
3850         status = sxg_allocate_complete(adapter, Buffer, pBuffer, Size, BufferType);
3851
3852         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlocMem",
3853                   adapter, Size, BufferType, status);
3854         return status;
3855 }
3856
3857 /*
3858  * sxg_allocate_rcvblock_complete - Complete a receive descriptor
3859  *                                      block allocation
3860  *
3861  * Arguments -
3862  *      adapter                         - A pointer to our adapter structure
3863  *      RcvBlock                        - receive block virtual address
3864  *      PhysicalAddress         - Physical address
3865  *      Length                          - Memory length
3866  *
3867  * Return
3868  */
3869 static int sxg_allocate_rcvblock_complete(struct adapter_t *adapter,
3870                                            void *RcvBlock,
3871                                            dma_addr_t PhysicalAddress,
3872                                            u32 Length)
3873 {
3874         u32 i;
3875         u32 BufferSize = adapter->ReceiveBufferSize;
3876         u64 Paddr;
3877         void *temp_RcvBlock;
3878         struct sxg_rcv_block_hdr *RcvBlockHdr;
3879         struct sxg_rcv_data_buffer_hdr *RcvDataBufferHdr;
3880         struct sxg_rcv_descriptor_block *RcvDescriptorBlock;
3881         struct sxg_rcv_descriptor_block_hdr *RcvDescriptorBlockHdr;
3882
3883         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlRcvBlk",
3884                   adapter, RcvBlock, Length, 0);
3885         if (RcvBlock == NULL) {
3886                 goto fail;
3887         }
3888         memset(RcvBlock, 0, Length);
3889         ASSERT((BufferSize == SXG_RCV_DATA_BUFFER_SIZE) ||
3890                (BufferSize == SXG_RCV_JUMBO_BUFFER_SIZE));
3891         ASSERT(Length == SXG_RCV_BLOCK_SIZE(SXG_RCV_DATA_HDR_SIZE));
3892         /*
3893          * First, initialize the contained pool of receive data buffers.
3894          * This initialization requires NBL/NB/MDL allocations, if any of them
3895          * fail, free the block and return without queueing the shared memory
3896          */
3897         //RcvDataBuffer = RcvBlock;
3898         temp_RcvBlock = RcvBlock;
3899         for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
3900                  i++, temp_RcvBlock += SXG_RCV_DATA_HDR_SIZE) {
3901                 RcvDataBufferHdr = (struct sxg_rcv_data_buffer_hdr *)
3902                                         temp_RcvBlock;
3903                 /* For FREE macro assertion */
3904                 RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM;
3905                 SXG_ALLOCATE_RCV_PACKET(adapter, RcvDataBufferHdr, BufferSize);
3906                 if (RcvDataBufferHdr->SxgDumbRcvPacket == NULL)
3907                         goto fail;
3908
3909         }
3910
3911         /*
3912          * Place this entire block of memory on the AllRcvBlocks queue so it
3913          * can be free later
3914          */
3915
3916         RcvBlockHdr = (struct sxg_rcv_block_hdr *) ((unsigned char *)RcvBlock +
3917                         SXG_RCV_BLOCK_HDR_OFFSET(SXG_RCV_DATA_HDR_SIZE));
3918         RcvBlockHdr->VirtualAddress = RcvBlock;
3919         RcvBlockHdr->PhysicalAddress = PhysicalAddress;
3920         spin_lock(&adapter->RcvQLock);
3921         adapter->AllRcvBlockCount++;
3922         InsertTailList(&adapter->AllRcvBlocks, &RcvBlockHdr->AllList);
3923         spin_unlock(&adapter->RcvQLock);
3924
3925         /* Now free the contained receive data buffers that we
3926          * initialized above */
3927         temp_RcvBlock = RcvBlock;
3928         for (i = 0, Paddr = PhysicalAddress;
3929              i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
3930              i++, Paddr += SXG_RCV_DATA_HDR_SIZE,
3931              temp_RcvBlock += SXG_RCV_DATA_HDR_SIZE) {
3932                 RcvDataBufferHdr =
3933                         (struct sxg_rcv_data_buffer_hdr *)temp_RcvBlock;
3934                 spin_lock(&adapter->RcvQLock);
3935                 SXG_FREE_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
3936                 spin_unlock(&adapter->RcvQLock);
3937         }
3938
3939         /* Locate the descriptor block and put it on a separate free queue */
3940         RcvDescriptorBlock =
3941             (struct sxg_rcv_descriptor_block *) ((unsigned char *)RcvBlock +
3942                                          SXG_RCV_DESCRIPTOR_BLOCK_OFFSET
3943                                          (SXG_RCV_DATA_HDR_SIZE));
3944         RcvDescriptorBlockHdr =
3945             (struct sxg_rcv_descriptor_block_hdr *) ((unsigned char *)RcvBlock +
3946                                              SXG_RCV_DESCRIPTOR_BLOCK_HDR_OFFSET
3947                                              (SXG_RCV_DATA_HDR_SIZE));
3948         RcvDescriptorBlockHdr->VirtualAddress = RcvDescriptorBlock;
3949         RcvDescriptorBlockHdr->PhysicalAddress = Paddr;
3950         spin_lock(&adapter->RcvQLock);
3951         SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter, RcvDescriptorBlockHdr);
3952         spin_unlock(&adapter->RcvQLock);
3953         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlRBlk",
3954                   adapter, RcvBlock, Length, 0);
3955         return STATUS_SUCCESS;
3956 fail:
3957         /* Free any allocated resources */
3958         if (RcvBlock) {
3959                 temp_RcvBlock = RcvBlock;
3960                 for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
3961                      i++, temp_RcvBlock += SXG_RCV_DATA_HDR_SIZE) {
3962                         RcvDataBufferHdr =
3963                             (struct sxg_rcv_data_buffer_hdr *)temp_RcvBlock;
3964                         SXG_FREE_RCV_PACKET(RcvDataBufferHdr);
3965                 }
3966                 pci_free_consistent(adapter->pcidev,
3967                                     Length, RcvBlock, PhysicalAddress);
3968         }
3969         DBG_ERROR("%s: OUT OF RESOURCES\n", __func__);
3970         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "RcvAFail",
3971                   adapter, adapter->FreeRcvBufferCount,
3972                   adapter->FreeRcvBlockCount, adapter->AllRcvBlockCount);
3973         adapter->Stats.NoMem++;
3974         /* As allocation failed, free all previously allocated blocks..*/
3975         //sxg_free_rcvblocks(adapter);
3976
3977         return STATUS_RESOURCES;
3978 }
3979
3980 /*
3981  * sxg_allocate_sgl_buffer_complete - Complete a SGL buffer allocation
3982  *
3983  * Arguments -
3984  *      adapter                         - A pointer to our adapter structure
3985  *      SxgSgl                          - struct sxg_scatter_gather buffer
3986  *      PhysicalAddress         - Physical address
3987  *      Length                          - Memory length
3988  *
3989  * Return
3990  */
3991 static void sxg_allocate_sgl_buffer_complete(struct adapter_t *adapter,
3992                                              struct sxg_scatter_gather *SxgSgl,
3993                                              dma_addr_t PhysicalAddress,
3994                                              u32 Length)
3995 {
3996         unsigned long sgl_flags;
3997         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlSglCmp",
3998                   adapter, SxgSgl, Length, 0);
3999         spin_lock_irqsave(&adapter->SglQLock, sgl_flags);
4000         adapter->AllSglBufferCount++;
4001         /* PhysicalAddress; */
4002         SxgSgl->PhysicalAddress = PhysicalAddress;
4003         /* Initialize backpointer once */
4004         SxgSgl->adapter = adapter;
4005         InsertTailList(&adapter->AllSglBuffers, &SxgSgl->AllList);
4006         spin_unlock_irqrestore(&adapter->SglQLock, sgl_flags);
4007         SxgSgl->State = SXG_BUFFER_BUSY;
4008         SXG_FREE_SGL_BUFFER(adapter, SxgSgl, NULL);
4009         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlSgl",
4010                   adapter, SxgSgl, Length, 0);
4011 }
4012
4013
4014 static int sxg_adapter_set_hwaddr(struct adapter_t *adapter)
4015 {
4016         /*
4017          *  DBG_ERROR ("%s ENTER card->config_set[%x] port[%d] physport[%d] \
4018          *  funct#[%d]\n", __func__, card->config_set,
4019          *  adapter->port, adapter->physport, adapter->functionnumber);
4020          *
4021          *  sxg_dbg_macaddrs(adapter);
4022          */
4023         /* DBG_ERROR ("%s AFTER copying from config.macinfo into currmacaddr\n",
4024          *                      __FUNCTION__);
4025          */
4026
4027         /* sxg_dbg_macaddrs(adapter); */
4028
4029         struct net_device * dev = adapter->netdev;
4030         if(!dev)
4031         {
4032                 printk("sxg: Dev is Null\n");
4033         }
4034
4035         DBG_ERROR("%s ENTER (%s)\n", __FUNCTION__, adapter->netdev->name);
4036
4037         if (netif_running(dev)) {
4038                 return -EBUSY;
4039         }
4040         if (!adapter) {
4041                 return -EBUSY;
4042         }
4043
4044         if (!(adapter->currmacaddr[0] ||
4045               adapter->currmacaddr[1] ||
4046               adapter->currmacaddr[2] ||
4047               adapter->currmacaddr[3] ||
4048               adapter->currmacaddr[4] || adapter->currmacaddr[5])) {
4049                 memcpy(adapter->currmacaddr, adapter->macaddr, 6);
4050         }
4051         if (adapter->netdev) {
4052                 memcpy(adapter->netdev->dev_addr, adapter->currmacaddr, 6);
4053                 memcpy(adapter->netdev->perm_addr, adapter->currmacaddr, 6);
4054         }
4055         /* DBG_ERROR ("%s EXIT port %d\n", __func__, adapter->port); */
4056         sxg_dbg_macaddrs(adapter);
4057
4058         return 0;
4059 }
4060
4061 #if XXXTODO
4062 static int sxg_mac_set_address(struct net_device *dev, void *ptr)
4063 {
4064         struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
4065         struct sockaddr *addr = ptr;
4066
4067         DBG_ERROR("%s ENTER (%s)\n", __func__, adapter->netdev->name);
4068
4069         if (netif_running(dev)) {
4070                 return -EBUSY;
4071         }
4072         if (!adapter) {
4073                 return -EBUSY;
4074         }
4075         DBG_ERROR("sxg: %s (%s) curr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
4076                   __func__, adapter->netdev->name, adapter->currmacaddr[0],
4077                   adapter->currmacaddr[1], adapter->currmacaddr[2],
4078                   adapter->currmacaddr[3], adapter->currmacaddr[4],
4079                   adapter->currmacaddr[5]);
4080         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4081         memcpy(adapter->currmacaddr, addr->sa_data, dev->addr_len);
4082         DBG_ERROR("sxg: %s (%s) new %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
4083                   __func__, adapter->netdev->name, adapter->currmacaddr[0],
4084                   adapter->currmacaddr[1], adapter->currmacaddr[2],
4085                   adapter->currmacaddr[3], adapter->currmacaddr[4],
4086                   adapter->currmacaddr[5]);
4087
4088         sxg_config_set(adapter, TRUE);
4089         return 0;
4090 }
4091 #endif
4092
4093 /*
4094  * SXG DRIVER FUNCTIONS  (below)
4095  *
4096  * sxg_initialize_adapter - Initialize adapter
4097  *
4098  * Arguments -
4099  *      adapter         - A pointer to our adapter structure
4100  *
4101  * Return - int
4102  */
4103 static int sxg_initialize_adapter(struct adapter_t *adapter)
4104 {
4105         u32 RssIds, IsrCount;
4106         u32 i;
4107         int status;
4108         int sxg_rcv_ring_size = SXG_RCV_RING_SIZE;
4109
4110         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitAdpt",
4111                   adapter, 0, 0, 0);
4112
4113         RssIds = 1;             /*  XXXTODO  SXG_RSS_CPU_COUNT(adapter); */
4114         IsrCount = adapter->msi_enabled ? RssIds : 1;
4115
4116         /*
4117          * Sanity check SXG_UCODE_REGS structure definition to
4118          * make sure the length is correct
4119          */
4120         ASSERT(sizeof(struct sxg_ucode_regs) == SXG_REGISTER_SIZE_PER_CPU);
4121
4122         /* Disable interrupts */
4123         SXG_DISABLE_ALL_INTERRUPTS(adapter);
4124
4125         /* Set MTU */
4126         ASSERT((adapter->FrameSize == ETHERMAXFRAME) ||
4127                (adapter->FrameSize == JUMBOMAXFRAME));
4128         WRITE_REG(adapter->UcodeRegs[0].LinkMtu, adapter->FrameSize, TRUE);
4129
4130         /* Set event ring base address and size */
4131         WRITE_REG64(adapter,
4132                     adapter->UcodeRegs[0].EventBase, adapter->PEventRings, 0);
4133         WRITE_REG(adapter->UcodeRegs[0].EventSize, EVENT_RING_SIZE, TRUE);
4134
4135         /* Per-ISR initialization */
4136         for (i = 0; i < IsrCount; i++) {
4137                 u64 Addr;
4138                 /* Set interrupt status pointer */
4139                 Addr = adapter->PIsr + (i * sizeof(u32));
4140                 WRITE_REG64(adapter, adapter->UcodeRegs[i].Isp, Addr, i);
4141         }
4142
4143         /* XMT ring zero index */
4144         WRITE_REG64(adapter,
4145                     adapter->UcodeRegs[0].SPSendIndex,
4146                     adapter->PXmtRingZeroIndex, 0);
4147
4148         /* Per-RSS initialization */
4149         for (i = 0; i < RssIds; i++) {
4150                 /* Release all event ring entries to the Microcode */
4151                 WRITE_REG(adapter->UcodeRegs[i].EventRelease, EVENT_RING_SIZE,
4152                           TRUE);
4153         }
4154
4155         /* Transmit ring base and size */
4156         WRITE_REG64(adapter,
4157                     adapter->UcodeRegs[0].XmtBase, adapter->PXmtRings, 0);
4158         WRITE_REG(adapter->UcodeRegs[0].XmtSize, SXG_XMT_RING_SIZE, TRUE);
4159
4160         /* Receive ring base and size */
4161         WRITE_REG64(adapter,
4162                     adapter->UcodeRegs[0].RcvBase, adapter->PRcvRings, 0);
4163         if (adapter->JumboEnabled == TRUE)
4164                 sxg_rcv_ring_size = SXG_JUMBO_RCV_RING_SIZE;
4165         WRITE_REG(adapter->UcodeRegs[0].RcvSize, sxg_rcv_ring_size, TRUE);
4166
4167         /* Populate the card with receive buffers */
4168         sxg_stock_rcv_buffers(adapter);
4169
4170         /*
4171          * Initialize checksum offload capabilities.  At the moment we always
4172          * enable IP and TCP receive checksums on the card. Depending on the
4173          * checksum configuration specified by the user, we can choose to
4174          * report or ignore the checksum information provided by the card.
4175          */
4176         WRITE_REG(adapter->UcodeRegs[0].ReceiveChecksum,
4177                   SXG_RCV_TCP_CSUM_ENABLED | SXG_RCV_IP_CSUM_ENABLED, TRUE);
4178
4179         adapter->flags |= (SXG_RCV_TCP_CSUM_ENABLED | SXG_RCV_IP_CSUM_ENABLED );
4180
4181         /* Initialize the MAC, XAUI */
4182         DBG_ERROR("sxg: %s ENTER sxg_initialize_link\n", __func__);
4183         status = sxg_initialize_link(adapter);
4184         DBG_ERROR("sxg: %s EXIT sxg_initialize_link status[%x]\n", __func__,
4185                   status);
4186         if (status != STATUS_SUCCESS) {
4187                 return (status);
4188         }
4189         /*
4190          * Initialize Dead to FALSE.
4191          * SlicCheckForHang or SlicDumpThread will take it from here.
4192          */
4193         adapter->Dead = FALSE;
4194         adapter->PingOutstanding = FALSE;
4195         adapter->XmtFcEnabled = TRUE;
4196         adapter->RcvFcEnabled = TRUE;
4197
4198         adapter->State = SXG_STATE_RUNNING;
4199
4200         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XInit",
4201                   adapter, 0, 0, 0);
4202         return (STATUS_SUCCESS);
4203 }
4204
4205 /*
4206  * sxg_fill_descriptor_block - Populate a descriptor block and give it to
4207  * the card.  The caller should hold the RcvQLock
4208  *
4209  * Arguments -
4210  *      adapter         - A pointer to our adapter structure
4211  *  RcvDescriptorBlockHdr       - Descriptor block to fill
4212  *
4213  * Return
4214  *      status
4215  */
4216 static int sxg_fill_descriptor_block(struct adapter_t *adapter,
4217              struct sxg_rcv_descriptor_block_hdr *RcvDescriptorBlockHdr)
4218 {
4219         u32 i;
4220         struct sxg_ring_info *RcvRingInfo = &adapter->RcvRingZeroInfo;
4221         struct sxg_rcv_data_buffer_hdr *RcvDataBufferHdr;
4222         struct sxg_rcv_descriptor_block *RcvDescriptorBlock;
4223         struct sxg_cmd *RingDescriptorCmd;
4224         struct sxg_rcv_ring *RingZero = &adapter->RcvRings[0];
4225
4226         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "FilBlk",
4227                   adapter, adapter->RcvBuffersOnCard,
4228                   adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
4229
4230         ASSERT(RcvDescriptorBlockHdr);
4231
4232         /*
4233          * If we don't have the resources to fill the descriptor block,
4234          * return failure
4235          */
4236         if ((adapter->FreeRcvBufferCount < SXG_RCV_DESCRIPTORS_PER_BLOCK) ||
4237             SXG_RING_FULL(RcvRingInfo)) {
4238                 adapter->Stats.NoMem++;
4239                 return (STATUS_FAILURE);
4240         }
4241         /* Get a ring descriptor command */
4242         SXG_GET_CMD(RingZero,
4243                     RcvRingInfo, RingDescriptorCmd, RcvDescriptorBlockHdr);
4244         ASSERT(RingDescriptorCmd);
4245         RcvDescriptorBlockHdr->State = SXG_BUFFER_ONCARD;
4246         RcvDescriptorBlock = (struct sxg_rcv_descriptor_block *)
4247                                  RcvDescriptorBlockHdr->VirtualAddress;
4248
4249         /* Fill in the descriptor block */
4250         for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK; i++) {
4251                 SXG_GET_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
4252                 ASSERT(RcvDataBufferHdr);
4253 //              ASSERT(RcvDataBufferHdr->SxgDumbRcvPacket);
4254                 if (!RcvDataBufferHdr->SxgDumbRcvPacket) {
4255                         SXG_ALLOCATE_RCV_PACKET(adapter, RcvDataBufferHdr,
4256                                                 adapter->ReceiveBufferSize);
4257                         if(RcvDataBufferHdr->skb)
4258                                 RcvDataBufferHdr->SxgDumbRcvPacket =
4259                                                 RcvDataBufferHdr->skb;
4260                         else
4261                                 goto no_memory;
4262                 }
4263                 SXG_REINIATIALIZE_PACKET(RcvDataBufferHdr->SxgDumbRcvPacket);
4264                 RcvDataBufferHdr->State = SXG_BUFFER_ONCARD;
4265                 RcvDescriptorBlock->Descriptors[i].VirtualAddress =
4266                                             (void *)RcvDataBufferHdr;
4267
4268                 RcvDescriptorBlock->Descriptors[i].PhysicalAddress =
4269                     RcvDataBufferHdr->PhysicalAddress;
4270         }
4271         /* Add the descriptor block to receive descriptor ring 0 */
4272         RingDescriptorCmd->Sgl = RcvDescriptorBlockHdr->PhysicalAddress;
4273
4274         /*
4275          * RcvBuffersOnCard is not protected via the receive lock (see
4276          * sxg_process_event_queue) We don't want to grap a lock every time a
4277          * buffer is returned to us, so we use atomic interlocked functions
4278          * instead.
4279          */
4280         adapter->RcvBuffersOnCard += SXG_RCV_DESCRIPTORS_PER_BLOCK;
4281
4282         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DscBlk",
4283                   RcvDescriptorBlockHdr,
4284                   RingDescriptorCmd, RcvRingInfo->Head, RcvRingInfo->Tail);
4285
4286         WRITE_REG(adapter->UcodeRegs[0].RcvCmd, 1, true);
4287         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFilBlk",
4288                   adapter, adapter->RcvBuffersOnCard,
4289                   adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
4290         return (STATUS_SUCCESS);
4291 no_memory:
4292         for (; i >= 0 ; i--) {
4293                 if (RcvDescriptorBlock->Descriptors[i].VirtualAddress) {
4294                         RcvDataBufferHdr = (struct sxg_rcv_data_buffer_hdr *)
4295                                             RcvDescriptorBlock->Descriptors[i].
4296                                                                 VirtualAddress;
4297                         RcvDescriptorBlock->Descriptors[i].PhysicalAddress =
4298                                             (dma_addr_t)NULL;
4299                         RcvDescriptorBlock->Descriptors[i].VirtualAddress=NULL;
4300                 }
4301                 SXG_FREE_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
4302         }
4303         RcvDescriptorBlockHdr->State = SXG_BUFFER_FREE;
4304         SXG_RETURN_CMD(RingZero, RcvRingInfo, RingDescriptorCmd,
4305                         RcvDescriptorBlockHdr);
4306
4307         return (-ENOMEM);
4308 }
4309
4310 /*
4311  * sxg_stock_rcv_buffers - Stock the card with receive buffers
4312  *
4313  * Arguments -
4314  *      adapter         - A pointer to our adapter structure
4315  *
4316  * Return
4317  *      None
4318  */
4319 static void sxg_stock_rcv_buffers(struct adapter_t *adapter)
4320 {
4321         struct sxg_rcv_descriptor_block_hdr *RcvDescriptorBlockHdr;
4322         int sxg_rcv_data_buffers = SXG_RCV_DATA_BUFFERS;
4323         int sxg_min_rcv_data_buffers = SXG_MIN_RCV_DATA_BUFFERS;
4324
4325         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "StockBuf",
4326                   adapter, adapter->RcvBuffersOnCard,
4327                   adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
4328         /*
4329          * First, see if we've got less than our minimum threshold of
4330          * receive buffers, there isn't an allocation in progress, and
4331          * we haven't exceeded our maximum.. get another block of buffers
4332          * None of this needs to be SMP safe.  It's round numbers.
4333          */
4334         if (adapter->JumboEnabled == TRUE)
4335                 sxg_min_rcv_data_buffers = SXG_MIN_JUMBO_RCV_DATA_BUFFERS;
4336         if ((adapter->FreeRcvBufferCount < sxg_min_rcv_data_buffers) &&
4337             (adapter->AllRcvBlockCount < SXG_MAX_RCV_BLOCKS) &&
4338             (atomic_read(&adapter->pending_allocations) == 0)) {
4339                 sxg_allocate_buffer_memory(adapter,
4340                                            SXG_RCV_BLOCK_SIZE
4341                                            (SXG_RCV_DATA_HDR_SIZE),
4342                                            SXG_BUFFER_TYPE_RCV);
4343         }
4344         /* Now grab the RcvQLock lock and proceed */
4345         spin_lock(&adapter->RcvQLock);
4346         if (adapter->JumboEnabled)
4347                 sxg_rcv_data_buffers = SXG_JUMBO_RCV_DATA_BUFFERS;
4348         while (adapter->RcvBuffersOnCard < sxg_rcv_data_buffers) {
4349                 struct list_entry *_ple;
4350
4351                 /* Get a descriptor block */
4352                 RcvDescriptorBlockHdr = NULL;
4353                 if (adapter->FreeRcvBlockCount) {
4354                         _ple = RemoveHeadList(&adapter->FreeRcvBlocks);
4355                         RcvDescriptorBlockHdr =
4356                             container_of(_ple, struct sxg_rcv_descriptor_block_hdr,
4357                                          FreeList);
4358                         adapter->FreeRcvBlockCount--;
4359                         RcvDescriptorBlockHdr->State = SXG_BUFFER_BUSY;
4360                 }
4361
4362                 if (RcvDescriptorBlockHdr == NULL) {
4363                         /* Bail out.. */
4364                         adapter->Stats.NoMem++;
4365                         break;
4366                 }
4367                 /* Fill in the descriptor block and give it to the card */
4368                 if (sxg_fill_descriptor_block(adapter, RcvDescriptorBlockHdr) ==
4369                     STATUS_FAILURE) {
4370                         /* Free the descriptor block */
4371                         SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter,
4372                                                       RcvDescriptorBlockHdr);
4373                         break;
4374                 }
4375         }
4376         spin_unlock(&adapter->RcvQLock);
4377         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFilBlks",
4378                   adapter, adapter->RcvBuffersOnCard,
4379                   adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
4380 }
4381
4382 /*
4383  * sxg_complete_descriptor_blocks - Return descriptor blocks that have been
4384  * completed by the microcode
4385  *
4386  * Arguments -
4387  *      adapter         - A pointer to our adapter structure
4388  *      Index           - Where the microcode is up to
4389  *
4390  * Return
4391  *      None
4392  */
4393 static void sxg_complete_descriptor_blocks(struct adapter_t *adapter,
4394                                            unsigned char Index)
4395 {
4396         struct sxg_rcv_ring *RingZero = &adapter->RcvRings[0];
4397         struct sxg_ring_info *RcvRingInfo = &adapter->RcvRingZeroInfo;
4398         struct sxg_rcv_descriptor_block_hdr *RcvDescriptorBlockHdr;
4399         struct sxg_cmd *RingDescriptorCmd;
4400
4401         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpRBlks",
4402                   adapter, Index, RcvRingInfo->Head, RcvRingInfo->Tail);
4403
4404         /* Now grab the RcvQLock lock and proceed */
4405         spin_lock(&adapter->RcvQLock);
4406         ASSERT(Index != RcvRingInfo->Tail);
4407         while (sxg_ring_get_forward_diff(RcvRingInfo, Index,
4408                                         RcvRingInfo->Tail) > 3) {
4409                 /*
4410                  * Locate the current Cmd (ring descriptor entry), and
4411                  * associated receive descriptor block, and advance
4412                  * the tail
4413                  */
4414                 SXG_RETURN_CMD(RingZero,
4415                                RcvRingInfo,
4416                                RingDescriptorCmd, RcvDescriptorBlockHdr);
4417                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpRBlk",
4418                           RcvRingInfo->Head, RcvRingInfo->Tail,
4419                           RingDescriptorCmd, RcvDescriptorBlockHdr);
4420
4421                 /* Clear the SGL field */
4422                 RingDescriptorCmd->Sgl = 0;
4423                 /*
4424                  * Attempt to refill it and hand it right back to the
4425                  * card.  If we fail to refill it, free the descriptor block
4426                  * header.  The card will be restocked later via the
4427                  * RcvBuffersOnCard test
4428                  */
4429                 if (sxg_fill_descriptor_block(adapter,
4430                          RcvDescriptorBlockHdr) == STATUS_FAILURE)
4431                         SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter,
4432                                                       RcvDescriptorBlockHdr);
4433         }
4434         spin_unlock(&adapter->RcvQLock);
4435         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XCRBlks",
4436                   adapter, Index, RcvRingInfo->Head, RcvRingInfo->Tail);
4437 }
4438
4439 /*
4440  * Read the statistics which the card has been maintaining.
4441  */
4442 void sxg_collect_statistics(struct adapter_t *adapter)
4443 {
4444         if(adapter->ucode_stats)
4445                 WRITE_REG64(adapter, adapter->UcodeRegs[0].GetUcodeStats,
4446                                 adapter->pucode_stats, 0);
4447         adapter->stats.rx_fifo_errors = adapter->ucode_stats->ERDrops;
4448         adapter->stats.rx_over_errors = adapter->ucode_stats->NBDrops;
4449         adapter->stats.tx_fifo_errors = adapter->ucode_stats->XDrops;
4450 }
4451
4452 static struct net_device_stats *sxg_get_stats(struct net_device * dev)
4453 {
4454         struct adapter_t *adapter = netdev_priv(dev);
4455
4456         sxg_collect_statistics(adapter);
4457         return (&adapter->stats);
4458 }
4459
4460 static struct pci_driver sxg_driver = {
4461         .name = sxg_driver_name,
4462         .id_table = sxg_pci_tbl,
4463         .probe = sxg_entry_probe,
4464         .remove = sxg_entry_remove,
4465 #if SXG_POWER_MANAGEMENT_ENABLED
4466         .suspend = sxgpm_suspend,
4467         .resume = sxgpm_resume,
4468 #endif
4469         /* .shutdown   =     slic_shutdown,  MOOK_INVESTIGATE */
4470 };
4471
4472 static int __init sxg_module_init(void)
4473 {
4474         sxg_init_driver();
4475
4476         if (debug >= 0)
4477                 sxg_debug = debug;
4478
4479         return pci_register_driver(&sxg_driver);
4480 }
4481
4482 static void __exit sxg_module_cleanup(void)
4483 {
4484         pci_unregister_driver(&sxg_driver);
4485 }
4486
4487 module_init(sxg_module_init);
4488 module_exit(sxg_module_cleanup);