drivers/xilinx_common/xdmav3_l.h

   1 /* $Id: */
   2
   3 /******************************************************************************
   4 *
   5 *       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
   6 *       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
   7 *       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
   8 *       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
   9 *       APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
  10 *       THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
  11 *       AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
  12 *       FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
  13 *       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
  14 *       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
  15 *       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
  16 *       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  17 *       FOR A PARTICULAR PURPOSE.
  18 *
  19 *       (c) Copyright 2006 Xilinx Inc.
  20 *       All rights reserved.
  21 * This program is free software; you can redistribute it and/or modify it
  22 * under the terms of the GNU General Public License as published by the
  23 * Free Software Foundation; either version 2 of the License, or (at your
  24 * option) any later version.
  25 *
  26 * You should have received a copy of the GNU General Public License
  27 * along with this program; if not, write to the Free Software
  28 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  29 *
  30 ******************************************************************************/
  31
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xdmav3_l.h
  36 *
  37 * This header file contains identifiers and low-level driver functions (or
  38 * macros) that can be used to access the Direct Memory Access and Scatter
  39 * Gather (SG DMA) device.
  40 *
  41 * For more information about the operation of this device, see the hardware
  42 * specification and documentation in the higher level driver xdma.h source
  43 * code file.
  44 *
  45 * <pre>
  46 * MODIFICATION HISTORY:
  47 *
  48 * Ver   Who  Date     Changes
  49 * ----- ---- -------- -------------------------------------------------------
  50 * 3.00a rmm  03/11/06 First release
  51 *       rmm  06/22/06 Added extern "C"
  52 * </pre>
  53 *
  54 ******************************************************************************/
  55
  56 #ifndef XDMAV3_L_H              /* prevent circular inclusions */
  57 #define XDMAV3_L_H              /* by using protection macros */
  58
  59 #ifdef __cplusplus
  60 extern "C" {
  61 #endif
  62
  63 /***************************** Include Files *********************************/
  64
  65 #include "xbasic_types.h"
  66 #include "xio.h"
  67
  68 /************************** Constant Definitions *****************************/
  69
  70
  71 /* Register offset definitions. Unless otherwise noted, register access is
  72  * 32 bit.
  73  */
  74
  75 /** @name DMA channel registers
  76  *  @{
  77  */
  78 #define XDMAV3_DMASR_OFFSET  0x00000000  /**< DMA Status Register */
  79 #define XDMAV3_DMACR_OFFSET  0x00000004  /**< DMA Control Register */
  80 #define XDMAV3_MSBA_OFFSET   0x00000008  /**< Most Significant Bus Address */
  81 #define XDMAV3_LSBA_OFFSET   0x0000000C  /**< Least Significant Bus Address */
  82 #define XDMAV3_BDA_OFFSET    0x00000010  /**< Buffer Descriptor Address */
  83 #define XDMAV3_LENGTH_OFFSET 0x00000014  /**< DMA Length */
  84 #define XDMAV3_ISR_OFFSET    0x00000018  /**< Interrupt Status Register */
  85 #define XDMAV3_IER_OFFSET    0x0000001C  /**< Interrupt Enable Register */
  86 #define XDMAV3_SWCR_OFFSET   0x00000020  /**< Software Control Register */
  87 /*@}*/
  88
  89 /** @name Buffer Descriptor register offsets
  90  *  @{
  91  */
  92 #define XDMAV3_BD_DMASR_OFFSET     0x00  /**< Channel DMASR register contents */
  93 #define XDMAV3_BD_DMACR_OFFSET     0x04  /**< Channel DMACR register contents */
  94 #define XDMAV3_BD_MSBA_OFFSET      0x08  /**< Channel MSBA register contents */
  95 #define XDMAV3_BD_LSBA_OFFSET      0x0C  /**< Channel LSBA register contents */
  96 #define XDMAV3_BD_BDA_OFFSET       0x10  /**< Next buffer descriptor pointer */
  97 #define XDMAV3_BD_LENGTH_OFFSET    0x14  /**< Channel LENGTH register contents */
  98 #define XDMAV3_BD_SR_OFFSET        0x18  /**< Packet Status */
  99 #define XDMAV3_BD_RSVD_OFFSET      0x1C  /**< Reserved */
 100 #define XDMAV3_BD_USR0_OFFSET      0x20  /**< HW User defined */
 101 #define XDMAV3_BD_USR1_OFFSET      0x24  /**< HW User defined */
 102 #define XDMAV3_BD_USR2_OFFSET      0x28  /**< HW User defined */
 103 #define XDMAV3_BD_USR3_OFFSET      0x2C  /**< HW User defined */
 104 #define XDMAV3_BD_USR4_OFFSET      0x30  /**< HW User defined */
 105 #define XDMAV3_BD_USR5_OFFSET      0x34  /**< HW User defined */
 106 #define XDMAV3_BD_LENCPY_OFFSET    0x38  /**< SW Driver usage */
 107 #define XDMAV3_BD_ID_OFFSET        0x3C  /**< SW Driver usage */
 108
 109 #define XDMAV3_BD_NUM_WORDS        16    /**< Number of 32-bit words that make
 110                                               up a BD */
 111 /*@}*/
 112
 113 /* Register masks. The following constants define bit locations of various
 114  * control bits in the registers. Constants are not defined for those registers
 115  * that have a single bit field representing all 32 bits. For further
 116  * information on the meaning of the various bit masks, refer to the HW spec.
 117  */
 118
 119
 120 /** @name DMA Status Register (DMASR) bitmasks
 121  *  @note These bitmasks are identical between XDMAV3_DMASR_OFFSET and
 122  *  XDMAV3_BD_DMASR_OFFSET
 123  * @{
 124  */
 125 #define XDMAV3_DMASR_DMABSY_MASK  0x80000000  /**< DMA busy */
 126 #define XDMAV3_DMASR_DBE_MASK     0x40000000  /**< Bus error */
 127 #define XDMAV3_DMASR_DBT_MASK     0x20000000  /**< Bus timeout */
 128 #define XDMAV3_DMASR_DMADONE_MASK 0x10000000  /**< DMA done */
 129 #define XDMAV3_DMASR_SGBSY_MASK   0x08000000  /**< SG channel busy */
 130 #define XDMAV3_DMASR_LAST_MASK    0x04000000  /**< Last BD of packet */
 131 #define XDMAV3_DMASR_SGDONE_MASK  0x01000000  /**< SGDMA done */
 132 #define XDMAV3_DMASR_DMACNFG_MASK 0x00300000  /**< DMA configuration */
 133
 134 #define XDMAV3_DMASR_DMACNFG_SIMPLE_MASK  0x00000000  /**< Simple DMA config */
 135 #define XDMAV3_DMASR_DMACNFG_SSGDMA_MASK  0x00100000  /**< Simple SGDMA config */
 136 #define XDMAV3_DMASR_DMACNFG_SGDMATX_MASK 0x00200000  /**< SGDMA xmit config */
 137 #define XDMAV3_DMASR_DMACNFG_SGDMARX_MASK 0x00300000  /**< SGDMA recv config */
 138 #define XDMAV3_DMASR_DMACNFG_MASK         0x00300000  /**< Mask for all */
 139
 140 /*@}*/
 141
 142 /** @name DMA Control Register (DMACR) bitmasks
 143  *  @note These bitmasks are identical between XDMAV3_DMACR_OFFSET and
 144  *  XDMAV3_BD_DMACR_OFFSET
 145  * @{
 146  */
 147 #define XDMAV3_DMACR_AINC_MASK    0x80000000  /**< Address increment */
 148 #define XDMAV3_DMACR_BPDRE_MASK   0x20000000  /**< Bypass DRE */
 149 #define XDMAV3_DMACR_SGS_MASK     0x08000000  /**< Scatter gather stop */
 150 #define XDMAV3_DMACR_LAST_MASK    0x04000000  /**< Last BD of packet */
 151 #define XDMAV3_DMACR_DEVSEL_MASK  0x00FF0000  /**< Device select */
 152 #define XDMAV3_DMACR_BDPAGE_MASK  0x00000F00  /**< BD page address */
 153 #define XDMAV3_DMACR_TYPE_MASK    0x00000070  /**< DMA transfer type */
 154 #define XDMAV3_DMACR_DSIZE_MASK   0x00000007  /**< DMA transfer width */
 155
 156 /* Sub-fields within XDMAV3_DMACR_DIR_MASK */
 157 #define XDMAV3_DMACR_DIR_RX_MASK       0x40000000  /**< Xfer in Rx direction */
 158 #define XDMAV3_DMACR_DIR_TX_MASK       0x00000000  /**< Xfer in Tx direction */
 159
 160 /* Sub-fields within XDMAV3_DMACR_TYPE_MASK */
 161 #define XDMAV3_DMACR_TYPE_BFBURST_MASK 0x00000010  /**< Bounded fixed length
 162                                                         burst */
 163 #define XDMAV3_DMACR_TYPE_BIBURST_MASK 0x00000020  /**< Bounded indeterminate
 164                                                         burst */
 165
 166 /* Sub-fields within XDMAV3_DMACR_DSIZE_MASK */
 167 #define XDMAV3_DMACR_DSIZE_8_MASK      0x00000000  /**< Xfer width = 8 bits */
 168 #define XDMAV3_DMACR_DSIZE_16_MASK     0x00000001  /**< Xfer width = 16 bits */
 169 #define XDMAV3_DMACR_DSIZE_32_MASK     0x00000002  /**< Xfer width = 32 bits */
 170 #define XDMAV3_DMACR_DSIZE_64_MASK     0x00000003  /**< Xfer width = 64 bits */
 171 #define XDMAV3_DMACR_DSIZE_128_MASK    0x00000004  /**< Xfer width = 128 bits */
 172
 173 /* Left shift values for selected masks */
 174 #define XDMAV3_DMACR_DEVSEL_SHIFT      16
 175 #define XDMAV3_DMACR_BDPAGE_SHIFT      8
 176 /*@}*/
 177
 178 /** @name Interrupt status bits for MAC interrupts
 179  *  These bits are associated with XDMAV3_ISR_OFFSET and
 180  *  XDMAV3_IER_OFFSET registers.
 181  *  @{
 182  */
 183 #define XDMAV3_IPXR_DD_MASK      0x00000040  /**< DMA complete */
 184 #define XDMAV3_IPXR_DE_MASK      0x00000020  /**< DMA error */
 185 #define XDMAV3_IPXR_PD_MASK      0x00000010  /**< Pkt done */
 186 #define XDMAV3_IPXR_PCTR_MASK    0x00000008  /**< Pkt count threshold reached */
 187 #define XDMAV3_IPXR_PWBR_MASK    0x00000004  /**< Pkt waitbound reached */
 188 #define XDMAV3_IPXR_SGDA_MASK    0x00000002  /**< SG Disable ack */
 189 #define XDMAV3_IPXR_SGEND_MASK   0x00000001  /**< SG End */
 190 /*@}*/
 191
 192 /** @name Software control register (SWCR) bitmasks
 193  *  @{
 194  */
 195 #define XDMAV3_SWCR_SGE_MASK     0x80000000  /**< SG Enable */
 196 #define XDMAV3_SWCR_SGD_MASK     0x40000000  /**< SG Disable */
 197 #define XDMAV3_SWCR_DSGAR_MASK   0x20000000  /**< SG Disable auto-restart */
 198 #define XDMAV3_SWCR_PWB_MASK     0x00FFF000  /**< Pkt waitbound */
 199 #define XDMAV3_SWCR_PCT_MASK     0x00000FFF  /**< Pkt threshold count */
 200
 201 /* Left shift values for selected masks */
 202 #define XDMAV3_SWCR_PCT_SHIFT    0
 203 #define XDMAV3_SWCR_PWB_SHIFT    12
 204 /*@}*/
 205
 206 /**************************** Type Definitions *******************************/
 207
 208 /***************** Macros (Inline Functions) Definitions *********************/
 209
 210
 211 /****************************************************************************/
 212 /**
 213 *
 214 * Read the given IPIF register.
 215 *
 216 * @param    BaseAddress is the IPIF base address of the device
 217 * @param    RegOffset is the register offset to be read
 218 *
 219 * @return   The 32-bit value of the register
 220 *
 221 * @note
 222 * C-style signature:
 223 *    u32 XDmaV3_mReadReg(u32 BaseAddress, u32 RegOffset)
 224 *
 225 *****************************************************************************/
 226 #define XDmaV3_mReadReg(BaseAddress, RegOffset) \
 227     XIo_In32((u32)(BaseAddress) + (u32)(RegOffset))
 228
 229
 230 /****************************************************************************/
 231 /**
 232 *
 233 * Write the given IPIF register.
 234 *
 235 * @param    BaseAddress is the IPIF base address of the device
 236 * @param    RegOffset is the register offset to be written
 237 * @param    Data is the 32-bit value to write to the register
 238 *
 239 * @return   None.
 240 *
 241 * @note
 242 * C-style signature:
 243 *    void XDmaV3_mWriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
 244 *
 245 *****************************************************************************/
 246 #define XDmaV3_mWriteReg(BaseAddress, RegOffset, Data)  \
 247     XIo_Out32((u32)(BaseAddress) + (u32)(RegOffset), (u32)(Data))
 248
 249
 250 /****************************************************************************/
 251 /**
 252 *
 253 * Read the given Buffer Descriptor word.
 254 *
 255 * @param    BaseAddress is the base address of the BD to read
 256 * @param    Offset is the word offset to be read
 257 *
 258 * @return   The 32-bit value of the field
 259 *
 260 * @note
 261 * C-style signature:
 262 *    u32 XDmaV3_mReadBd(u32 BaseAddress, u32 Offset)
 263 *
 264 *****************************************************************************/
 265 #define XDmaV3_mReadBd(BaseAddress, Offset)             \
 266     (*(u32*)((u32)(BaseAddress) + (u32)(Offset)))
 267
 268
 269 /****************************************************************************/
 270 /**
 271 *
 272 * Write the given Buffer Descriptor word.
 273 *
 274 * @param    BaseAddress is the base address of the BD to write
 275 * @param    Offset is the word offset to be written
 276 * @param    Data is the 32-bit value to write to the field
 277 *
 278 * @return   None.
 279 *
 280 * @note
 281 * C-style signature:
 282 *    void XDmaV3_mWriteReg(u32 BaseAddress, u32 Offset, u32 Data)
 283 *
 284 *****************************************************************************/
 285 #define XDmaV3_mWriteBd(BaseAddress, Offset, Data)              \
 286     (*(u32*)((u32)(BaseAddress) + (u32)(Offset)) = (Data))
 287
 288
 289 /************************** Function Prototypes ******************************/
 290
 291 #ifdef __cplusplus
 292 }
 293 #endif
 294
 295 #endif /* end of protection macro */