drivers/xilinx_common/xdma_channel.c

   1 /* $Id: xdma_channel.c,v 1.1 2006/12/13 14:21:45 imanuilov Exp $ */
   2 /******************************************************************************
   3 *
   4 *       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
   5 *       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
   6 *       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
   7 *       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
   8 *       APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
   9 *       THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
  10 *       AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
  11 *       FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
  12 *       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
  13 *       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
  14 *       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
  15 *       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  16 *       FOR A PARTICULAR PURPOSE.
  17 *
  18 *       (c) Copyright 2001-2004 Xilinx Inc.
  19 *       All rights reserved.
  20 * This program is free software; you can redistribute it and/or modify it
  21 * under the terms of the GNU General Public License as published by the
  22 * Free Software Foundation; either version 2 of the License, or (at your
  23 * option) any later version.
  24 *
  25 * You should have received a copy of the GNU General Public License
  26 * along with this program; if not, write to the Free Software
  27 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28 *
  29 ******************************************************************************/
  30 /*****************************************************************************/
  31 /**
  32 *
  33 * @file xdma_channel.c
  34 *
  35 * <b>Description</b>
  36 *
  37 * This file contains the DMA channel component. This component supports
  38 * a distributed DMA design in which each device can have it's own dedicated
  39 * DMA channel, as opposed to a centralized DMA design. This component
  40 * performs processing for DMA on all devices.
  41 *
  42 * See xdma_channel.h for more information about this component.
  43 *
  44 * @note
  45 *
  46 * None.
  47 *
  48 * <pre>
  49 * MODIFICATION HISTORY:
  50 *
  51 * Ver   Who  Date     Changes
  52 * ----- ---- -------- -----------------------------------------------
  53 * 1.00a xd  10/27/04  Doxygenated for inclusion in API documentation
  54 * 1.00b ecm 10/31/05  Updated for the check sum offload changes.
  55 * 1.00b xd  03/22/06  Fixed a multi-descriptor packet related bug that sgdma
  56 *                     engine is restarted in case no scatter gather disabled
  57 *                     bit is set yet
  58 * </pre>
  59 *
  60 ******************************************************************************/
  61
  62 /***************************** Include Files *********************************/
  63
  64 #include "xdma_channel.h"
  65 #include "xbasic_types.h"
  66 #include "xio.h"
  67
  68 /************************** Constant Definitions *****************************/
  69
  70
  71 /**************************** Type Definitions *******************************/
  72
  73
  74 /***************** Macros (Inline Functions) Definitions *********************/
  75
  76
  77 /************************** Function Prototypes ******************************/
  78
  79
  80 /*****************************************************************************/
  81 /**
  82 *
  83 * This function initializes a DMA channel.  This function must be called
  84 * prior to using a DMA channel.  Initialization of a channel includes setting
  85 * up the registers base address, and resetting the channel such that it's in a
  86 * known state.  Interrupts for the channel are disabled when the channel is
  87 * reset.
  88 *
  89 * @param
  90 *
  91 * InstancePtr contains a pointer to the DMA channel to operate on.
  92 *
  93 * @param
  94 *
  95 * BaseAddress contains the base address of the registers for the DMA channel.
  96 *
  97 * @return
  98 *
  99 * XST_SUCCESS indicating initialization was successful.
 100 *
 101 * @note
 102 *
 103 * None.
 104 *
 105 ******************************************************************************/
 106 int XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress)
 107 {
 108         /* assert to verify input arguments, don't assert base address */
 109
 110         XASSERT_NONVOID(InstancePtr != NULL);
 111
 112         /* setup the base address of the registers for the DMA channel such
 113          * that register accesses can be done
 114          */
 115         InstancePtr->RegBaseAddress = BaseAddress;
 116
 117         /* initialize the scatter gather list such that it indicates it has not
 118          * been created yet and the DMA channel is ready to use (initialized)
 119          */
 120         InstancePtr->GetPtr = NULL;
 121         InstancePtr->PutPtr = NULL;
 122         InstancePtr->CommitPtr = NULL;
 123         InstancePtr->LastPtr = NULL;
 124
 125         InstancePtr->TotalDescriptorCount = 0;
 126         InstancePtr->ActiveDescriptorCount = 0;
 127
 128         InstancePtr->ActivePacketCount = 0;
 129         InstancePtr->Committed = FALSE;
 130
 131         InstancePtr->IsReady = XCOMPONENT_IS_READY;
 132
 133         /* initialize the version of the component
 134          */
 135         XVersion_FromString(&InstancePtr->Version, "1.00a");
 136
 137         /* reset the DMA channel such that it's in a known state and ready
 138          * and indicate the initialization occurred with no errors, note that
 139          * the is ready variable must be set before this call or reset will assert
 140          */
 141         XDmaChannel_Reset(InstancePtr);
 142
 143         return XST_SUCCESS;
 144 }
 145
 146 /*****************************************************************************/
 147 /**
 148 *
 149 * This function determines if a DMA channel component has been successfully
 150 * initialized such that it's ready to use.
 151 *
 152 * @param
 153 *
 154 * InstancePtr contains a pointer to the DMA channel to operate on.
 155 *
 156 * @return
 157 *
 158 * TRUE if the DMA channel component is ready, FALSE otherwise.
 159 *
 160 * @note
 161 *
 162 * None.
 163 *
 164 ******************************************************************************/
 165 u32 XDmaChannel_IsReady(XDmaChannel * InstancePtr)
 166 {
 167         /* assert to verify input arguments used by the base component */
 168
 169         XASSERT_NONVOID(InstancePtr != NULL);
 170
 171         return InstancePtr->IsReady == XCOMPONENT_IS_READY;
 172 }
 173
 174 /*****************************************************************************/
 175 /**
 176 *
 177 * This function gets the software version for the specified DMA channel
 178 * component.
 179 *
 180 * @param
 181 *
 182 * InstancePtr contains a pointer to the DMA channel to operate on.
 183 *
 184 * @return
 185 *
 186 * A pointer to the software version of the specified DMA channel.
 187 *
 188 * @note
 189 *
 190 * None.
 191 *
 192 ******************************************************************************/
 193 XVersion *XDmaChannel_GetVersion(XDmaChannel * InstancePtr)
 194 {
 195         /* assert to verify input arguments */
 196
 197         XASSERT_NONVOID(InstancePtr != NULL);
 198         XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 199
 200         /* return a pointer to the version of the DMA channel */
 201
 202         return &InstancePtr->Version;
 203 }
 204
 205 /*****************************************************************************/
 206 /**
 207 *
 208 * This function performs a self test on the specified DMA channel.  This self
 209 * test is destructive as the DMA channel is reset and a register default is
 210 * verified.
 211 *
 212 * @param
 213 *
 214 * InstancePtr is a pointer to the DMA channel to be operated on.
 215 *
 216 * @return
 217 *
 218 * XST_SUCCESS is returned if the self test is successful, or one of the
 219 * following errors.
 220 *                                       <br><br>
 221 * - XST_DMA_RESET_REGISTER_ERROR        Indicates the control register value
 222 *                                       after a reset was not correct
 223 *
 224 * @note
 225 *
 226 * This test does not performs a DMA transfer to test the channel because the
 227 * DMA hardware will not currently allow a non-local memory transfer to non-local
 228 * memory (memory copy), but only allows a non-local memory to or from the device
 229 * memory (typically a FIFO).
 230 *
 231 ******************************************************************************/
 232
 233 #define XDC_CONTROL_REG_RESET_MASK  0x98000000UL        /* control reg reset value */
 234
 235 int XDmaChannel_SelfTest(XDmaChannel * InstancePtr)
 236 {
 237         u32 ControlReg;
 238
 239         /* assert to verify input arguments */
 240
 241         XASSERT_NONVOID(InstancePtr != NULL);
 242         XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 243
 244         /* reset the DMA channel such that it's in a known state before the test
 245          * it resets to no interrupts enabled, the desired state for the test
 246          */
 247         XDmaChannel_Reset(InstancePtr);
 248
 249         /* this should be the first test to help prevent a lock up with the polling
 250          * loop that occurs later in the test, check the reset value of the DMA
 251          * control register to make sure it's correct, return with an error if not
 252          */
 253         ControlReg = XDmaChannel_GetControl(InstancePtr);
 254         if (ControlReg != XDC_CONTROL_REG_RESET_MASK) {
 255                 return XST_DMA_RESET_REGISTER_ERROR;
 256         }
 257
 258         return XST_SUCCESS;
 259 }
 260
 261 /*****************************************************************************/
 262 /**
 263 *
 264 * This function resets the DMA channel. This is a destructive operation such
 265 * that it should not be done while a channel is being used.  If the DMA channel
 266 * is transferring data into other blocks, such as a FIFO, it may be necessary
 267 * to reset other blocks.  This function does not modify the contents of a
 268 * scatter gather list for a DMA channel such that the user is responsible for
 269 * getting buffer descriptors from the list if necessary.
 270 *
 271 * @param
 272 *
 273 * InstancePtr contains a pointer to the DMA channel to operate on.
 274 *
 275 * @return
 276 *
 277 * None.
 278 *
 279 * @note
 280 *
 281 * None.
 282 *
 283 ******************************************************************************/
 284 void XDmaChannel_Reset(XDmaChannel * InstancePtr)
 285 {
 286         /* assert to verify input arguments */
 287
 288         XASSERT_VOID(InstancePtr != NULL);
 289         XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 290
 291         /* reset the DMA channel such that it's in a known state, the reset
 292          * register is self clearing such that it only has to be set
 293          */
 294         XIo_Out32(InstancePtr->RegBaseAddress + XDC_RST_REG_OFFSET,
 295                   XDC_RESET_MASK);
 296 }
 297
 298 /*****************************************************************************/
 299 /**
 300 *
 301 * This function gets the control register contents of the DMA channel.
 302 *
 303 * @param
 304 *
 305 * InstancePtr contains a pointer to the DMA channel to operate on.
 306 *
 307 * @return
 308 *
 309 * The control register contents of the DMA channel. One or more of the
 310 * following values may be contained the register.  Each of the values are
 311 * unique bit masks.
 312 *                               <br><br>
 313 * - XDC_DMACR_SOURCE_INCR_MASK  Increment the source address
 314 *                               <br><br>
 315 * - XDC_DMACR_DEST_INCR_MASK    Increment the destination address
 316 *                               <br><br>
 317 * - XDC_DMACR_SOURCE_LOCAL_MASK Local source address
 318 *                               <br><br>
 319 * - XDC_DMACR_DEST_LOCAL_MASK   Local destination address
 320 *                               <br><br>
 321 * - XDC_DMACR_SG_ENABLE_MASK    Scatter gather enable
 322 *                               <br><br>
 323 * - XDC_DMACR_GEN_BD_INTR_MASK  Individual buffer descriptor interrupt
 324 *                               <br><br>
 325 * - XDC_DMACR_LAST_BD_MASK      Last buffer descriptor in a packet
 326 *
 327 * @note
 328 *
 329 * None.
 330 *
 331 ******************************************************************************/
 332 u32 XDmaChannel_GetControl(XDmaChannel * InstancePtr)
 333 {
 334         /* assert to verify input arguments */
 335
 336         XASSERT_NONVOID(InstancePtr != NULL);
 337         XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 338
 339         /* return the contents of the DMA control register */
 340
 341         return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET);
 342 }
 343
 344 /*****************************************************************************/
 345 /**
 346 *
 347 * This function sets the control register of the specified DMA channel.
 348 *
 349 * @param
 350 *
 351 * InstancePtr contains a pointer to the DMA channel to operate on.
 352 *
 353 * @param
 354 *
 355 * Control contains the value to be written to the control register of the DMA
 356 * channel. One or more of the following values may be contained the register.
 357 * Each of the values are unique bit masks such that they may be ORed together
 358 * to enable multiple bits or inverted and ANDed to disable multiple bits.
 359 * - XDC_DMACR_SOURCE_INCR_MASK  Increment the source address
 360 * - XDC_DMACR_DEST_INCR_MASK    Increment the destination address
 361 * - XDC_DMACR_SOURCE_LOCAL_MASK Local source address
 362 * - XDC_DMACR_DEST_LOCAL_MASK   Local destination address
 363 * - XDC_DMACR_SG_ENABLE_MASK    Scatter gather enable
 364 * - XDC_DMACR_GEN_BD_INTR_MASK  Individual buffer descriptor interrupt
 365 * - XDC_DMACR_LAST_BD_MASK      Last buffer descriptor in a packet
 366 *
 367 * @return
 368 *
 369 * None.
 370 *
 371 * @note
 372 *
 373 * None.
 374 *
 375 ******************************************************************************/
 376 void XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control)
 377 {
 378         u32 Register;
 379
 380         /* assert to verify input arguments except the control which can't be
 381          * asserted since all values are valid
 382          */
 383         XASSERT_VOID(InstancePtr != NULL);
 384         XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 385
 386         /*
 387          * set the DMA control register to the specified value, not altering the
 388          * other fields in the register
 389          */
 390
 391         Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET);
 392         Register &= XDC_DMACR_TX_CS_INIT_MASK;
 393         XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET,
 394                   Register | Control);
 395 }
 396
 397 /*****************************************************************************/
 398 /**
 399 *
 400 * This function gets the status register contents of the DMA channel.
 401 *
 402 * @param
 403 *
 404 * InstancePtr contains a pointer to the DMA channel to operate on.
 405 *
 406 * @return
 407 *
 408 * The status register contents of the DMA channel. One or more of the
 409 * following values may be contained the register. Each of the values are
 410 * unique bit masks.
 411 *                               <br><br>
 412 * - XDC_DMASR_BUSY_MASK         The DMA channel is busy
 413 *                               <br><br>
 414 * - XDC_DMASR_BUS_ERROR_MASK    A bus error occurred
 415 *                               <br><br>
 416 * - XDC_DMASR_BUS_TIMEOUT_MASK  A bus timeout occurred
 417 *                               <br><br>
 418 * - XDC_DMASR_LAST_BD_MASK      The last buffer descriptor of a packet
 419 *
 420 * @note
 421 *
 422 * None.
 423 *
 424 ******************************************************************************/
 425 u32 XDmaChannel_GetStatus(XDmaChannel * InstancePtr)
 426 {
 427         /* assert to verify input arguments */
 428
 429         XASSERT_NONVOID(InstancePtr != NULL);
 430         XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 431
 432         /* return the contents of the DMA status register */
 433
 434         return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET);
 435 }
 436
 437 /*****************************************************************************/
 438 /**
 439 *
 440 * This function sets the interrupt status register of the specified DMA channel.
 441 * Setting any bit of the interrupt status register will clear the bit to
 442 * indicate the interrupt processing has been completed. The definitions of each
 443 * bit in the register match the definition of the bits in the interrupt enable
 444 * register.
 445 *
 446 * @param
 447 *
 448 * InstancePtr contains a pointer to the DMA channel to operate on.
 449 *
 450 * @param
 451 *
 452 * Status contains the value to be written to the status register of the DMA
 453 * channel.  One or more of the following values may be contained the register.
 454 * Each of the values are unique bit masks such that they may be ORed together
 455 * to enable multiple bits or inverted and ANDed to disable multiple bits.
 456 * - XDC_IXR_DMA_DONE_MASK       The dma operation is done
 457 * - XDC_IXR_DMA_ERROR_MASK      The dma operation had an error
 458 * - XDC_IXR_PKT_DONE_MASK       A packet is complete
 459 * - XDC_IXR_PKT_THRESHOLD_MASK  The packet count threshold reached
 460 * - XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
 461 * - XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
 462 * - XDC_IXR_BD_MASK             A buffer descriptor is done
 463 *
 464 * @return
 465 *
 466 * None.
 467 *
 468 * @note
 469 *
 470 * None.
 471 *
 472 ******************************************************************************/
 473 void XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status)
 474 {
 475         /* assert to verify input arguments except the status which can't be
 476          * asserted since all values are valid
 477          */
 478         XASSERT_VOID(InstancePtr != NULL);
 479         XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 480
 481         /* set the interrupt status register with the specified value such that
 482          * all bits which are set in the register are cleared effectively clearing
 483          * any active interrupts
 484          */
 485         XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET, Status);
 486 }
 487
 488 /*****************************************************************************/
 489 /**
 490 *
 491 * This function gets the interrupt status register of the specified DMA channel.
 492 * The interrupt status register indicates which interrupts are active
 493 * for the DMA channel.  If an interrupt is active, the status register must be
 494 * set (written) with the bit set for each interrupt which has been processed
 495 * in order to clear the interrupts.  The definitions of each bit in the register
 496 * match the definition of the bits in the interrupt enable register.
 497 *
 498 * @param
 499 *
 500 * InstancePtr contains a pointer to the DMA channel to operate on.
 501 *
 502 * @return
 503 *
 504 * The interrupt status register contents of the specified DMA channel.
 505 * One or more of the following values may be contained the register.
 506 * Each of the values are unique bit masks.
 507 *                               <br><br>
 508 * - XDC_IXR_DMA_DONE_MASK       The dma operation is done
 509 *                               <br><br>
 510 * - XDC_IXR_DMA_ERROR_MASK      The dma operation had an error
 511 *                               <br><br>
 512 * - XDC_IXR_PKT_DONE_MASK       A packet is complete
 513 *                               <br><br>
 514 * - XDC_IXR_PKT_THRESHOLD_MASK  The packet count threshold reached
 515 *                               <br><br>
 516 * - XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
 517 *                               <br><br>
 518 * - XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
 519 *                               <br><br>
 520 * - XDC_IXR_SG_END_MASK         Current descriptor was the end of the list
 521 *                               <br><br>
 522 * - XDC_IXR_BD_MASK             A buffer descriptor is done
 523 *
 524 * @note
 525 *
 526 * None.
 527 *
 528 ******************************************************************************/
 529 u32 XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr)
 530 {
 531         /* assert to verify input arguments */
 532
 533         XASSERT_NONVOID(InstancePtr != NULL);
 534         XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 535
 536         /* return the contents of the interrupt status register */
 537
 538         return XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET);
 539 }
 540
 541 /*****************************************************************************/
 542 /**
 543 *
 544 * This function sets the interrupt enable register of the specified DMA
 545 * channel.  The interrupt enable register contains bits which enable
 546 * individual interrupts for the DMA channel.  The definitions of each bit
 547 * in the register match the definition of the bits in the interrupt status
 548 * register.
 549 *
 550 * @param
 551 *
 552 * InstancePtr contains a pointer to the DMA channel to operate on.
 553 *
 554 * @param
 555 *
 556 * Enable contains the interrupt enable register contents to be written
 557 * in the DMA channel. One or more of the following values may be contained
 558 * the register. Each of the values are unique bit masks such that they may be
 559 * ORed together to enable multiple bits or inverted and ANDed to disable
 560 * multiple bits.
 561 * - XDC_IXR_DMA_DONE_MASK       The dma operation is done
 562 * - XDC_IXR_DMA_ERROR_MASK      The dma operation had an error
 563 * - XDC_IXR_PKT_DONE_MASK       A packet is complete
 564 * - XDC_IXR_PKT_THRESHOLD_MASK  The packet count threshold reached
 565 * - XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
 566 * - XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
 567 * - XDC_IXR_SG_END_MASK         Current descriptor was the end of the list
 568 * - XDC_IXR_BD_MASK             A buffer descriptor is done
 569 *
 570 * @return
 571 *
 572 * None.
 573 *
 574 * @note
 575 *
 576 * None.
 577 *
 578 ******************************************************************************/
 579 void XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable)
 580 {
 581         /* assert to verify input arguments except the enable which can't be
 582          * asserted since all values are valid
 583          */
 584         XASSERT_VOID(InstancePtr != NULL);
 585         XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 586
 587         /* set the interrupt enable register to the specified value */
 588
 589         XIo_Out32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET, Enable);
 590 }
 591
 592 /*****************************************************************************/
 593 /**
 594 *
 595 * This function gets the interrupt enable of the DMA channel.  The
 596 * interrupt enable contains flags which enable individual interrupts for the
 597 * DMA channel. The definitions of each bit in the register match the definition
 598 * of the bits in the interrupt status register.
 599 *
 600 * @param
 601 *
 602 * InstancePtr contains a pointer to the DMA channel to operate on.
 603 *
 604 * @return
 605 *
 606 * The interrupt enable of the DMA channel.  One or more of the following values
 607 * may be contained the register. Each of the values are unique bit masks.
 608 *                               <br><br>
 609 * - XDC_IXR_DMA_DONE_MASK       The dma operation is done
 610 *                               <br><br>
 611 * - XDC_IXR_DMA_ERROR_MASK      The dma operation had an error
 612 *                               <br><br>
 613 * - XDC_IXR_PKT_DONE_MASK       A packet is complete
 614 *                               <br><br>
 615 * - XDC_IXR_PKT_THRESHOLD_MASK  The packet count threshold reached
 616 *                               <br><br>
 617 * - XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
 618 *                               <br><br>
 619 * - XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
 620 *                               <br><br>
 621 * - XDC_IXR_BD_MASK             A buffer descriptor is done
 622 *
 623 * @note
 624 *
 625 * None.
 626 *
 627 ******************************************************************************/
 628 u32 XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr)
 629 {
 630         /* assert to verify input arguments */
 631
 632         XASSERT_NONVOID(InstancePtr != NULL);
 633         XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 634
 635         /* return the contents of the interrupt enable register */
 636
 637         return XIo_In32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET);
 638 }
 639
 640 /*****************************************************************************/
 641 /**
 642 *
 643 * This function starts the DMA channel transferring data from a memory source
 644 * to a memory destination. This function only starts the operation and returns
 645 * before the operation may be complete.  If the interrupt is enabled, an
 646 * interrupt will be generated when the operation is complete, otherwise it is
 647 * necessary to poll the channel status to determine when it's complete.  It is
 648 * the responsibility of the caller to determine when the operation is complete
 649 * by handling the generated interrupt or polling the status.  It is also the
 650 * responsibility of the caller to ensure that the DMA channel is not busy with
 651 * another transfer before calling this function.
 652 *
 653 * @param
 654 *
 655 * InstancePtr contains a pointer to the DMA channel to operate on.
 656 *
 657 * @param
 658 *
 659 * SourcePtr contains a pointer to the source memory where the data is to
 660 * be transferred from and must be 32 bit aligned.
 661 *
 662 * @param
 663 *
 664 * DestinationPtr contains a pointer to the destination memory where the data
 665 * is to be transferred and must be 32 bit aligned.
 666 *
 667 * @param
 668 *
 669 * ByteCount contains the number of bytes to transfer during the DMA operation.
 670 *
 671 * @return
 672 *
 673 * None.
 674 *
 675 * @note
 676 *
 677 * The DMA hw will not currently allow a non-local memory transfer to non-local
 678 * memory (memory copy), but only allows a non-local memory to or from the device
 679 * memory (typically a FIFO).
 680 * <br><br>
 681 * It is the responsibility of the caller to ensure that the cache is
 682 * flushed and invalidated both before and after the DMA operation completes
 683 * if the memory pointed to is cached. The caller must also ensure that the
 684 * pointers contain a physical address rather than a virtual address
 685 * if address translation is being used.
 686 *
 687 ******************************************************************************/
 688 void XDmaChannel_Transfer(XDmaChannel * InstancePtr,
 689                           u32 *SourcePtr, u32 *DestinationPtr, u32 ByteCount)
 690 {
 691         /* assert to verify input arguments and the alignment of any arguments
 692          * which have expected alignments
 693          */
 694         XASSERT_VOID(InstancePtr != NULL);
 695         XASSERT_VOID(SourcePtr != NULL);
 696         XASSERT_VOID(((u32) SourcePtr & 3) == 0);
 697         XASSERT_VOID(DestinationPtr != NULL);
 698         XASSERT_VOID(((u32) DestinationPtr & 3) == 0);
 699         XASSERT_VOID(ByteCount != 0);
 700         XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
 701
 702         /* setup the source and destination address registers for the transfer */
 703
 704         XIo_Out32(InstancePtr->RegBaseAddress + XDC_SA_REG_OFFSET,
 705                   (u32) SourcePtr);
 706
 707         XIo_Out32(InstancePtr->RegBaseAddress + XDC_DA_REG_OFFSET,
 708                   (u32) DestinationPtr);
 709
 710         /* start the DMA transfer to copy from the source buffer to the
 711          * destination buffer by writing the length to the length register
 712          */
 713         XIo_Out32(InstancePtr->RegBaseAddress + XDC_LEN_REG_OFFSET, ByteCount);
 714 }