?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
serial: xilinx_uartps: fix bad register write in console_write
[linux-2.6-xlnx.git] / drivers / net / irda / pxaficp_ir.c
blobff16daf33ae130df9f3de215e790e1c997748870
1 /*
2 * linux/drivers/net/irda/pxaficp_ir.c
3 *
4 * Based on sa1100_ir.c by Russell King
5 *
6 * Changes copyright (C) 2003-2005 MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Infra-red driver (SIR/FIR) for the PXA2xx embedded microprocessor
13 *
14 */
15 #include <linux/dma-mapping.h>
16 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/netdevice.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/gpio.h>
23 #include <linux/slab.h>
24
25 #include <net/irda/irda.h>
26 #include <net/irda/irmod.h>
27 #include <net/irda/wrapper.h>
28 #include <net/irda/irda_device.h>
29
30 #include <mach/dma.h>
31 #include <mach/irda.h>
32 #include <mach/regs-uart.h>
33 #include <mach/regs-ost.h>
34
35 #define FICP __REG(0x40800000) /* Start of FICP area */
36 #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
37 #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
38 #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
39 #define ICDR __REG(0x4080000c) /* ICP Data Register */
40 #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
41 #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
42
43 #define ICCR0_AME (1 << 7) /* Address match enable */
44 #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
45 #define ICCR0_RIE (1 << 5) /* Receive FIFO interrupt enable */
46 #define ICCR0_RXE (1 << 4) /* Receive enable */
47 #define ICCR0_TXE (1 << 3) /* Transmit enable */
48 #define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
49 #define ICCR0_LBM (1 << 1) /* Loopback mode */
50 #define ICCR0_ITR (1 << 0) /* IrDA transmission */
51
52 #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
53 #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
54 #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
55 #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
56 #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
57 #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
58
59 #ifdef CONFIG_PXA27x
60 #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
61 #endif
62 #define ICSR0_FRE (1 << 5) /* Framing error */
63 #define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
64 #define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
65 #define ICSR0_RAB (1 << 2) /* Receiver abort */
66 #define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
67 #define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
68
69 #define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
70 #define ICSR1_CRE (1 << 5) /* CRC error */
71 #define ICSR1_EOF (1 << 4) /* End of frame */
72 #define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
73 #define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
74 #define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
75 #define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
76
77 #define IrSR_RXPL_NEG_IS_ZERO (1<<4)
78 #define IrSR_RXPL_POS_IS_ZERO 0x0
79 #define IrSR_TXPL_NEG_IS_ZERO (1<<3)
80 #define IrSR_TXPL_POS_IS_ZERO 0x0
81 #define IrSR_XMODE_PULSE_1_6 (1<<2)
82 #define IrSR_XMODE_PULSE_3_16 0x0
83 #define IrSR_RCVEIR_IR_MODE (1<<1)
84 #define IrSR_RCVEIR_UART_MODE 0x0
85 #define IrSR_XMITIR_IR_MODE (1<<0)
86 #define IrSR_XMITIR_UART_MODE 0x0
87
88 #define IrSR_IR_RECEIVE_ON (\
89 IrSR_RXPL_NEG_IS_ZERO | \
90 IrSR_TXPL_POS_IS_ZERO | \
91 IrSR_XMODE_PULSE_3_16 | \
92 IrSR_RCVEIR_IR_MODE | \
93 IrSR_XMITIR_UART_MODE)
94
95 #define IrSR_IR_TRANSMIT_ON (\
96 IrSR_RXPL_NEG_IS_ZERO | \
97 IrSR_TXPL_POS_IS_ZERO | \
98 IrSR_XMODE_PULSE_3_16 | \
99 IrSR_RCVEIR_UART_MODE | \
100 IrSR_XMITIR_IR_MODE)
101
102 struct pxa_irda {
103 int speed;
104 int newspeed;
105 unsigned long last_oscr;
106
107 unsigned char *dma_rx_buff;
108 unsigned char *dma_tx_buff;
109 dma_addr_t dma_rx_buff_phy;
110 dma_addr_t dma_tx_buff_phy;
111 unsigned int dma_tx_buff_len;
112 int txdma;
113 int rxdma;
114
115 struct irlap_cb *irlap;
116 struct qos_info qos;
117
118 iobuff_t tx_buff;
119 iobuff_t rx_buff;
120
121 struct device *dev;
122 struct pxaficp_platform_data *pdata;
123 struct clk *fir_clk;
124 struct clk *sir_clk;
125 struct clk *cur_clk;
126 };
127
128 static inline void pxa_irda_disable_clk(struct pxa_irda *si)
129 {
130 if (si->cur_clk)
131 clk_disable_unprepare(si->cur_clk);
132 si->cur_clk = NULL;
133 }
134
135 static inline void pxa_irda_enable_firclk(struct pxa_irda *si)
136 {
137 si->cur_clk = si->fir_clk;
138 clk_prepare_enable(si->fir_clk);
139 }
140
141 static inline void pxa_irda_enable_sirclk(struct pxa_irda *si)
142 {
143 si->cur_clk = si->sir_clk;
144 clk_prepare_enable(si->sir_clk);
145 }
146
147
148 #define IS_FIR(si) ((si)->speed >= 4000000)
149 #define IRDA_FRAME_SIZE_LIMIT 2047
150
151 inline static void pxa_irda_fir_dma_rx_start(struct pxa_irda *si)
152 {
153 DCSR(si->rxdma) = DCSR_NODESC;
154 DSADR(si->rxdma) = __PREG(ICDR);
155 DTADR(si->rxdma) = si->dma_rx_buff_phy;
156 DCMD(si->rxdma) = DCMD_INCTRGADDR | DCMD_FLOWSRC | DCMD_WIDTH1 | DCMD_BURST32 | IRDA_FRAME_SIZE_LIMIT;
157 DCSR(si->rxdma) |= DCSR_RUN;
158 }
159
160 inline static void pxa_irda_fir_dma_tx_start(struct pxa_irda *si)
161 {
162 DCSR(si->txdma) = DCSR_NODESC;
163 DSADR(si->txdma) = si->dma_tx_buff_phy;
164 DTADR(si->txdma) = __PREG(ICDR);
165 DCMD(si->txdma) = DCMD_INCSRCADDR | DCMD_FLOWTRG | DCMD_ENDIRQEN | DCMD_WIDTH1 | DCMD_BURST32 | si->dma_tx_buff_len;
166 DCSR(si->txdma) |= DCSR_RUN;
167 }
168
169 /*
170 * Set the IrDA communications mode.
171 */
172 static void pxa_irda_set_mode(struct pxa_irda *si, int mode)
173 {
174 if (si->pdata->transceiver_mode)
175 si->pdata->transceiver_mode(si->dev, mode);
176 else {
177 if (gpio_is_valid(si->pdata->gpio_pwdown))
178 gpio_set_value(si->pdata->gpio_pwdown,
179 !(mode & IR_OFF) ^
180 !si->pdata->gpio_pwdown_inverted);
181 pxa2xx_transceiver_mode(si->dev, mode);
182 }
183 }
184
185 /*
186 * Set the IrDA communications speed.
187 */
188 static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
189 {
190 unsigned long flags;
191 unsigned int divisor;
192
193 switch (speed) {
194 case 9600: case 19200: case 38400:
195 case 57600: case 115200:
196
197 /* refer to PXA250/210 Developer's Manual 10-7 */
198 /* BaudRate = 14.7456 MHz / (16*Divisor) */
199 divisor = 14745600 / (16 * speed);
200
201 local_irq_save(flags);
202
203 if (IS_FIR(si)) {
204 /* stop RX DMA */
205 DCSR(si->rxdma) &= ~DCSR_RUN;
206 /* disable FICP */
207 ICCR0 = 0;
208 pxa_irda_disable_clk(si);
209
210 /* set board transceiver to SIR mode */
211 pxa_irda_set_mode(si, IR_SIRMODE);
212
213 /* enable the STUART clock */
214 pxa_irda_enable_sirclk(si);
215 }
216
217 /* disable STUART first */
218 STIER = 0;
219
220 /* access DLL & DLH */
221 STLCR |= LCR_DLAB;
222 STDLL = divisor & 0xff;
223 STDLH = divisor >> 8;
224 STLCR &= ~LCR_DLAB;
225
226 si->speed = speed;
227 STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6;
228 STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE;
229
230 local_irq_restore(flags);
231 break;
232
233 case 4000000:
234 local_irq_save(flags);
235
236 /* disable STUART */
237 STIER = 0;
238 STISR = 0;
239 pxa_irda_disable_clk(si);
240
241 /* disable FICP first */
242 ICCR0 = 0;
243
244 /* set board transceiver to FIR mode */
245 pxa_irda_set_mode(si, IR_FIRMODE);
246
247 /* enable the FICP clock */
248 pxa_irda_enable_firclk(si);
249
250 si->speed = speed;
251 pxa_irda_fir_dma_rx_start(si);
252 ICCR0 = ICCR0_ITR | ICCR0_RXE;
253
254 local_irq_restore(flags);
255 break;
256
257 default:
258 return -EINVAL;
259 }
260
261 return 0;
262 }
263
264 /* SIR interrupt service routine. */
265 static irqreturn_t pxa_irda_sir_irq(int irq, void *dev_id)
266 {
267 struct net_device *dev = dev_id;
268 struct pxa_irda *si = netdev_priv(dev);
269 int iir, lsr, data;
270
271 iir = STIIR;
272
273 switch (iir & 0x0F) {
274 case 0x06: /* Receiver Line Status */
275 lsr = STLSR;
276 while (lsr & LSR_FIFOE) {
277 data = STRBR;
278 if (lsr & (LSR_OE | LSR_PE | LSR_FE | LSR_BI)) {
279 printk(KERN_DEBUG "pxa_ir: sir receiving error\n");
280 dev->stats.rx_errors++;
281 if (lsr & LSR_FE)
282 dev->stats.rx_frame_errors++;
283 if (lsr & LSR_OE)
284 dev->stats.rx_fifo_errors++;
285 } else {
286 dev->stats.rx_bytes++;
287 async_unwrap_char(dev, &dev->stats,
288 &si->rx_buff, data);
289 }
290 lsr = STLSR;
291 }
292 si->last_oscr = OSCR;
293 break;
294
295 case 0x04: /* Received Data Available */
296 /* forth through */
297
298 case 0x0C: /* Character Timeout Indication */
299 do {
300 dev->stats.rx_bytes++;
301 async_unwrap_char(dev, &dev->stats, &si->rx_buff, STRBR);
302 } while (STLSR & LSR_DR);
303 si->last_oscr = OSCR;
304 break;
305
306 case 0x02: /* Transmit FIFO Data Request */
307 while ((si->tx_buff.len) && (STLSR & LSR_TDRQ)) {
308 STTHR = *si->tx_buff.data++;
309 si->tx_buff.len -= 1;
310 }
311
312 if (si->tx_buff.len == 0) {
313 dev->stats.tx_packets++;
314 dev->stats.tx_bytes += si->tx_buff.data - si->tx_buff.head;
315
316 /* We need to ensure that the transmitter has finished. */
317 while ((STLSR & LSR_TEMT) == 0)
318 cpu_relax();
319 si->last_oscr = OSCR;
320
321 /*
322 * Ok, we've finished transmitting. Now enable
323 * the receiver. Sometimes we get a receive IRQ
324 * immediately after a transmit...
325 */
326 if (si->newspeed) {
327 pxa_irda_set_speed(si, si->newspeed);
328 si->newspeed = 0;
329 } else {
330 /* enable IR Receiver, disable IR Transmitter */
331 STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6;
332 /* enable STUART and receive interrupts */
333 STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE;
334 }
335 /* I'm hungry! */
336 netif_wake_queue(dev);
337 }
338 break;
339 }
340
341 return IRQ_HANDLED;
342 }
343
344 /* FIR Receive DMA interrupt handler */
345 static void pxa_irda_fir_dma_rx_irq(int channel, void *data)
346 {
347 int dcsr = DCSR(channel);
348
349 DCSR(channel) = dcsr & ~DCSR_RUN;
350
351 printk(KERN_DEBUG "pxa_ir: fir rx dma bus error %#x\n", dcsr);
352 }
353
354 /* FIR Transmit DMA interrupt handler */
355 static void pxa_irda_fir_dma_tx_irq(int channel, void *data)
356 {
357 struct net_device *dev = data;
358 struct pxa_irda *si = netdev_priv(dev);
359 int dcsr;
360
361 dcsr = DCSR(channel);
362 DCSR(channel) = dcsr & ~DCSR_RUN;
363
364 if (dcsr & DCSR_ENDINTR) {
365 dev->stats.tx_packets++;
366 dev->stats.tx_bytes += si->dma_tx_buff_len;
367 } else {
368 dev->stats.tx_errors++;
369 }
370
371 while (ICSR1 & ICSR1_TBY)
372 cpu_relax();
373 si->last_oscr = OSCR;
374
375 /*
376 * HACK: It looks like the TBY bit is dropped too soon.
377 * Without this delay things break.
378 */
379 udelay(120);
380
381 if (si->newspeed) {
382 pxa_irda_set_speed(si, si->newspeed);
383 si->newspeed = 0;
384 } else {
385 int i = 64;
386
387 ICCR0 = 0;
388 pxa_irda_fir_dma_rx_start(si);
389 while ((ICSR1 & ICSR1_RNE) && i--)
390 (void)ICDR;
391 ICCR0 = ICCR0_ITR | ICCR0_RXE;
392
393 if (i < 0)
394 printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n");
395 }
396 netif_wake_queue(dev);
397 }
398
399 /* EIF(Error in FIFO/End in Frame) handler for FIR */
400 static void pxa_irda_fir_irq_eif(struct pxa_irda *si, struct net_device *dev, int icsr0)
401 {
402 unsigned int len, stat, data;
403
404 /* Get the current data position. */
405 len = DTADR(si->rxdma) - si->dma_rx_buff_phy;
406
407 do {
408 /* Read Status, and then Data. */
409 stat = ICSR1;
410 rmb();
411 data = ICDR;
412
413 if (stat & (ICSR1_CRE | ICSR1_ROR)) {
414 dev->stats.rx_errors++;
415 if (stat & ICSR1_CRE) {
416 printk(KERN_DEBUG "pxa_ir: fir receive CRC error\n");
417 dev->stats.rx_crc_errors++;
418 }
419 if (stat & ICSR1_ROR) {
420 printk(KERN_DEBUG "pxa_ir: fir receive overrun\n");
421 dev->stats.rx_over_errors++;
422 }
423 } else {
424 si->dma_rx_buff[len++] = data;
425 }
426 /* If we hit the end of frame, there's no point in continuing. */
427 if (stat & ICSR1_EOF)
428 break;
429 } while (ICSR0 & ICSR0_EIF);
430
431 if (stat & ICSR1_EOF) {
432 /* end of frame. */
433 struct sk_buff *skb;
434
435 if (icsr0 & ICSR0_FRE) {
436 printk(KERN_ERR "pxa_ir: dropping erroneous frame\n");
437 dev->stats.rx_dropped++;
438 return;
439 }
440
441 skb = alloc_skb(len+1,GFP_ATOMIC);
442 if (!skb) {
443 printk(KERN_ERR "pxa_ir: fir out of memory for receive skb\n");
444 dev->stats.rx_dropped++;
445 return;
446 }
447
448 /* Align IP header to 20 bytes */
449 skb_reserve(skb, 1);
450 skb_copy_to_linear_data(skb, si->dma_rx_buff, len);
451 skb_put(skb, len);
452
453 /* Feed it to IrLAP */
454 skb->dev = dev;
455 skb_reset_mac_header(skb);
456 skb->protocol = htons(ETH_P_IRDA);
457 netif_rx(skb);
458
459 dev->stats.rx_packets++;
460 dev->stats.rx_bytes += len;
461 }
462 }
463
464 /* FIR interrupt handler */
465 static irqreturn_t pxa_irda_fir_irq(int irq, void *dev_id)
466 {
467 struct net_device *dev = dev_id;
468 struct pxa_irda *si = netdev_priv(dev);
469 int icsr0, i = 64;
470
471 /* stop RX DMA */
472 DCSR(si->rxdma) &= ~DCSR_RUN;
473 si->last_oscr = OSCR;
474 icsr0 = ICSR0;
475
476 if (icsr0 & (ICSR0_FRE | ICSR0_RAB)) {
477 if (icsr0 & ICSR0_FRE) {
478 printk(KERN_DEBUG "pxa_ir: fir receive frame error\n");
479 dev->stats.rx_frame_errors++;
480 } else {
481 printk(KERN_DEBUG "pxa_ir: fir receive abort\n");
482 dev->stats.rx_errors++;
483 }
484 ICSR0 = icsr0 & (ICSR0_FRE | ICSR0_RAB);
485 }
486
487 if (icsr0 & ICSR0_EIF) {
488 /* An error in FIFO occurred, or there is a end of frame */
489 pxa_irda_fir_irq_eif(si, dev, icsr0);
490 }
491
492 ICCR0 = 0;
493 pxa_irda_fir_dma_rx_start(si);
494 while ((ICSR1 & ICSR1_RNE) && i--)
495 (void)ICDR;
496 ICCR0 = ICCR0_ITR | ICCR0_RXE;
497
498 if (i < 0)
499 printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n");
500
501 return IRQ_HANDLED;
502 }
503
504 /* hard_xmit interface of irda device */
505 static int pxa_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
506 {
507 struct pxa_irda *si = netdev_priv(dev);
508 int speed = irda_get_next_speed(skb);
509
510 /*
511 * Does this packet contain a request to change the interface
512 * speed? If so, remember it until we complete the transmission
513 * of this frame.
514 */
515 if (speed != si->speed && speed != -1)
516 si->newspeed = speed;
517
518 /*
519 * If this is an empty frame, we can bypass a lot.
520 */
521 if (skb->len == 0) {
522 if (si->newspeed) {
523 si->newspeed = 0;
524 pxa_irda_set_speed(si, speed);
525 }
526 dev_kfree_skb(skb);
527 return NETDEV_TX_OK;
528 }
529
530 netif_stop_queue(dev);
531
532 if (!IS_FIR(si)) {
533 si->tx_buff.data = si->tx_buff.head;
534 si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data, si->tx_buff.truesize);
535
536 /* Disable STUART interrupts and switch to transmit mode. */
537 STIER = 0;
538 STISR = IrSR_IR_TRANSMIT_ON | IrSR_XMODE_PULSE_1_6;
539
540 /* enable STUART and transmit interrupts */
541 STIER = IER_UUE | IER_TIE;
542 } else {
543 unsigned long mtt = irda_get_mtt(skb);
544
545 si->dma_tx_buff_len = skb->len;
546 skb_copy_from_linear_data(skb, si->dma_tx_buff, skb->len);
547
548 if (mtt)
549 while ((unsigned)(OSCR - si->last_oscr)/4 < mtt)
550 cpu_relax();
551
552 /* stop RX DMA, disable FICP */
553 DCSR(si->rxdma) &= ~DCSR_RUN;
554 ICCR0 = 0;
555
556 pxa_irda_fir_dma_tx_start(si);
557 ICCR0 = ICCR0_ITR | ICCR0_TXE;
558 }
559
560 dev_kfree_skb(skb);
561 return NETDEV_TX_OK;
562 }
563
564 static int pxa_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
565 {
566 struct if_irda_req *rq = (struct if_irda_req *)ifreq;
567 struct pxa_irda *si = netdev_priv(dev);
568 int ret;
569
570 switch (cmd) {
571 case SIOCSBANDWIDTH:
572 ret = -EPERM;
573 if (capable(CAP_NET_ADMIN)) {
574 /*
575 * We are unable to set the speed if the
576 * device is not running.
577 */
578 if (netif_running(dev)) {
579 ret = pxa_irda_set_speed(si,
580 rq->ifr_baudrate);
581 } else {
582 printk(KERN_INFO "pxa_ir: SIOCSBANDWIDTH: !netif_running\n");
583 ret = 0;
584 }
585 }
586 break;
587
588 case SIOCSMEDIABUSY:
589 ret = -EPERM;
590 if (capable(CAP_NET_ADMIN)) {
591 irda_device_set_media_busy(dev, TRUE);
592 ret = 0;
593 }
594 break;
595
596 case SIOCGRECEIVING:
597 ret = 0;
598 rq->ifr_receiving = IS_FIR(si) ? 0
599 : si->rx_buff.state != OUTSIDE_FRAME;
600 break;
601
602 default:
603 ret = -EOPNOTSUPP;
604 break;
605 }
606
607 return ret;
608 }
609
610 static void pxa_irda_startup(struct pxa_irda *si)
611 {
612 /* Disable STUART interrupts */
613 STIER = 0;
614 /* enable STUART interrupt to the processor */
615 STMCR = MCR_OUT2;
616 /* configure SIR frame format: StartBit - Data 7 ... Data 0 - Stop Bit */
617 STLCR = LCR_WLS0 | LCR_WLS1;
618 /* enable FIFO, we use FIFO to improve performance */
619 STFCR = FCR_TRFIFOE | FCR_ITL_32;
620
621 /* disable FICP */
622 ICCR0 = 0;
623 /* configure FICP ICCR2 */
624 ICCR2 = ICCR2_TXP | ICCR2_TRIG_32;
625
626 /* configure DMAC */
627 DRCMR(17) = si->rxdma | DRCMR_MAPVLD;
628 DRCMR(18) = si->txdma | DRCMR_MAPVLD;
629
630 /* force SIR reinitialization */
631 si->speed = 4000000;
632 pxa_irda_set_speed(si, 9600);
633
634 printk(KERN_DEBUG "pxa_ir: irda startup\n");
635 }
636
637 static void pxa_irda_shutdown(struct pxa_irda *si)
638 {
639 unsigned long flags;
640
641 local_irq_save(flags);
642
643 /* disable STUART and interrupt */
644 STIER = 0;
645 /* disable STUART SIR mode */
646 STISR = 0;
647
648 /* disable DMA */
649 DCSR(si->txdma) &= ~DCSR_RUN;
650 DCSR(si->rxdma) &= ~DCSR_RUN;
651 /* disable FICP */
652 ICCR0 = 0;
653
654 /* disable the STUART or FICP clocks */
655 pxa_irda_disable_clk(si);
656
657 DRCMR(17) = 0;
658 DRCMR(18) = 0;
659
660 local_irq_restore(flags);
661
662 /* power off board transceiver */
663 pxa_irda_set_mode(si, IR_OFF);
664
665 printk(KERN_DEBUG "pxa_ir: irda shutdown\n");
666 }
667
668 static int pxa_irda_start(struct net_device *dev)
669 {
670 struct pxa_irda *si = netdev_priv(dev);
671 int err;
672
673 si->speed = 9600;
674
675 err = request_irq(IRQ_STUART, pxa_irda_sir_irq, 0, dev->name, dev);
676 if (err)
677 goto err_irq1;
678
679 err = request_irq(IRQ_ICP, pxa_irda_fir_irq, 0, dev->name, dev);
680 if (err)
681 goto err_irq2;
682
683 /*
684 * The interrupt must remain disabled for now.
685 */
686 disable_irq(IRQ_STUART);
687 disable_irq(IRQ_ICP);
688
689 err = -EBUSY;
690 si->rxdma = pxa_request_dma("FICP_RX",DMA_PRIO_LOW, pxa_irda_fir_dma_rx_irq, dev);
691 if (si->rxdma < 0)
692 goto err_rx_dma;
693
694 si->txdma = pxa_request_dma("FICP_TX",DMA_PRIO_LOW, pxa_irda_fir_dma_tx_irq, dev);
695 if (si->txdma < 0)
696 goto err_tx_dma;
697
698 err = -ENOMEM;
699 si->dma_rx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT,
700 &si->dma_rx_buff_phy, GFP_KERNEL );
701 if (!si->dma_rx_buff)
702 goto err_dma_rx_buff;
703
704 si->dma_tx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT,
705 &si->dma_tx_buff_phy, GFP_KERNEL );
706 if (!si->dma_tx_buff)
707 goto err_dma_tx_buff;
708
709 /* Setup the serial port for the initial speed. */
710 pxa_irda_startup(si);
711
712 /*
713 * Open a new IrLAP layer instance.
714 */
715 si->irlap = irlap_open(dev, &si->qos, "pxa");
716 err = -ENOMEM;
717 if (!si->irlap)
718 goto err_irlap;
719
720 /*
721 * Now enable the interrupt and start the queue
722 */
723 enable_irq(IRQ_STUART);
724 enable_irq(IRQ_ICP);
725 netif_start_queue(dev);
726
727 printk(KERN_DEBUG "pxa_ir: irda driver opened\n");
728
729 return 0;
730
731 err_irlap:
732 pxa_irda_shutdown(si);
733 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy);
734 err_dma_tx_buff:
735 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy);
736 err_dma_rx_buff:
737 pxa_free_dma(si->txdma);
738 err_tx_dma:
739 pxa_free_dma(si->rxdma);
740 err_rx_dma:
741 free_irq(IRQ_ICP, dev);
742 err_irq2:
743 free_irq(IRQ_STUART, dev);
744 err_irq1:
745
746 return err;
747 }
748
749 static int pxa_irda_stop(struct net_device *dev)
750 {
751 struct pxa_irda *si = netdev_priv(dev);
752
753 netif_stop_queue(dev);
754
755 pxa_irda_shutdown(si);
756
757 /* Stop IrLAP */
758 if (si->irlap) {
759 irlap_close(si->irlap);
760 si->irlap = NULL;
761 }
762
763 free_irq(IRQ_STUART, dev);
764 free_irq(IRQ_ICP, dev);
765
766 pxa_free_dma(si->rxdma);
767 pxa_free_dma(si->txdma);
768
769 if (si->dma_rx_buff)
770 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy);
771 if (si->dma_tx_buff)
772 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy);
773
774 printk(KERN_DEBUG "pxa_ir: irda driver closed\n");
775 return 0;
776 }
777
778 static int pxa_irda_suspend(struct platform_device *_dev, pm_message_t state)
779 {
780 struct net_device *dev = platform_get_drvdata(_dev);
781 struct pxa_irda *si;
782
783 if (dev && netif_running(dev)) {
784 si = netdev_priv(dev);
785 netif_device_detach(dev);
786 pxa_irda_shutdown(si);
787 }
788
789 return 0;
790 }
791
792 static int pxa_irda_resume(struct platform_device *_dev)
793 {
794 struct net_device *dev = platform_get_drvdata(_dev);
795 struct pxa_irda *si;
796
797 if (dev && netif_running(dev)) {
798 si = netdev_priv(dev);
799 pxa_irda_startup(si);
800 netif_device_attach(dev);
801 netif_wake_queue(dev);
802 }
803
804 return 0;
805 }
806
807
808 static int pxa_irda_init_iobuf(iobuff_t *io, int size)
809 {
810 io->head = kmalloc(size, GFP_KERNEL | GFP_DMA);
811 if (io->head != NULL) {
812 io->truesize = size;
813 io->in_frame = FALSE;
814 io->state = OUTSIDE_FRAME;
815 io->data = io->head;
816 }
817 return io->head ? 0 : -ENOMEM;
818 }
819
820 static const struct net_device_ops pxa_irda_netdev_ops = {
821 .ndo_open = pxa_irda_start,
822 .ndo_stop = pxa_irda_stop,
823 .ndo_start_xmit = pxa_irda_hard_xmit,
824 .ndo_do_ioctl = pxa_irda_ioctl,
825 };
826
827 static int pxa_irda_probe(struct platform_device *pdev)
828 {
829 struct net_device *dev;
830 struct pxa_irda *si;
831 unsigned int baudrate_mask;
832 int err;
833
834 if (!pdev->dev.platform_data)
835 return -ENODEV;
836
837 err = request_mem_region(__PREG(STUART), 0x24, "IrDA") ? 0 : -EBUSY;
838 if (err)
839 goto err_mem_1;
840
841 err = request_mem_region(__PREG(FICP), 0x1c, "IrDA") ? 0 : -EBUSY;
842 if (err)
843 goto err_mem_2;
844
845 dev = alloc_irdadev(sizeof(struct pxa_irda));
846 if (!dev)
847 goto err_mem_3;
848
849 SET_NETDEV_DEV(dev, &pdev->dev);
850 si = netdev_priv(dev);
851 si->dev = &pdev->dev;
852 si->pdata = pdev->dev.platform_data;
853
854 si->sir_clk = clk_get(&pdev->dev, "UARTCLK");
855 si->fir_clk = clk_get(&pdev->dev, "FICPCLK");
856 if (IS_ERR(si->sir_clk) || IS_ERR(si->fir_clk)) {
857 err = PTR_ERR(IS_ERR(si->sir_clk) ? si->sir_clk : si->fir_clk);
858 goto err_mem_4;
859 }
860
861 /*
862 * Initialise the SIR buffers
863 */
864 err = pxa_irda_init_iobuf(&si->rx_buff, 14384);
865 if (err)
866 goto err_mem_4;
867 err = pxa_irda_init_iobuf(&si->tx_buff, 4000);
868 if (err)
869 goto err_mem_5;
870
871 if (gpio_is_valid(si->pdata->gpio_pwdown)) {
872 err = gpio_request(si->pdata->gpio_pwdown, "IrDA switch");
873 if (err)
874 goto err_startup;
875 err = gpio_direction_output(si->pdata->gpio_pwdown,
876 !si->pdata->gpio_pwdown_inverted);
877 if (err) {
878 gpio_free(si->pdata->gpio_pwdown);
879 goto err_startup;
880 }
881 }
882
883 if (si->pdata->startup) {
884 err = si->pdata->startup(si->dev);
885 if (err)
886 goto err_startup;
887 }
888
889 if (gpio_is_valid(si->pdata->gpio_pwdown) && si->pdata->startup)
890 dev_warn(si->dev, "gpio_pwdown and startup() both defined!\n");
891
892 dev->netdev_ops = &pxa_irda_netdev_ops;
893
894 irda_init_max_qos_capabilies(&si->qos);
895
896 baudrate_mask = 0;
897 if (si->pdata->transceiver_cap & IR_SIRMODE)
898 baudrate_mask |= IR_9600|IR_19200|IR_38400|IR_57600|IR_115200;
899 if (si->pdata->transceiver_cap & IR_FIRMODE)
900 baudrate_mask |= IR_4000000 << 8;
901
902 si->qos.baud_rate.bits &= baudrate_mask;
903 si->qos.min_turn_time.bits = 7; /* 1ms or more */
904
905 irda_qos_bits_to_value(&si->qos);
906
907 err = register_netdev(dev);
908
909 if (err == 0)
910 dev_set_drvdata(&pdev->dev, dev);
911
912 if (err) {
913 if (si->pdata->shutdown)
914 si->pdata->shutdown(si->dev);
915 err_startup:
916 kfree(si->tx_buff.head);
917 err_mem_5:
918 kfree(si->rx_buff.head);
919 err_mem_4:
920 if (si->sir_clk && !IS_ERR(si->sir_clk))
921 clk_put(si->sir_clk);
922 if (si->fir_clk && !IS_ERR(si->fir_clk))
923 clk_put(si->fir_clk);
924 free_netdev(dev);
925 err_mem_3:
926 release_mem_region(__PREG(FICP), 0x1c);
927 err_mem_2:
928 release_mem_region(__PREG(STUART), 0x24);
929 }
930 err_mem_1:
931 return err;
932 }
933
934 static int pxa_irda_remove(struct platform_device *_dev)
935 {
936 struct net_device *dev = platform_get_drvdata(_dev);
937
938 if (dev) {
939 struct pxa_irda *si = netdev_priv(dev);
940 unregister_netdev(dev);
941 if (gpio_is_valid(si->pdata->gpio_pwdown))
942 gpio_free(si->pdata->gpio_pwdown);
943 if (si->pdata->shutdown)
944 si->pdata->shutdown(si->dev);
945 kfree(si->tx_buff.head);
946 kfree(si->rx_buff.head);
947 clk_put(si->fir_clk);
948 clk_put(si->sir_clk);
949 free_netdev(dev);
950 }
951
952 release_mem_region(__PREG(STUART), 0x24);
953 release_mem_region(__PREG(FICP), 0x1c);
954
955 return 0;
956 }
957
958 static struct platform_driver pxa_ir_driver = {
959 .driver = {
960 .name = "pxa2xx-ir",
961 .owner = THIS_MODULE,
962 },
963 .probe = pxa_irda_probe,
964 .remove = pxa_irda_remove,
965 .suspend = pxa_irda_suspend,
966 .resume = pxa_irda_resume,
967 };
968
969 module_platform_driver(pxa_ir_driver);
970
971 MODULE_LICENSE("GPL");
972 MODULE_ALIAS("platform:pxa2xx-ir");