drivers/hwmon/xilinx-xadcps.c

   1 /*
   2  * drivers/hwmon/xilinx-xadcps.c - Xilinx Zynq XADC support
   3  *
   4  * Copyright (c) 2012 Wind River Systems, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License v2 as published by the
   8  * Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/err.h>
  22 #include <linux/kernel.h>
  23 #include <linux/slab.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/sysfs.h>
  27 #include <linux/kobject.h>
  28 #include <linux/io.h>
  29 #include <linux/spinlock.h>
  30
  31 #include <linux/hwmon.h>
  32 #include <linux/hwmon-sysfs.h>
  33
  34 /*XADC interface register offsets*/
  35 #define XADC_CONFIG     0x00
  36 #define XADC_INTSTS     0x04
  37 #define XADC_INTMSK     0x08
  38 #define XADC_STATUS     0x0C
  39 #define XADC_CFIFO      0x10
  40 #define XADC_DFIFO      0x14
  41 #define XADC_CTL        0x18
  42
  43 /*XADC interface register fields*/
  44 #define XADC_CONFIG_ENABLE              (1<<31)
  45 #define XADC_CONFIG_CFIFOTH_MSK         0xF
  46 #define XADC_CONFIG_CFIFOTH_SHIFT       20
  47 #define XADC_CONFIG_DFIFOTH_MSK         0xF
  48 #define XADC_CONFIG_DFIFOTH_SHIFT       16
  49 #define XADC_CONFIG_WEDGE               (1<<13)
  50 #define XADC_CONFIG_REDGE               (1<<12)
  51 #define XADC_CONFIG_TCKRATE_MSK         0x3
  52 #define XADC_CONFIG_TCKRATE_SHIFT       8
  53 #define XADC_CONFIG_IGAP_MSK            0x1F
  54 #define XADC_CONFIG_IGAP_SHIFT          0
  55
  56 #define TCKRATE_DIV2                    0
  57 #define TCKRATE_DIV4                    1
  58 #define TCKRATE_DIV8                    2
  59 #define TCKRATE_DIV16                   3
  60
  61 #define XADC_INT_CFIFO_LTH              (1<<9)
  62 #define XADC_INT_DFIFO_GTH              (1<<8)
  63 #define XADC_INT_OT                     (1<<7)
  64
  65 #define XADC_STATUS_CFIFO_LVL_MSK       0xF
  66 #define XADC_STATUS_CFIFO_LVL_SHIFT     16
  67 #define XADC_STATUS_DFIFO_LVL_MSK       0xF
  68 #define XADC_STATUS_DFIFO_LVL_SHIFT     12
  69 #define XADC_STATUS_CFIFO_FULL          (1<<11)
  70 #define XADC_STATUS_CFIFO_EMPTY         (1<<10)
  71 #define XADC_STATUS_DFIFO_FULL          (1<<9)
  72 #define XADC_STATUS_DFIFO_EMPTY         (1<<8)
  73 #define XADC_STATUS_OT                  (1<<7)
  74
  75 #define XADC_CTL_RESET                  (1<<4)
  76
  77 #define XADC_FIFO_CMD_MSK               0x0F
  78 #define XADC_FIFO_CMD_SHIFT             26
  79 #define XADC_FIFO_ADDR_MSK              0x3FF
  80 #define XADC_FIFO_ADDR_SHIFT            16
  81 #define XADC_FIFO_DATA_MSK              0xFFFF
  82 #define XADC_FIFO_DATA_SHIFT            0
  83
  84 /*XADC commands*/
  85 #define XADC_CMD_NOP                    0
  86 #define XADC_CMD_READ                   1
  87 #define XADC_CMD_WRITE                  2
  88
  89 /*XADC register offsets*/
  90 #define REG_TEMP                0x00
  91 #define REG_VCCINT              0x01
  92 #define REG_VCCAUX              0x02
  93 #define REG_VPVN                0x03
  94 #define REG_VREFP               0x04
  95 #define REG_VREFN               0x05
  96 #define REG_VCCBRAM             0x06
  97
  98 #define REG_VAUX0               0x10
  99
 100 #define REG_MAX_TEMP            0x20
 101 #define REG_MAX_VCCINT          0x21
 102 #define REG_MAX_VCCAUX          0x22
 103 #define REG_MAX_VCCBRAM         0x23
 104 #define REG_MIN_TEMP            0x24
 105 #define REG_MIN_VCCINT          0x25
 106 #define REG_MIN_VCCAUX          0x26
 107 #define REG_MIN_VCCBRAM         0x27
 108
 109 #define REG_FLAG                0x3F
 110 #define REG_CFG0                0x40
 111 #define REG_CFG1                0x41
 112 #define REG_CFG2                0x42
 113
 114 #define REG_SEQ_SEL0            0x48
 115 #define REG_SEQ_SEL1            0x49
 116 #define REG_SEQ_AVG0            0x4A
 117 #define REG_SEQ_AVG1            0x4B
 118 #define REG_SEQ_BIP0            0x4C
 119 #define REG_SEQ_BIP1            0x4D
 120 #define REG_SEQ_ACQ0            0x4E
 121 #define REG_SEQ_ACQ1            0x4F
 122
 123 /*XADC register fields*/
 124 #define REG_CFG1_CAL_ADCO       (1<<4)  /*ADC offset*/
 125 #define REG_CFG1_CAL_ADCOG      (1<<5)  /*ADC offset & gain*/
 126 #define REG_CFG1_CAL_SSO        (1<<6)  /*Supply sensor offset*/
 127 #define REG_CFG1_CAL_SSOG       (1<<7)  /*supply sensor offset &gain*/
 128
 129
 130 #define REG_CFG1_SEQ_MSK        0x0F
 131 #define REG_CFG1_SEQ_SHIFT      12
 132
 133 #define MODE_DEF                0       /*Internal sensors, no alarms*/
 134 #define MODE_1PASS              1       /*Single pass*/
 135 #define MODE_CONTINUOUS         2       /*Continuous*/
 136 #define MODE_1CHAN              3       /*Single channel*/
 137 #define MODE_SIM                4       /*Simultaneous AUX0/8, AUX1/9, ...*/
 138 #define MODE_IND                8       /*Independent:ADC A -int, ADC B -ext*/
 139
 140 #define REG_FLAG_DIS            1<<8
 141 #define REG_FLAG_REF            1<<9
 142
 143 /*Sequencer registers 0*/
 144 #define REG_SEQ_CAL             (1<<0)
 145 #define REG_SEQ_TEMP            (1<<8)
 146 #define REG_SEQ_VCCINT          (1<<9)
 147 #define REG_SEQ_VCCAUX          (1<<10)
 148 #define REG_SEQ_V               (1<<11)
 149 #define REG_SEQ_VREFP           (1<<12)
 150 #define REG_SEQ_VREFN           (1<<13)
 151 #define REG_SEQ_VCCBRAM         (1<<14)
 152
 153 /*Sequencer registers 1*/
 154 #define REG_SEQ_VAUX(i)         (1<<i)
 155
 156 #define READ(dev,reg) readl((dev->iobase+XADC_##reg))
 157 #define WRITE(dev,reg,value) writel(value, dev->iobase+XADC_##reg)
 158
 159 #define GETFIELD(reg,field,value) \
 160         (((value)>>(reg##_##field##_SHIFT)) &\
 161                 reg##_##field##_MSK)
 162
 163 #define SETFIELD(reg,field,value) \
 164         (((value)&reg##_##field##_MSK) <<\
 165                 reg##_##field##_SHIFT)
 166
 167 #define CLRFIELD(reg,field,value) \
 168         ((value)&~(reg##_##field##_MSK <<\
 169                 reg##_##field##_SHIFT))
 170
 171 #define READOP(reg) \
 172                 (SETFIELD(XADC_FIFO,CMD,XADC_CMD_READ) |\
 173                 SETFIELD(XADC_FIFO,ADDR,reg))
 174
 175 #define WRITEOP(reg,val) \
 176                 (SETFIELD(XADC_FIFO,CMD,XADC_CMD_WRITE) |\
 177                 SETFIELD(XADC_FIFO,ADDR,reg) |\
 178                 SETFIELD(XADC_FIFO,DATA,val))
 179
 180 #define NOOP \
 181                 (SETFIELD(XADC_FIFO,CMD,XADC_CMD_NOP))
 182
 183 struct xadc_op {
 184         u32 cmd;
 185         u32 res;
 186 };
 187
 188 struct xadc_batch {
 189         int count;
 190         int writeptr;
 191         int readptr;
 192         struct list_head q;
 193         struct completion comp;
 194         struct xadc_op ops[];
 195 };
 196
 197
 198 struct xadc_t {
 199         struct device *dev;
 200         struct device *hwmon;
 201         struct resource *mem;
 202         void __iomem *iobase;
 203         int irq;
 204         spinlock_t slock;
 205         struct list_head runq;
 206         struct xadc_batch *curr;
 207         u32 chanmode[17];       /*Channel 0-15 VAUX, 16 is V*/
 208         #define CHAN_ON         1
 209         #define CHAN_BIPOLAR    2
 210 };
 211
 212
 213 static void run_batch(struct xadc_t *xadc)
 214 {
 215         u32 config, rdt;
 216
 217         if (list_empty(&xadc->runq)) {
 218                 xadc->curr = NULL;
 219                 return;
 220                 }
 221         xadc->curr = list_first_entry(&xadc->runq, struct xadc_batch, q);
 222         list_del(&xadc->curr->q);
 223
 224         config = READ(xadc, CONFIG);
 225         config = CLRFIELD(XADC_CONFIG, CFIFOTH, config);
 226         config = CLRFIELD(XADC_CONFIG, DFIFOTH, config);
 227
 228         rdt = xadc->curr->count-xadc->curr->readptr;
 229         if (rdt > 15) /* Trigger at half FIFO or count*/
 230                 rdt = 8;
 231         else
 232                 rdt --;
 233
 234         config |=       SETFIELD(XADC_CONFIG,CFIFOTH, 0) | /*Just trigger*/
 235                         SETFIELD(XADC_CONFIG,DFIFOTH, rdt);
 236
 237         WRITE(xadc, CONFIG, config);
 238
 239         /*unmask CFIFO,DFIFO interrupts*/
 240         WRITE(xadc, INTMSK, READ(xadc, INTMSK) & ~
 241                 (XADC_INT_CFIFO_LTH|XADC_INT_DFIFO_GTH));
 242 }
 243
 244 static void add_batch(struct xadc_t *xadc, struct xadc_batch *b)
 245 {
 246         unsigned long flags;
 247
 248         BUG_ON(b->count < 1);
 249         b->writeptr = 0;
 250         b->readptr = 0;
 251         init_completion(&b->comp);
 252         list_add_tail(&b->q,&xadc->runq);
 253         spin_lock_irqsave(&xadc->slock, flags);
 254         if (!xadc->curr)
 255                 run_batch(xadc);
 256         spin_unlock_irqrestore(&xadc->slock, flags);
 257 }
 258
 259 static inline u16 read_register(struct xadc_t *xadc, unsigned int reg)
 260 {
 261         struct xadc_batch *b=kzalloc(sizeof(struct xadc_batch) +
 262                 2*sizeof(struct xadc_op), GFP_KERNEL);
 263         u16 ret;
 264
 265         if (NULL == b)
 266                 return 0;
 267         b->count = 2;
 268         b->ops[0].cmd = READOP(reg);
 269         b->ops[1].cmd = NOOP;
 270         add_batch(xadc, b);
 271         wait_for_completion_interruptible(&b->comp);
 272         ret = GETFIELD(XADC_FIFO, DATA, b->ops[1].res);
 273         kfree(b);
 274         return ret;
 275 }
 276
 277 static inline void write_register(struct xadc_t *xadc, unsigned int reg,
 278         u16 val)
 279 {
 280         struct xadc_batch *b=kzalloc(sizeof(struct xadc_batch) +
 281                 1*sizeof(struct xadc_op), GFP_KERNEL);
 282
 283         if (NULL == b)
 284                 return;
 285         b->count = 1;
 286         b->ops[0].cmd = WRITEOP(reg, val);
 287         add_batch(xadc, b);
 288         wait_for_completion_interruptible(&b->comp);
 289         kfree(b);
 290 }
 291
 292 static inline unsigned reg2temp (u16 reg)
 293 {
 294         unsigned val;
 295
 296         val = (reg >> 4) & 0xFFF; /*Use only 12 bits*/
 297         val = ((val * 503975)/4096) - 273150; /* (X*503.975/4096) -273.15 */
 298         val = DIV_ROUND_CLOSEST(val,1000);
 299         return val;
 300 }
 301
 302 static inline unsigned reg2vcc (u16 reg)
 303 {
 304         unsigned val;
 305
 306         val = (reg >> 4) & 0xFFF; /*Use only 12 bits*/
 307         val = ((val * 3000)/4096); /* (X*3/4096)*/
 308         /*Return voltage in mV*/
 309         return val;
 310 }
 311
 312 static inline unsigned reg2v (u16 reg)
 313 {
 314         unsigned val;
 315
 316         val = (reg >> 4) & 0xFFF; /*Use only 12 bits*/
 317         val = (val*1000/4096); /* (X/4096)*/
 318         /*Return voltage in mV*/
 319         return val;
 320 }
 321
 322 static inline int reg2bv (u16 reg)
 323 {
 324         int val;
 325
 326         val = (reg >> 4) & 0xFFF; /*Use only 12 bits*/
 327         if (val & 0x800)
 328                 val = val - 0x1000;
 329         val = (val*1000/4096); /* (X/4096)*/
 330         /*Return voltage in mV*/
 331         return val;
 332 }
 333
 334 static ssize_t xadc_read_temp(struct device *dev,
 335                 struct device_attribute *devattr, char *buf)
 336 {
 337         struct platform_device *pdev = to_platform_device(dev);
 338         struct xadc_t *xadc = platform_get_drvdata(pdev);
 339         struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
 340         unsigned int reg = attr->index;
 341
 342         return sprintf(buf, "%u\n", reg2temp(read_register(xadc, reg)));
 343 }
 344
 345 static ssize_t xadc_read_vcc(struct device *dev,
 346                 struct device_attribute *devattr, char *buf)
 347 {
 348         struct platform_device *pdev = to_platform_device(dev);
 349         struct xadc_t *xadc = platform_get_drvdata(pdev);
 350         struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
 351         unsigned int reg = attr->index;
 352
 353         return sprintf(buf, "%u\n", reg2vcc(read_register(xadc, reg)));
 354 }
 355
 356 static ssize_t xadc_read_v(struct device *dev,
 357                 struct device_attribute *devattr, char *buf)
 358 {
 359         struct platform_device *pdev = to_platform_device(dev);
 360         struct xadc_t *xadc = platform_get_drvdata(pdev);
 361         struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
 362         unsigned int reg = attr->index;
 363         unsigned int chan = attr->nr;
 364
 365         if (!(xadc->chanmode[chan]&CHAN_ON))
 366                 return sprintf(buf, "%d\n", 0);
 367         if ((xadc->chanmode[chan]&CHAN_BIPOLAR))
 368                 return sprintf(buf, "%d\n", reg2bv(read_register(xadc, reg)));
 369         return sprintf(buf, "%u\n", reg2v(read_register(xadc, reg)));
 370 }
 371
 372 #ifdef DEBUG
 373 static ssize_t xadc_read_registers(struct device *dev,
 374                 struct device_attribute *devattr, char *buf)
 375 {
 376         struct platform_device *pdev = to_platform_device(dev);
 377         struct xadc_t *xadc = platform_get_drvdata(pdev);
 378         unsigned int i,count=0;
 379
 380         for (i=0;i<0x60;i++)
 381                 count +=sprintf(buf+count, \
 382                         "%02X %04x\n", i, read_register(xadc, i));
 383         return count;
 384 }
 385 #endif
 386
 387 static ssize_t xadc_read_flags(struct device *dev,
 388                 struct device_attribute *devattr, char *buf)
 389 {
 390         struct platform_device *pdev = to_platform_device(dev);
 391         struct xadc_t *xadc = platform_get_drvdata(pdev);
 392
 393         u16 val = read_register(xadc, REG_FLAG);
 394
 395         return sprintf(buf, "enabled:\t%s\nreference:\t%s\n",
 396                 val&REG_FLAG_DIS?"no":"yes",
 397                 val&REG_FLAG_REF?"internal":"external");
 398 }
 399
 400 static ssize_t xadc_read_vmode(struct device *dev,
 401                 struct device_attribute *devattr, char *buf)
 402 {
 403         struct platform_device *pdev = to_platform_device(dev);
 404         struct xadc_t *xadc = platform_get_drvdata(pdev);
 405         struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
 406         unsigned int channel = attr->nr;
 407
 408         return sprintf(buf, "%s\n",
 409                 (xadc->chanmode[channel] & CHAN_ON) ?\
 410                         ((xadc->chanmode[channel] & CHAN_BIPOLAR) ? \
 411                                 "bipolar":"unipolar")
 412                         : "off");
 413 }
 414
 415 static ssize_t xadc_write_vmode(struct device *dev,
 416                 struct device_attribute *devattr,
 417                 const char *buf, size_t count)
 418 {
 419         struct platform_device *pdev = to_platform_device(dev);
 420         struct xadc_t *xadc = platform_get_drvdata(pdev);
 421         struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
 422         unsigned int channel = attr->nr;
 423         unsigned int reg = attr->index;
 424         u32 mode;
 425         u16 val;
 426
 427         if (!strncmp("off",buf,3)) {
 428                 mode = 0;
 429                 goto end;
 430                 }
 431
 432         if (!strncmp("unipolar",buf,8)) {
 433                 mode = CHAN_ON;
 434                 goto end;
 435                 }
 436
 437         if (!strncmp("bipolar",buf,7)) {
 438                 mode = CHAN_ON | CHAN_BIPOLAR;
 439                 goto end;
 440                 }
 441
 442         return -EIO;
 443 end:
 444         if (mode == xadc->chanmode[channel])
 445                 return count;
 446
 447         xadc->chanmode[channel] = mode;
 448
 449         if (mode & CHAN_BIPOLAR) {
 450                 val = read_register(xadc, reg + REG_SEQ_BIP0);
 451                 if (0 == reg) /*only dedicated channel there*/
 452                         val |= REG_SEQ_V;
 453                         else
 454                         val |= (1<<channel);
 455                 write_register(xadc, reg + REG_SEQ_BIP0, val);
 456                 } else {
 457                 val = read_register(xadc, reg + REG_SEQ_BIP0);
 458                 if (0 == reg) /*only dedicated channel there*/
 459                         val &= ~REG_SEQ_V;
 460                         else
 461                         val &= ~(1<<channel);
 462                 write_register(xadc, reg + REG_SEQ_BIP0, val);
 463                 }
 464
 465         if (mode & CHAN_ON) {
 466                 val = read_register(xadc, reg + REG_SEQ_SEL0);
 467                 if (0 == reg) /*only dedicated channel there*/
 468                         val |= REG_SEQ_V;
 469                         else
 470                         val |= (1<<channel);
 471                 write_register(xadc, reg + REG_SEQ_SEL0, val);
 472                 } else {
 473                 val = read_register(xadc, reg + REG_SEQ_SEL0);
 474                 if (0 == reg) /*only dedicated channel there*/
 475                         val &= ~REG_SEQ_V;
 476                         else
 477                         val &= ~(1<<channel);
 478                 write_register(xadc, reg + REG_SEQ_SEL0, val);
 479                 }
 480
 481         return count;
 482 }
 483
 484 static ssize_t show_name(struct device *dev,
 485                 struct device_attribute *devattr, char *buf)
 486 {
 487
 488         return sprintf(buf, "%s\n","xadcps");
 489 }
 490
 491 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
 492
 493 static SENSOR_DEVICE_ATTR(status, S_IRUGO, xadc_read_flags, \
 494         NULL, 0);
 495 static SENSOR_DEVICE_ATTR(temp, S_IRUGO, xadc_read_temp, \
 496         NULL, REG_TEMP);
 497 static SENSOR_DEVICE_ATTR(temp_min, S_IRUGO, xadc_read_temp, \
 498         NULL, REG_MIN_TEMP);
 499 static SENSOR_DEVICE_ATTR(temp_max, S_IRUGO, xadc_read_temp, \
 500         NULL, REG_MAX_TEMP);
 501 static SENSOR_DEVICE_ATTR(vccint, S_IRUGO, xadc_read_vcc, \
 502         NULL, REG_VCCINT);
 503 static SENSOR_DEVICE_ATTR(vccint_min, S_IRUGO, xadc_read_vcc, \
 504         NULL, REG_MIN_VCCINT);
 505 static SENSOR_DEVICE_ATTR(vccint_max, S_IRUGO, xadc_read_vcc, \
 506         NULL, REG_MAX_VCCINT);
 507 static SENSOR_DEVICE_ATTR(vccaux, S_IRUGO, xadc_read_vcc, \
 508         NULL, REG_VCCAUX);
 509 static SENSOR_DEVICE_ATTR(vccaux_min, S_IRUGO, xadc_read_vcc, \
 510         NULL, REG_MIN_VCCAUX);
 511 static SENSOR_DEVICE_ATTR(vccaux_max, S_IRUGO, xadc_read_vcc, \
 512         NULL, REG_MAX_VCCAUX);
 513 static SENSOR_DEVICE_ATTR(vccbram, S_IRUGO, xadc_read_vcc, \
 514         NULL, REG_VCCBRAM);
 515 static SENSOR_DEVICE_ATTR(vccbram_min, S_IRUGO, xadc_read_vcc, \
 516         NULL, REG_MIN_VCCBRAM);
 517 static SENSOR_DEVICE_ATTR(vccbram_max, S_IRUGO, xadc_read_vcc, \
 518         NULL, REG_MAX_VCCBRAM);
 519 /*
 520  *channel number, register
 521  *for VPVN  = 16, REG_VPVN
 522  *for VAUXi =  i, REG_VAUX0 + i
 523  */
 524 static SENSOR_DEVICE_ATTR_2(v, S_IRUGO, xadc_read_v, \
 525         NULL, 16, REG_VPVN);
 526 /*channel number, offset from REG_SEQ_xxx_0
 527  *for VPVN  = 16, 0
 528  *for VAUXi =  i, 1
 529  */
 530 static SENSOR_DEVICE_ATTR_2(v_mode, S_IWUSR|S_IRUGO, xadc_read_vmode, \
 531         xadc_write_vmode, 16, 0);
 532 #ifdef DEBUG
 533 static SENSOR_DEVICE_ATTR(registers, S_IRUGO, xadc_read_registers, \
 534         NULL, 0);
 535 #endif
 536
 537 static struct attribute *xadc_attr[] = {
 538         &dev_attr_name.attr,
 539 #ifdef DEBUG
 540         &sensor_dev_attr_registers.dev_attr.attr,
 541 #endif
 542         &sensor_dev_attr_status.dev_attr.attr,
 543         &sensor_dev_attr_temp.dev_attr.attr,
 544         &sensor_dev_attr_temp_min.dev_attr.attr,
 545         &sensor_dev_attr_temp_max.dev_attr.attr,
 546         &sensor_dev_attr_vccint.dev_attr.attr,
 547         &sensor_dev_attr_vccint_min.dev_attr.attr,
 548         &sensor_dev_attr_vccint_max.dev_attr.attr,
 549         &sensor_dev_attr_vccaux.dev_attr.attr,
 550         &sensor_dev_attr_vccaux_min.dev_attr.attr,
 551         &sensor_dev_attr_vccaux_max.dev_attr.attr,
 552         &sensor_dev_attr_vccbram.dev_attr.attr,
 553         &sensor_dev_attr_vccbram_min.dev_attr.attr,
 554         &sensor_dev_attr_vccbram_max.dev_attr.attr,
 555         &sensor_dev_attr_v.dev_attr.attr,
 556         &sensor_dev_attr_v_mode.dev_attr.attr,
 557         NULL
 558 };
 559
 560
 561
 562 static const struct attribute_group xadc_group = {
 563         .attrs = xadc_attr,
 564 };
 565
 566 static irqreturn_t xadc_irq(int irq, void *data)
 567 {
 568         struct xadc_t *xadc = data;
 569         u32 intsts, intmsk;
 570
 571
 572         intsts = READ(xadc, INTSTS);
 573         intmsk = READ(xadc, INTMSK);
 574         dev_dbg(xadc->dev, "intsts %08x intmsk %08x\n", intsts, intmsk);
 575
 576         if (intsts & ~intmsk & XADC_INT_DFIFO_GTH) {
 577
 578                 while (!(READ(xadc, STATUS) & XADC_STATUS_DFIFO_EMPTY))
 579                         xadc->curr->ops[xadc->curr->readptr++].res =
 580                                 READ(xadc, DFIFO);
 581                 if ((xadc->curr->readptr) == xadc->curr->count) {
 582                                 intmsk |= XADC_INT_DFIFO_GTH;
 583                                 WRITE(xadc, INTMSK, intmsk);
 584                                 complete(&xadc->curr->comp);
 585                                 run_batch(xadc);
 586                         } else {
 587                                 u32 config;
 588                                 int rdt;
 589
 590                                 config = READ(xadc, CONFIG);
 591                                 config = CLRFIELD(XADC_CONFIG, \
 592                                         DFIFOTH, config);
 593                                 rdt = xadc->curr->count-xadc->curr->readptr;
 594                                 if (rdt > 15)
 595                                         rdt = 8;
 596                                         else
 597                                         rdt --;
 598                                 config |= SETFIELD(XADC_CONFIG, DFIFOTH, rdt);
 599                                 WRITE(xadc, CONFIG, config);
 600                         }
 601                 WRITE(xadc, INTSTS, XADC_INT_DFIFO_GTH);
 602                 }
 603
 604         if (intsts & ~intmsk & XADC_INT_CFIFO_LTH) {
 605                 int i, towrite;
 606                 u32 status = READ(xadc, STATUS);
 607
 608                 /*Don't write more than FIFO capacity*/
 609                 towrite = xadc->curr->count - xadc->curr->writeptr;
 610                 towrite = (15 - GETFIELD(XADC_STATUS, CFIFO_LVL, status));
 611                 towrite = min(towrite,
 612                         xadc->curr->count - xadc->curr->writeptr);
 613
 614                 for (i = 0; i < towrite; i++)
 615                         WRITE(xadc, CFIFO,
 616                                 xadc->curr->ops[xadc->curr->writeptr++].cmd);
 617
 618                 if (xadc->curr->writeptr == xadc->curr->count) {
 619                                 intmsk |= XADC_INT_CFIFO_LTH;
 620                                 WRITE(xadc, INTMSK, intmsk);
 621                         } else {
 622                                 u32 config;
 623                                 int cmdt;
 624                                 config = READ(xadc, CONFIG);
 625                                 config = CLRFIELD(XADC_CONFIG, \
 626                                         CFIFOTH, config);
 627                                 cmdt = xadc->curr->count-xadc->curr->writeptr;
 628                                 if (cmdt > 8) /*Half-full*/
 629                                         cmdt = 8;
 630                                         else /* Will write all next time*/
 631                                         cmdt --;
 632                                 config |= SETFIELD(XADC_CONFIG, \
 633                                         CFIFOTH, cmdt);
 634                                 WRITE(xadc, CONFIG, config);
 635                         }
 636                 WRITE(xadc, INTSTS, XADC_INT_CFIFO_LTH);
 637                 }
 638
 639         return IRQ_HANDLED;
 640 }
 641
 642 static struct xadc_batch setup = {
 643         .count = 11,
 644         .ops = {
 645                 {.cmd = WRITEOP(REG_CFG1, REG_CFG1_CAL_SSOG |\
 646                                         REG_CFG1_CAL_ADCOG |\
 647                                         SETFIELD(REG_CFG1, SEQ, MODE_DEF)),},
 648                 {.cmd = READOP(REG_FLAG),},/*read flags*/
 649                 {.cmd = WRITEOP(REG_SEQ_SEL0, 0)},
 650                 {.cmd = WRITEOP(REG_SEQ_AVG0, 0)},
 651                 {.cmd = WRITEOP(REG_SEQ_BIP0, 0)},
 652                 {.cmd = WRITEOP(REG_SEQ_ACQ0, 0)},
 653                 {.cmd = WRITEOP(REG_SEQ_SEL1, 0)},
 654                 {.cmd = WRITEOP(REG_SEQ_AVG1, 0)},
 655                 {.cmd = WRITEOP(REG_SEQ_BIP1, 0)},
 656                 {.cmd = WRITEOP(REG_SEQ_ACQ1, 0)},
 657                 {.cmd = WRITEOP(REG_CFG1, REG_CFG1_CAL_SSOG |\
 658                                         REG_CFG1_CAL_ADCOG |\
 659                                         SETFIELD(REG_CFG1, SEQ, MODE_IND)),},
 660                 },
 661 };
 662
 663 static int __devinit xadc_probe(struct platform_device *pdev)
 664 {
 665         struct xadc_t *xadc;
 666         u16 val;
 667         int ret;
 668
 669         xadc = kzalloc(sizeof(struct xadc_t), GFP_KERNEL);
 670         if (!xadc) {
 671                 dev_err(&pdev->dev, "Failed to allocate driver structure\n");
 672                 return -ENOMEM;
 673         }
 674         xadc->dev=&pdev->dev;
 675
 676         xadc->irq = platform_get_irq(pdev, 0);
 677         if (xadc->irq < 0) {
 678                 ret = xadc->irq;
 679                 dev_err(xadc->dev, "Failed to get platform irq\n");
 680                 goto err_free;
 681         }
 682
 683         xadc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 684         if (!xadc->mem) {
 685                 ret = -ENOENT;
 686                 dev_err(xadc->dev, "Failed to get platform resource\n");
 687                 goto err_free;
 688         }
 689
 690         xadc->mem = request_mem_region(xadc->mem->start,
 691                         resource_size(xadc->mem), pdev->name);
 692
 693         if (!xadc->mem) {
 694                 ret = -ENODEV;
 695                 dev_err(xadc->dev, "Failed to request memory region\n");
 696                 goto err_free;
 697         }
 698
 699         xadc->iobase = ioremap(xadc->mem->start, resource_size(xadc->mem));
 700         if (!xadc->iobase) {
 701                 ret = -ENODEV;
 702                 dev_err(xadc->dev, "Failed to ioremap memory\n");
 703                 goto err_mem_region;
 704         }
 705
 706         ret = request_irq(xadc->irq, xadc_irq,
 707                 IRQF_SHARED,
 708                 "xadc", xadc);
 709         if (ret) {
 710                 dev_err(xadc->dev, "Failed to request irq: %d\n", xadc->irq);
 711                 goto err_io_remap;
 712         }
 713
 714         ret = sysfs_create_group(&pdev->dev.kobj, &xadc_group);
 715         if (ret)
 716                 goto err_irq;
 717
 718         platform_set_drvdata(pdev, xadc);
 719
 720         xadc->hwmon = hwmon_device_register(&pdev->dev);
 721         if (IS_ERR(xadc->hwmon)) {
 722                 ret = PTR_ERR(xadc->hwmon);
 723                 dev_err(xadc->dev, "Failed to register hwmon device\n");
 724                 goto err_group;
 725         }
 726
 727         WRITE(xadc, CONFIG, 0);
 728         WRITE(xadc, CTL, 0); /*~RESET*/
 729
 730         WRITE(xadc, CONFIG, XADC_CONFIG_WEDGE |/*Default values*/
 731                 XADC_CONFIG_REDGE |
 732                 SETFIELD(XADC_CONFIG, TCKRATE, TCKRATE_DIV16) |
 733                 SETFIELD(XADC_CONFIG, IGAP, 20)
 734                 );
 735
 736         WRITE(xadc, CONFIG, READ(xadc, CONFIG) | XADC_CONFIG_ENABLE);
 737
 738         WRITE(xadc, INTSTS, ~0); /*clear all interrupts*/
 739         WRITE(xadc, INTMSK, ~(0)); /*mask all interrupts*/
 740
 741         INIT_LIST_HEAD(&xadc->runq);
 742         spin_lock_init(&xadc->slock);
 743
 744         add_batch(xadc, &setup);
 745         wait_for_completion_interruptible(&setup.comp);
 746
 747         val = setup.ops[2].res;
 748         dev_info(xadc->dev, "enabled:\t%s\treference:\t%s\n",
 749                 val&REG_FLAG_DIS?"no":"yes",
 750                 val&REG_FLAG_REF?"internal":"external");
 751
 752         return 0;
 753
 754 err_group:
 755         sysfs_remove_group(&pdev->dev.kobj, &xadc_group);
 756 err_irq:
 757         free_irq(xadc->irq, xadc);
 758 err_io_remap:
 759         iounmap(xadc->iobase);
 760 err_mem_region:
 761         release_mem_region(xadc->mem->start, resource_size(xadc->mem));
 762 err_free:
 763         kfree(xadc);
 764         return ret;
 765 }
 766
 767 static int __devexit xadc_remove(struct platform_device *pdev)
 768 {
 769         struct xadc_t *xadc = platform_get_drvdata(pdev);
 770
 771         hwmon_device_unregister(xadc->hwmon);
 772
 773         sysfs_remove_group(&pdev->dev.kobj, &xadc_group);
 774
 775         free_irq(xadc->irq, xadc);
 776
 777         iounmap(xadc->iobase);
 778         release_mem_region(xadc->mem->start, resource_size(xadc->mem));
 779
 780         platform_set_drvdata(pdev, NULL);
 781
 782         kfree(xadc);
 783
 784         return 0;
 785 }
 786
 787 #ifdef CONFIG_OF
 788 static struct of_device_id xadcps_of_match[] __devinitdata = {
 789         { .compatible = "xlnx,ps7-xadc-1.00.a", },
 790         { /* end of table */}
 791 };
 792 MODULE_DEVICE_TABLE(of, xadcps_of_match);
 793 #else
 794 #define xadcps_of_match NULL
 795 #endif /* CONFIG_OF */
 796
 797 static struct platform_driver xadc_driver = {
 798         .probe = xadc_probe,
 799         .remove = __devexit_p(xadc_remove),
 800         .driver = {
 801                 .name = "xadcps",
 802                 .owner = THIS_MODULE,
 803                 .of_match_table = xadcps_of_match,
 804         },
 805 };
 806
 807 module_platform_driver(xadc_driver);
 808
 809 MODULE_AUTHOR("Vlad Lungu <vlad.lungu@windriver.com>");
 810 MODULE_DESCRIPTION("Xilinx Zynq XADC");
 811 MODULE_LICENSE("GPL v2");
 812 MODULE_ALIAS("platform:xadcps");