drivers/hwmon/hwmon-vid.c

   1 /*
   2  * hwmon-vid.c - VID/VRM/VRD voltage conversions
   3  *
   4  * Copyright (c) 2004 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * Partly imported from i2c-vid.h of the lm_sensors project
   7  * Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com>
   8  * With assistance from Trent Piepho <xyzzy@speakeasy.org>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24
  25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  26
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/hwmon-vid.h>
  30
  31 /*
  32  * Common code for decoding VID pins.
  33  *
  34  * References:
  35  *
  36  * For VRM 8.4 to 9.1, "VRM x.y DC-DC Converter Design Guidelines",
  37  * available at http://developer.intel.com/.
  38  *
  39  * For VRD 10.0 and up, "VRD x.y Design Guide",
  40  * available at http://developer.intel.com/.
  41  *
  42  * AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094,
  43  * http://support.amd.com/us/Processor_TechDocs/26094.PDF
  44  * Table 74. VID Code Voltages
  45  * This corresponds to an arbitrary VRM code of 24 in the functions below.
  46  * These CPU models (K8 revision <= E) have 5 VID pins. See also:
  47  * Revision Guide for AMD Athlon 64 and AMD Opteron Processors, AMD Publication 25759,
  48  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf
  49  *
  50  * AMD NPT Family 0Fh Processors, AMD Publication 32559,
  51  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
  52  * Table 71. VID Code Voltages
  53  * This corresponds to an arbitrary VRM code of 25 in the functions below.
  54  * These CPU models (K8 revision >= F) have 6 VID pins. See also:
  55  * Revision Guide for AMD NPT Family 0Fh Processors, AMD Publication 33610,
  56  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
  57  *
  58  * The 17 specification is in fact Intel Mobile Voltage Positioning -
  59  * (IMVP-II). You can find more information in the datasheet of Max1718
  60  * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452
  61  *
  62  * The 13 specification corresponds to the Intel Pentium M series. There
  63  * doesn't seem to be any named specification for these. The conversion
  64  * tables are detailed directly in the various Pentium M datasheets:
  65  * http://www.intel.com/design/intarch/pentiumm/docs_pentiumm.htm
  66  *
  67  * The 14 specification corresponds to Intel Core series. There
  68  * doesn't seem to be any named specification for these. The conversion
  69  * tables are detailed directly in the various Pentium Core datasheets:
  70  * http://www.intel.com/design/mobile/datashts/309221.htm
  71  *
  72  * The 110 (VRM 11) specification corresponds to Intel Conroe based series.
  73  * http://www.intel.com/design/processor/applnots/313214.htm
  74  */
  75
  76 /*
  77  * vrm is the VRM/VRD document version multiplied by 10.
  78  * val is the 4-bit or more VID code.
  79  * Returned value is in mV to avoid floating point in the kernel.
  80  * Some VID have some bits in uV scale, this is rounded to mV.
  81  */
  82 int vid_from_reg(int val, u8 vrm)
  83 {
  84         int vid;
  85
  86         switch (vrm) {
  87
  88         case 100:               /* VRD 10.0 */
  89                 /* compute in uV, round to mV */
  90                 val &= 0x3f;
  91                 if ((val & 0x1f) == 0x1f)
  92                         return 0;
  93                 if ((val & 0x1f) <= 0x09 || val == 0x0a)
  94                         vid = 1087500 - (val & 0x1f) * 25000;
  95                 else
  96                         vid = 1862500 - (val & 0x1f) * 25000;
  97                 if (val & 0x20)
  98                         vid -= 12500;
  99                 return (vid + 500) / 1000;
 100
 101         case 110:               /* Intel Conroe */
 102                                 /* compute in uV, round to mV */
 103                 val &= 0xff;
 104                 if (val < 0x02 || val > 0xb2)
 105                         return 0;
 106                 return (1600000 - (val - 2) * 6250 + 500) / 1000;
 107
 108         case 24:                /* Athlon64 & Opteron */
 109                 val &= 0x1f;
 110                 if (val == 0x1f)
 111                         return 0;
 112                                 /* fall through */
 113         case 25:                /* AMD NPT 0Fh */
 114                 val &= 0x3f;
 115                 return (val < 32) ? 1550 - 25 * val
 116                         : 775 - (25 * (val - 31)) / 2;
 117
 118         case 91:                /* VRM 9.1 */
 119         case 90:                /* VRM 9.0 */
 120                 val &= 0x1f;
 121                 return val == 0x1f ? 0 :
 122                                      1850 - val * 25;
 123
 124         case 85:                /* VRM 8.5 */
 125                 val &= 0x1f;
 126                 return (val & 0x10  ? 25 : 0) +
 127                        ((val & 0x0f) > 0x04 ? 2050 : 1250) -
 128                        ((val & 0x0f) * 50);
 129
 130         case 84:                /* VRM 8.4 */
 131                 val &= 0x0f;
 132                                 /* fall through */
 133         case 82:                /* VRM 8.2 */
 134                 val &= 0x1f;
 135                 return val == 0x1f ? 0 :
 136                        val & 0x10  ? 5100 - (val) * 100 :
 137                                      2050 - (val) * 50;
 138         case 17:                /* Intel IMVP-II */
 139                 val &= 0x1f;
 140                 return val & 0x10 ? 975 - (val & 0xF) * 25 :
 141                                     1750 - val * 50;
 142         case 13:
 143         case 131:
 144                 val &= 0x3f;
 145                 /* Exception for Eden ULV 500 MHz */
 146                 if (vrm == 131 && val == 0x3f)
 147                         val++;
 148                 return 1708 - val * 16;
 149         case 14:                /* Intel Core */
 150                                 /* compute in uV, round to mV */
 151                 val &= 0x7f;
 152                 return val > 0x77 ? 0 : (1500000 - (val * 12500) + 500) / 1000;
 153         default:                /* report 0 for unknown */
 154                 if (vrm)
 155                         pr_warn("Requested unsupported VRM version (%u)\n",
 156                                 (unsigned int)vrm);
 157                 return 0;
 158         }
 159 }
 160 EXPORT_SYMBOL(vid_from_reg);
 161
 162 /*
 163  * After this point is the code to automatically determine which
 164  * VRM/VRD specification should be used depending on the CPU.
 165  */
 166
 167 struct vrm_model {
 168         u8 vendor;
 169         u8 family;
 170         u8 model_from;
 171         u8 model_to;
 172         u8 stepping_to;
 173         u8 vrm_type;
 174 };
 175
 176 #define ANY 0xFF
 177
 178 #ifdef CONFIG_X86
 179
 180 /*
 181  * The stepping_to parameter is highest acceptable stepping for current line.
 182  * The model match must be exact for 4-bit values. For model values 0x10
 183  * and above (extended model), all models below the parameter will match.
 184  */
 185
 186 static struct vrm_model vrm_models[] = {
 187         {X86_VENDOR_AMD, 0x6, 0x0, ANY, ANY, 90},       /* Athlon Duron etc */
 188         {X86_VENDOR_AMD, 0xF, 0x0, 0x3F, ANY, 24},      /* Athlon 64, Opteron */
 189         /*
 190          * In theory, all NPT family 0Fh processors have 6 VID pins and should
 191          * thus use vrm 25, however in practice not all mainboards route the
 192          * 6th VID pin because it is never needed. So we use the 5 VID pin
 193          * variant (vrm 24) for the models which exist today.
 194          */
 195         {X86_VENDOR_AMD, 0xF, 0x40, 0x7F, ANY, 24},     /* NPT family 0Fh */
 196         {X86_VENDOR_AMD, 0xF, 0x80, ANY, ANY, 25},      /* future fam. 0Fh */
 197         {X86_VENDOR_AMD, 0x10, 0x0, ANY, ANY, 25},      /* NPT family 10h */
 198
 199         {X86_VENDOR_INTEL, 0x6, 0x0, 0x6, ANY, 82},     /* Pentium Pro,
 200                                                          * Pentium II, Xeon,
 201                                                          * Mobile Pentium,
 202                                                          * Celeron */
 203         {X86_VENDOR_INTEL, 0x6, 0x7, 0x7, ANY, 84},     /* Pentium III, Xeon */
 204         {X86_VENDOR_INTEL, 0x6, 0x8, 0x8, ANY, 82},     /* Pentium III, Xeon */
 205         {X86_VENDOR_INTEL, 0x6, 0x9, 0x9, ANY, 13},     /* Pentium M (130 nm) */
 206         {X86_VENDOR_INTEL, 0x6, 0xA, 0xA, ANY, 82},     /* Pentium III Xeon */
 207         {X86_VENDOR_INTEL, 0x6, 0xB, 0xB, ANY, 85},     /* Tualatin */
 208         {X86_VENDOR_INTEL, 0x6, 0xD, 0xD, ANY, 13},     /* Pentium M (90 nm) */
 209         {X86_VENDOR_INTEL, 0x6, 0xE, 0xE, ANY, 14},     /* Intel Core (65 nm) */
 210         {X86_VENDOR_INTEL, 0x6, 0xF, ANY, ANY, 110},    /* Intel Conroe and
 211                                                          * later */
 212         {X86_VENDOR_INTEL, 0xF, 0x0, 0x0, ANY, 90},     /* P4 */
 213         {X86_VENDOR_INTEL, 0xF, 0x1, 0x1, ANY, 90},     /* P4 Willamette */
 214         {X86_VENDOR_INTEL, 0xF, 0x2, 0x2, ANY, 90},     /* P4 Northwood */
 215         {X86_VENDOR_INTEL, 0xF, 0x3, ANY, ANY, 100},    /* Prescott and above
 216                                                          * assume VRD 10 */
 217
 218         {X86_VENDOR_CENTAUR, 0x6, 0x7, 0x7, ANY, 85},   /* Eden ESP/Ezra */
 219         {X86_VENDOR_CENTAUR, 0x6, 0x8, 0x8, 0x7, 85},   /* Ezra T */
 220         {X86_VENDOR_CENTAUR, 0x6, 0x9, 0x9, 0x7, 85},   /* Nehemiah */
 221         {X86_VENDOR_CENTAUR, 0x6, 0x9, 0x9, ANY, 17},   /* C3-M, Eden-N */
 222         {X86_VENDOR_CENTAUR, 0x6, 0xA, 0xA, 0x7, 0},    /* No information */
 223         {X86_VENDOR_CENTAUR, 0x6, 0xA, 0xA, ANY, 13},   /* C7-M, C7,
 224                                                          * Eden (Esther) */
 225         {X86_VENDOR_CENTAUR, 0x6, 0xD, 0xD, ANY, 134},  /* C7-D, C7-M, C7,
 226                                                          * Eden (Esther) */
 227 };
 228
 229 /*
 230  * Special case for VIA model D: there are two different possible
 231  * VID tables, so we have to figure out first, which one must be
 232  * used. This resolves temporary drm value 134 to 14 (Intel Core
 233  * 7-bit VID), 13 (Pentium M 6-bit VID) or 131 (Pentium M 6-bit VID
 234  * + quirk for Eden ULV 500 MHz).
 235  * Note: something similar might be needed for model A, I'm not sure.
 236  */
 237 static u8 get_via_model_d_vrm(void)
 238 {
 239         unsigned int vid, brand, dummy;
 240         static const char *brands[4] = {
 241                 "C7-M", "C7", "Eden", "C7-D"
 242         };
 243
 244         rdmsr(0x198, dummy, vid);
 245         vid &= 0xff;
 246
 247         rdmsr(0x1154, brand, dummy);
 248         brand = ((brand >> 4) ^ (brand >> 2)) & 0x03;
 249
 250         if (vid > 0x3f) {
 251                 pr_info("Using %d-bit VID table for VIA %s CPU\n",
 252                         7, brands[brand]);
 253                 return 14;
 254         } else {
 255                 pr_info("Using %d-bit VID table for VIA %s CPU\n",
 256                         6, brands[brand]);
 257                 /* Enable quirk for Eden */
 258                 return brand == 2 ? 131 : 13;
 259         }
 260 }
 261
 262 static u8 find_vrm(u8 family, u8 model, u8 stepping, u8 vendor)
 263 {
 264         int i;
 265
 266         for (i = 0; i < ARRAY_SIZE(vrm_models); i++) {
 267                 if (vendor == vrm_models[i].vendor &&
 268                     family == vrm_models[i].family &&
 269                     model >= vrm_models[i].model_from &&
 270                     model <= vrm_models[i].model_to &&
 271                     stepping <= vrm_models[i].stepping_to)
 272                         return vrm_models[i].vrm_type;
 273         }
 274
 275         return 0;
 276 }
 277
 278 u8 vid_which_vrm(void)
 279 {
 280         struct cpuinfo_x86 *c = &cpu_data(0);
 281         u8 vrm_ret;
 282
 283         if (c->x86 < 6)         /* Any CPU with family lower than 6 */
 284                 return 0;       /* doesn't have VID */
 285
 286         vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_mask, c->x86_vendor);
 287         if (vrm_ret == 134)
 288                 vrm_ret = get_via_model_d_vrm();
 289         if (vrm_ret == 0)
 290                 pr_info("Unknown VRM version of your x86 CPU\n");
 291         return vrm_ret;
 292 }
 293
 294 /* and now for something completely different for the non-x86 world */
 295 #else
 296 u8 vid_which_vrm(void)
 297 {
 298         pr_info("Unknown VRM version of your CPU\n");
 299         return 0;
 300 }
 301 #endif
 302 EXPORT_SYMBOL(vid_which_vrm);
 303
 304 MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
 305
 306 MODULE_DESCRIPTION("hwmon-vid driver");
 307 MODULE_LICENSE("GPL");