drivers/xilinx_common/xdmav3_intr.c

   1 /* $Id: */
   2 /******************************************************************************
   3 *
   4 *       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
   5 *       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
   6 *       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
   7 *       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
   8 *       APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
   9 *       THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
  10 *       AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
  11 *       FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
  12 *       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
  13 *       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
  14 *       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
  15 *       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  16 *       FOR A PARTICULAR PURPOSE.
  17 *
  18 *       (c) Copyright 2006 Xilinx Inc.
  19 *       All rights reserved.
  20 * This program is free software; you can redistribute it and/or modify it
  21 * under the terms of the GNU General Public License as published by the
  22 * Free Software Foundation; either version 2 of the License, or (at your
  23 * option) any later version.
  24 *
  25 * You should have received a copy of the GNU General Public License
  26 * along with this program; if not, write to the Free Software
  27 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28 *
  29 ******************************************************************************/
  30 /*****************************************************************************/
  31 /**
  32 *
  33 * @file xdmav3_intr.c
  34 *
  35 * This file implements interrupt control related functions. For more
  36 * information on this driver, see xdmav3.h.
  37 *
  38 * <pre>
  39 * MODIFICATION HISTORY:
  40 *
  41 * Ver   Who  Date     Changes
  42 * ----- ---- -------- -------------------------------------------------------
  43 * 3.00a rmm  03/11/06 First release
  44 * </pre>
  45 ******************************************************************************/
  46
  47 /***************************** Include Files *********************************/
  48
  49 #include "xdmav3.h"
  50
  51 /************************** Constant Definitions *****************************/
  52
  53
  54 /**************************** Type Definitions *******************************/
  55
  56
  57 /***************** Macros (Inline Functions) Definitions *********************/
  58
  59
  60 /************************** Function Prototypes ******************************/
  61
  62
  63 /************************** Variable Definitions *****************************/
  64
  65
  66 /*****************************************************************************/
  67 /**
  68 * Set the interrupt status register for this channel. Use this function
  69 * to ack pending interrupts.
  70 *
  71 * @param InstancePtr is a pointer to the instance to be worked on.
  72 * @param Mask is a logical OR of XDMAV3_IPXR_*_MASK constants found in
  73 *        xdmav3_l.h.
  74 *
  75 ******************************************************************************/
  76 void XDmaV3_SetInterruptStatus(XDmaV3 * InstancePtr, u32 Mask)
  77 {
  78         XDmaV3_mWriteReg(InstancePtr->RegBase, XDMAV3_ISR_OFFSET, Mask);
  79 }
  80
  81
  82 /*****************************************************************************/
  83 /**
  84 * Retrieve the interrupt status for this channel. OR the results of this
  85 * function with results from XDmaV3_GetInterruptEnable() to determine which
  86 * interrupts are currently pending to the processor.
  87 *
  88 * @param InstancePtr is a pointer to the instance to be worked on.
  89 *
  90 * @return Mask of interrupt bits made up of XDMAV3_IPXR_*_MASK constants found
  91 *         in xdmav3_l.h.
  92 *
  93 ******************************************************************************/
  94 u32 XDmaV3_GetInterruptStatus(XDmaV3 * InstancePtr)
  95 {
  96         return (XDmaV3_mReadReg(InstancePtr->RegBase, XDMAV3_ISR_OFFSET));
  97 }
  98
  99
 100 /*****************************************************************************/
 101 /**
 102 * Enable specific DMA interrupts.
 103 *
 104 * @param InstancePtr is a pointer to the instance to be worked on.
 105 * @param Mask is a logical OR of of XDMAV3_IPXR_*_MASK constants found in
 106 *        xdmav3_l.h.
 107 *
 108 ******************************************************************************/
 109 void XDmaV3_SetInterruptEnable(XDmaV3 * InstancePtr, u32 Mask)
 110 {
 111         XDmaV3_mWriteReg(InstancePtr->RegBase, XDMAV3_IER_OFFSET, Mask);
 112 }
 113
 114
 115 /*****************************************************************************/
 116 /**
 117 * Retrieve the interrupt enable register for this channel. Use this function to
 118 * determine which interrupts are currently enabled to the processor.
 119 *
 120 * @param InstancePtr is a pointer to the instance to be worked on.
 121 *
 122 * @return Mask of interrupt bits made up of XDMAV3_IPXR_*_MASK constants found in
 123 *         xdmav3_l.h.
 124 *
 125 ******************************************************************************/
 126 u32 XDmaV3_GetInterruptEnable(XDmaV3 * InstancePtr)
 127 {
 128         return (XDmaV3_mReadReg(InstancePtr->RegBase, XDMAV3_IER_OFFSET));
 129 }