Xilinx: ARM: I2C: SI570: Driver updated for more error checking
[linux-2.6-xlnx.git] / drivers / video / xylon / xylonfb / logicvc.h
blob7bd05f17d7c7634c0cf58781985a4ccd95b4f268
1 /*
2 * Xylon logiCVC IP core definitions
4 * Author: Xylon d.o.o.
5 * e-mail: davor.joja@logicbricks.com
7 * 2012 (c) Xylon d.o.o.
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
14 #ifndef __LOGICVC_H__
15 #define __LOGICVC_H__
17 /* All logiCVC registers are 32 bit registers, at distance of 64 bit */
18 #define LOGICVC_REG_DIST_USED 8 /* All logicvc registers are spaced at 8 bytes */
19 #define LOGICVC_SHSY_FP_ROFF (0 * LOGICVC_REG_DIST_USED) /* R_HSY_FP */
20 #define LOGICVC_SHSY_ROFF (1 * LOGICVC_REG_DIST_USED) /* R_HSY */
21 #define LOGICVC_SHSY_BP_ROFF (2 * LOGICVC_REG_DIST_USED) /* R_HSY_BP */
22 #define LOGICVC_SHSY_RES_ROFF (3 * LOGICVC_REG_DIST_USED) /* R_HSY_RES */
23 #define LOGICVC_SVSY_FP_ROFF (4 * LOGICVC_REG_DIST_USED) /* R_VSY_FP */
24 #define LOGICVC_SVSY_ROFF (5 * LOGICVC_REG_DIST_USED) /* R_VSY */
25 #define LOGICVC_SVSY_BP_ROFF (6 * LOGICVC_REG_DIST_USED) /* R_VSY_BP */
26 #define LOGICVC_SVSY_RES_ROFF (7 * LOGICVC_REG_DIST_USED) /* R_VSY_RES */
27 #define LOGICVC_SCTRL_ROFF (8 * LOGICVC_REG_DIST_USED) /* R_CTRL */
28 #define LOGICVC_SDTYPE_ROFF (9 * LOGICVC_REG_DIST_USED) /* R_DTYPE */
29 #define LOGICVC_BACKCOL_ROFF (10 * LOGICVC_REG_DIST_USED) /* R_BACKGROUND */
30 #define LOGICVC_DOUBLE_VBUFF_ROFF (11 * LOGICVC_REG_DIST_USED) /* R_DOUBLE_VBUFF */
31 #define LOGICVC_DOUBLE_CLUT_ROFF (12 * LOGICVC_REG_DIST_USED) /* R_DOUBLE_CLUT */
32 #define LOGICVC_INT_ROFF (13 * LOGICVC_REG_DIST_USED) /* R_INT */
33 #define LOGICVC_INT_MASK_ROFF (14 * LOGICVC_REG_DIST_USED) /* R_INT_MASK */
34 #define LOGICVC_SPWRCTRL_ROFF (15 * LOGICVC_REG_DIST_USED) /* R_PWRCTRL */
36 /* logiCVC layer registers base and distance between the layers */
37 //#define LOGICVC_LAYER_DISTANCE (16 * LOGICVC_REG_DIST_USED) /* distance between groups of layer registers */
38 //#define LOGICVC_LAYER0_BASE_ROFF (32 * LOGICVC_REG_DIST_USED) /* offset to the beginning of layer 0 registers */
39 //#define LOGICVC_LAYER1_BASE_ROFF (LOGICVC_LAYER0_BASE_ROFF + LOGICVC_LAYER_DISTANCE * 1) /* offset to the beginning of layer 1 registers */
40 //#define LOGICVC_LAYER2_BASE_ROFF (LOGICVC_LAYER0_BASE_ROFF + LOGICVC_LAYER_DISTANCE * 2) /* offset to the beginning of layer 2 registers */
41 //#define LOGICVC_LAYER3_BASE_ROFF (LOGICVC_LAYER0_BASE_ROFF + LOGICVC_LAYER_DISTANCE * 3) /* offset to the beginning of layer 3 registers */
42 //#define LOGICVC_LAYER4_BASE_ROFF (LOGICVC_LAYER0_BASE_ROFF + LOGICVC_LAYER_DISTANCE * 4) /* offset to the beginning of layer 4 registers */
43 /* logiCVC layer registers offsets (common for each layer) */
44 #define LOGICVC_LAYER_HOR_OFF_ROFF (0 * LOGICVC_REG_DIST_USED) /* LH_OFFSET */
45 #define LOGICVC_LAYER_VER_OFF_ROFF (1 * LOGICVC_REG_DIST_USED) /* LV_OFFSET */
46 #define LOGICVC_LAYER_HOR_POS_ROFF (2 * LOGICVC_REG_DIST_USED) /* LH_POSITION */
47 #define LOGICVC_LAYER_VER_POS_ROFF (3 * LOGICVC_REG_DIST_USED) /* LV_POSITION */
48 #define LOGICVC_LAYER_WIDTH_ROFF (4 * LOGICVC_REG_DIST_USED) /* LH_WIDTH */
49 #define LOGICVC_LAYER_HEIGHT_ROFF (5 * LOGICVC_REG_DIST_USED) /* LV_HEIGHT */
50 #define LOGICVC_LAYER_ALPHA_ROFF (6 * LOGICVC_REG_DIST_USED) /* ALPHA */
51 #define LOGICVC_LAYER_CTRL_ROFF (7 * LOGICVC_REG_DIST_USED) /* CTRL */
52 #define LOGICVC_LAYER_TRANSP_ROFF (8 * LOGICVC_REG_DIST_USED) /* TRANSPARENT */
54 /* logiCVC interrupt bits */
55 #define LOGICVC_L0_VBUFF_SW_INT 0x01
56 #define LOGICVC_L1_VBUFF_SW_INT 0x02
57 #define LOGICVC_L2_VBUFF_SW_INT 0x04
58 #define LOGICVC_L3_VBUFF_SW_INT 0x08
59 #define LOGICVC_L4_VBUFF_SW_INT 0x10
60 #define LOGICVC_V_SYNC_INT 0x20
61 #define LOGICVC_E_VIDEO_VALID_INT 0x40
62 #define LOGICVC_L0_CLUT_SW_INT 0x100
63 #define LOGICVC_L1_CLUT_SW_INT 0x200
64 #define LOGICVC_L2_CLUT_SW_INT 0x400
65 #define LOGICVC_L3_CLUT_SW_INT 0x800
66 #define LOGICVC_L4_CLUT_SW_INT 0x1000
68 /* logiCVC layer base offsets */
69 #define LOGICVC_LAYER_BASE_OFFSET 0x100
70 #define LOGICVC_LAYER_0_OFFSET 0
71 #define LOGICVC_LAYER_1_OFFSET 0x80
72 #define LOGICVC_LAYER_2_OFFSET 0x100
73 #define LOGICVC_LAYER_3_OFFSET 0x180
74 #define LOGICVC_LAYER_4_OFFSET 0x200
76 /* logiCVC layer CLUT base offsets */
77 #define LOGICVC_CLUT_BASE_OFFSET 0x1000
78 #define LOGICVC_CLUT_L0_CLUT_0_OFFSET 0
79 #define LOGICVC_CLUT_L0_CLUT_1_OFFSET 0x800
80 #define LOGICVC_CLUT_L1_CLUT_0_OFFSET 0x1000
81 #define LOGICVC_CLUT_L1_CLUT_1_OFFSET 0x1800
82 #define LOGICVC_CLUT_L2_CLUT_0_OFFSET 0x2000
83 #define LOGICVC_CLUT_L2_CLUT_1_OFFSET 0x2800
84 #define LOGICVC_CLUT_L3_CLUT_0_OFFSET 0x3000
85 #define LOGICVC_CLUT_L3_CLUT_1_OFFSET 0x3800
86 #define LOGICVC_CLUT_L4_CLUT_0_OFFSET 0x4000
87 #define LOGICVC_CLUT_L4_CLUT_1_OFFSET 0x4800
88 #define LOGICVC_CLUT_REGISTER_SIZE 8
90 /* logiCVC register and CLUT base offsets */
91 #define LOGICVC_GENERAL_REGISTERS_RANGE 0x100
92 #define LOGICVC_REGISTERS_RANGE 0x6000
94 /* logiCVC register initial values */
95 #define CTRL_REG_INIT 0x001F
96 #define SD_REG_INIT 0
98 /* logiCVC display power signals */
99 #define LOGICVC_EN_BLIGHT_MSK 0x01
100 #define LOGICVC_EN_VDD_MSK 0x02
101 #define LOGICVC_EN_VEE_MSK 0x04
102 #define LOGICVC_V_EN_MSK 0x08
104 /* logiCVC various definitions */
105 #define LOGICVC_MAX_LAYERS 5
106 #define LOGICVC_LAYER_ON 0x10
107 #define LOGICVC_MAX_VRES 4096 /* this value must be 2048! for now it's hacked */
108 #define TRANSPARENT_COLOR_8BPP_CLUT_16 0xF813
109 #define TRANSPARENT_COLOR_8BPP_CLUT_24 0x00FF009C
110 #define TRANSPARENT_COLOR_16BPP 0xF813
111 #define TRANSPARENT_COLOR_24BPP 0x00FF009C
112 #define BACKGROUND_COLOR 0x00000000
114 #define LOGICVC_LAYER_ALPHA 0
115 #define LOGICVC_PIXEL_ALPHA 1
116 #define LOGICVC_CLUT_16BPP_ALPHA 2
117 #define LOGICVC_CLUT_32BPP_ALPHA 3
119 #endif /* __LOGICVC_H__ */