2 * linux/arch/arm/plat-omap/mcbsp.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Multichannel mode not supported.
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
28 #include <mach/mcbsp.h>
30 static struct omap_mcbsp mcbsp
[OMAP_MAX_MCBSP_COUNT
];
32 #define omap_mcbsp_check_valid_id(id) (mcbsp[id].pdata && \
33 mcbsp[id].pdata->ops && \
34 mcbsp[id].pdata->ops->check && \
35 (mcbsp[id].pdata->ops->check(id) == 0))
37 static void omap_mcbsp_dump_reg(u8 id
)
39 dev_dbg(mcbsp
[id
].dev
, "**** McBSP%d regs ****\n", mcbsp
[id
].id
);
40 dev_dbg(mcbsp
[id
].dev
, "DRR2: 0x%04x\n",
41 OMAP_MCBSP_READ(mcbsp
[id
].io_base
, DRR2
));
42 dev_dbg(mcbsp
[id
].dev
, "DRR1: 0x%04x\n",
43 OMAP_MCBSP_READ(mcbsp
[id
].io_base
, DRR1
));
44 dev_dbg(mcbsp
[id
].dev
, "DXR2: 0x%04x\n",
45 OMAP_MCBSP_READ(mcbsp
[id
].io_base
, DXR2
));
46 dev_dbg(mcbsp
[id
].dev
, "DXR1: 0x%04x\n",
47 OMAP_MCBSP_READ(mcbsp
[id
].io_base
, DXR1
));
48 dev_dbg(mcbsp
[id
].dev
, "SPCR2: 0x%04x\n",
49 OMAP_MCBSP_READ(mcbsp
[id
].io_base
, SPCR2
));
50 dev_dbg(mcbsp
[id
].dev
, "SPCR1: 0x%04x\n",
51 OMAP_MCBSP_READ(mcbsp
[id
].io_base
, SPCR1
));
52 dev_dbg(mcbsp
[id
].dev
, "RCR2: 0x%04x\n",
53 OMAP_MCBSP_READ(mcbsp
[id
].io_base
, RCR2
));
54 dev_dbg(mcbsp
[id
].dev
, "RCR1: 0x%04x\n",
55 OMAP_MCBSP_READ(mcbsp
[id
].io_base
, RCR1
));
56 dev_dbg(mcbsp
[id
].dev
, "XCR2: 0x%04x\n",
57 OMAP_MCBSP_READ(mcbsp
[id
].io_base
, XCR2
));
58 dev_dbg(mcbsp
[id
].dev
, "XCR1: 0x%04x\n",
59 OMAP_MCBSP_READ(mcbsp
[id
].io_base
, XCR1
));
60 dev_dbg(mcbsp
[id
].dev
, "SRGR2: 0x%04x\n",
61 OMAP_MCBSP_READ(mcbsp
[id
].io_base
, SRGR2
));
62 dev_dbg(mcbsp
[id
].dev
, "SRGR1: 0x%04x\n",
63 OMAP_MCBSP_READ(mcbsp
[id
].io_base
, SRGR1
));
64 dev_dbg(mcbsp
[id
].dev
, "PCR0: 0x%04x\n",
65 OMAP_MCBSP_READ(mcbsp
[id
].io_base
, PCR0
));
66 dev_dbg(mcbsp
[id
].dev
, "***********************\n");
69 static irqreturn_t
omap_mcbsp_tx_irq_handler(int irq
, void *dev_id
)
71 struct omap_mcbsp
*mcbsp_tx
= dev_id
;
73 dev_dbg(mcbsp_tx
->dev
, "TX IRQ callback : 0x%x\n",
74 OMAP_MCBSP_READ(mcbsp_tx
->io_base
, SPCR2
));
76 complete(&mcbsp_tx
->tx_irq_completion
);
81 static irqreturn_t
omap_mcbsp_rx_irq_handler(int irq
, void *dev_id
)
83 struct omap_mcbsp
*mcbsp_rx
= dev_id
;
85 dev_dbg(mcbsp_rx
->dev
, "RX IRQ callback : 0x%x\n",
86 OMAP_MCBSP_READ(mcbsp_rx
->io_base
, SPCR2
));
88 complete(&mcbsp_rx
->rx_irq_completion
);
93 static void omap_mcbsp_tx_dma_callback(int lch
, u16 ch_status
, void *data
)
95 struct omap_mcbsp
*mcbsp_dma_tx
= data
;
97 dev_dbg(mcbsp_dma_tx
->dev
, "TX DMA callback : 0x%x\n",
98 OMAP_MCBSP_READ(mcbsp_dma_tx
->io_base
, SPCR2
));
100 /* We can free the channels */
101 omap_free_dma(mcbsp_dma_tx
->dma_tx_lch
);
102 mcbsp_dma_tx
->dma_tx_lch
= -1;
104 complete(&mcbsp_dma_tx
->tx_dma_completion
);
107 static void omap_mcbsp_rx_dma_callback(int lch
, u16 ch_status
, void *data
)
109 struct omap_mcbsp
*mcbsp_dma_rx
= data
;
111 dev_dbg(mcbsp_dma_rx
->dev
, "RX DMA callback : 0x%x\n",
112 OMAP_MCBSP_READ(mcbsp_dma_rx
->io_base
, SPCR2
));
114 /* We can free the channels */
115 omap_free_dma(mcbsp_dma_rx
->dma_rx_lch
);
116 mcbsp_dma_rx
->dma_rx_lch
= -1;
118 complete(&mcbsp_dma_rx
->rx_dma_completion
);
122 * omap_mcbsp_config simply write a config to the
124 * You either call this function or set the McBSP registers
125 * by yourself before calling omap_mcbsp_start().
127 void omap_mcbsp_config(unsigned int id
, const struct omap_mcbsp_reg_cfg
*config
)
131 if (!omap_mcbsp_check_valid_id(id
)) {
132 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
136 io_base
= mcbsp
[id
].io_base
;
137 dev_dbg(mcbsp
[id
].dev
, "Configuring McBSP%d io_base: 0x%8x\n",
138 mcbsp
[id
].id
, io_base
);
140 /* We write the given config */
141 OMAP_MCBSP_WRITE(io_base
, SPCR2
, config
->spcr2
);
142 OMAP_MCBSP_WRITE(io_base
, SPCR1
, config
->spcr1
);
143 OMAP_MCBSP_WRITE(io_base
, RCR2
, config
->rcr2
);
144 OMAP_MCBSP_WRITE(io_base
, RCR1
, config
->rcr1
);
145 OMAP_MCBSP_WRITE(io_base
, XCR2
, config
->xcr2
);
146 OMAP_MCBSP_WRITE(io_base
, XCR1
, config
->xcr1
);
147 OMAP_MCBSP_WRITE(io_base
, SRGR2
, config
->srgr2
);
148 OMAP_MCBSP_WRITE(io_base
, SRGR1
, config
->srgr1
);
149 OMAP_MCBSP_WRITE(io_base
, MCR2
, config
->mcr2
);
150 OMAP_MCBSP_WRITE(io_base
, MCR1
, config
->mcr1
);
151 OMAP_MCBSP_WRITE(io_base
, PCR0
, config
->pcr0
);
153 EXPORT_SYMBOL(omap_mcbsp_config
);
156 * We can choose between IRQ based or polled IO.
157 * This needs to be called before omap_mcbsp_request().
159 int omap_mcbsp_set_io_type(unsigned int id
, omap_mcbsp_io_type_t io_type
)
161 if (!omap_mcbsp_check_valid_id(id
)) {
162 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
166 spin_lock(&mcbsp
[id
].lock
);
168 if (!mcbsp
[id
].free
) {
169 dev_err(mcbsp
[id
].dev
, "McBSP%d is currently in use\n",
171 spin_unlock(&mcbsp
[id
].lock
);
175 mcbsp
[id
].io_type
= io_type
;
177 spin_unlock(&mcbsp
[id
].lock
);
181 EXPORT_SYMBOL(omap_mcbsp_set_io_type
);
183 int omap_mcbsp_request(unsigned int id
)
187 if (!omap_mcbsp_check_valid_id(id
)) {
188 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
192 if (mcbsp
[id
].pdata
->ops
->request
)
193 mcbsp
[id
].pdata
->ops
->request(id
);
195 clk_enable(mcbsp
[id
].clk
);
197 spin_lock(&mcbsp
[id
].lock
);
198 if (!mcbsp
[id
].free
) {
199 dev_err(mcbsp
[id
].dev
, "McBSP%d is currently in use\n",
201 spin_unlock(&mcbsp
[id
].lock
);
206 spin_unlock(&mcbsp
[id
].lock
);
208 if (mcbsp
[id
].io_type
== OMAP_MCBSP_IRQ_IO
) {
209 /* We need to get IRQs here */
210 err
= request_irq(mcbsp
[id
].tx_irq
, omap_mcbsp_tx_irq_handler
,
211 0, "McBSP", (void *) (&mcbsp
[id
]));
213 dev_err(mcbsp
[id
].dev
, "Unable to request TX IRQ %d "
214 "for McBSP%d\n", mcbsp
[id
].tx_irq
,
219 init_completion(&(mcbsp
[id
].tx_irq_completion
));
221 err
= request_irq(mcbsp
[id
].rx_irq
, omap_mcbsp_rx_irq_handler
,
222 0, "McBSP", (void *) (&mcbsp
[id
]));
224 dev_err(mcbsp
[id
].dev
, "Unable to request RX IRQ %d "
225 "for McBSP%d\n", mcbsp
[id
].rx_irq
,
227 free_irq(mcbsp
[id
].tx_irq
, (void *) (&mcbsp
[id
]));
231 init_completion(&(mcbsp
[id
].rx_irq_completion
));
236 EXPORT_SYMBOL(omap_mcbsp_request
);
238 void omap_mcbsp_free(unsigned int id
)
240 if (!omap_mcbsp_check_valid_id(id
)) {
241 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
245 if (mcbsp
[id
].pdata
->ops
->free
)
246 mcbsp
[id
].pdata
->ops
->free(id
);
248 clk_disable(mcbsp
[id
].clk
);
250 spin_lock(&mcbsp
[id
].lock
);
251 if (mcbsp
[id
].free
) {
252 dev_err(mcbsp
[id
].dev
, "McBSP%d was not reserved\n",
254 spin_unlock(&mcbsp
[id
].lock
);
259 spin_unlock(&mcbsp
[id
].lock
);
261 if (mcbsp
[id
].io_type
== OMAP_MCBSP_IRQ_IO
) {
263 free_irq(mcbsp
[id
].rx_irq
, (void *) (&mcbsp
[id
]));
264 free_irq(mcbsp
[id
].tx_irq
, (void *) (&mcbsp
[id
]));
267 EXPORT_SYMBOL(omap_mcbsp_free
);
270 * Here we start the McBSP, by enabling the sample
271 * generator, both transmitter and receivers,
272 * and the frame sync.
274 void omap_mcbsp_start(unsigned int id
)
279 if (!omap_mcbsp_check_valid_id(id
)) {
280 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
284 io_base
= mcbsp
[id
].io_base
;
286 mcbsp
[id
].rx_word_length
= (OMAP_MCBSP_READ(io_base
, RCR1
) >> 5) & 0x7;
287 mcbsp
[id
].tx_word_length
= (OMAP_MCBSP_READ(io_base
, XCR1
) >> 5) & 0x7;
289 /* Start the sample generator */
290 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
291 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
| (1 << 6));
293 /* Enable transmitter and receiver */
294 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
295 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
| 1);
297 w
= OMAP_MCBSP_READ(io_base
, SPCR1
);
298 OMAP_MCBSP_WRITE(io_base
, SPCR1
, w
| 1);
302 /* Start frame sync */
303 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
304 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
| (1 << 7));
306 /* Dump McBSP Regs */
307 omap_mcbsp_dump_reg(id
);
309 EXPORT_SYMBOL(omap_mcbsp_start
);
311 void omap_mcbsp_stop(unsigned int id
)
316 if (!omap_mcbsp_check_valid_id(id
)) {
317 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
321 io_base
= mcbsp
[id
].io_base
;
323 /* Reset transmitter */
324 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
325 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
& ~(1));
328 w
= OMAP_MCBSP_READ(io_base
, SPCR1
);
329 OMAP_MCBSP_WRITE(io_base
, SPCR1
, w
& ~(1));
331 /* Reset the sample rate generator */
332 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
333 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
& ~(1 << 6));
335 EXPORT_SYMBOL(omap_mcbsp_stop
);
337 /* polled mcbsp i/o operations */
338 int omap_mcbsp_pollwrite(unsigned int id
, u16 buf
)
342 if (!omap_mcbsp_check_valid_id(id
)) {
343 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
347 base
= mcbsp
[id
].io_base
;
348 writew(buf
, base
+ OMAP_MCBSP_REG_DXR1
);
349 /* if frame sync error - clear the error */
350 if (readw(base
+ OMAP_MCBSP_REG_SPCR2
) & XSYNC_ERR
) {
352 writew(readw(base
+ OMAP_MCBSP_REG_SPCR2
) & (~XSYNC_ERR
),
353 base
+ OMAP_MCBSP_REG_SPCR2
);
357 /* wait for transmit confirmation */
359 while (!(readw(base
+ OMAP_MCBSP_REG_SPCR2
) & XRDY
)) {
360 if (attemps
++ > 1000) {
361 writew(readw(base
+ OMAP_MCBSP_REG_SPCR2
) &
363 base
+ OMAP_MCBSP_REG_SPCR2
);
365 writew(readw(base
+ OMAP_MCBSP_REG_SPCR2
) |
367 base
+ OMAP_MCBSP_REG_SPCR2
);
369 dev_err(mcbsp
[id
].dev
, "Could not write to"
370 " McBSP%d Register\n", mcbsp
[id
].id
);
378 EXPORT_SYMBOL(omap_mcbsp_pollwrite
);
380 int omap_mcbsp_pollread(unsigned int id
, u16
*buf
)
384 if (!omap_mcbsp_check_valid_id(id
)) {
385 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
389 base
= mcbsp
[id
].io_base
;
390 /* if frame sync error - clear the error */
391 if (readw(base
+ OMAP_MCBSP_REG_SPCR1
) & RSYNC_ERR
) {
393 writew(readw(base
+ OMAP_MCBSP_REG_SPCR1
) & (~RSYNC_ERR
),
394 base
+ OMAP_MCBSP_REG_SPCR1
);
398 /* wait for recieve confirmation */
400 while (!(readw(base
+ OMAP_MCBSP_REG_SPCR1
) & RRDY
)) {
401 if (attemps
++ > 1000) {
402 writew(readw(base
+ OMAP_MCBSP_REG_SPCR1
) &
404 base
+ OMAP_MCBSP_REG_SPCR1
);
406 writew(readw(base
+ OMAP_MCBSP_REG_SPCR1
) |
408 base
+ OMAP_MCBSP_REG_SPCR1
);
410 dev_err(mcbsp
[id
].dev
, "Could not read from"
411 " McBSP%d Register\n", mcbsp
[id
].id
);
416 *buf
= readw(base
+ OMAP_MCBSP_REG_DRR1
);
420 EXPORT_SYMBOL(omap_mcbsp_pollread
);
423 * IRQ based word transmission.
425 void omap_mcbsp_xmit_word(unsigned int id
, u32 word
)
428 omap_mcbsp_word_length word_length
;
430 if (!omap_mcbsp_check_valid_id(id
)) {
431 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
435 io_base
= mcbsp
[id
].io_base
;
436 word_length
= mcbsp
[id
].tx_word_length
;
438 wait_for_completion(&(mcbsp
[id
].tx_irq_completion
));
440 if (word_length
> OMAP_MCBSP_WORD_16
)
441 OMAP_MCBSP_WRITE(io_base
, DXR2
, word
>> 16);
442 OMAP_MCBSP_WRITE(io_base
, DXR1
, word
& 0xffff);
444 EXPORT_SYMBOL(omap_mcbsp_xmit_word
);
446 u32
omap_mcbsp_recv_word(unsigned int id
)
449 u16 word_lsb
, word_msb
= 0;
450 omap_mcbsp_word_length word_length
;
452 if (!omap_mcbsp_check_valid_id(id
)) {
453 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
457 word_length
= mcbsp
[id
].rx_word_length
;
458 io_base
= mcbsp
[id
].io_base
;
460 wait_for_completion(&(mcbsp
[id
].rx_irq_completion
));
462 if (word_length
> OMAP_MCBSP_WORD_16
)
463 word_msb
= OMAP_MCBSP_READ(io_base
, DRR2
);
464 word_lsb
= OMAP_MCBSP_READ(io_base
, DRR1
);
466 return (word_lsb
| (word_msb
<< 16));
468 EXPORT_SYMBOL(omap_mcbsp_recv_word
);
470 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id
, u32 word
)
473 omap_mcbsp_word_length tx_word_length
;
474 omap_mcbsp_word_length rx_word_length
;
475 u16 spcr2
, spcr1
, attempts
= 0, word_lsb
, word_msb
= 0;
477 if (!omap_mcbsp_check_valid_id(id
)) {
478 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
482 io_base
= mcbsp
[id
].io_base
;
483 tx_word_length
= mcbsp
[id
].tx_word_length
;
484 rx_word_length
= mcbsp
[id
].rx_word_length
;
486 if (tx_word_length
!= rx_word_length
)
489 /* First we wait for the transmitter to be ready */
490 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
491 while (!(spcr2
& XRDY
)) {
492 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
493 if (attempts
++ > 1000) {
494 /* We must reset the transmitter */
495 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
& (~XRST
));
497 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
| XRST
);
499 dev_err(mcbsp
[id
].dev
, "McBSP%d transmitter not "
500 "ready\n", mcbsp
[id
].id
);
505 /* Now we can push the data */
506 if (tx_word_length
> OMAP_MCBSP_WORD_16
)
507 OMAP_MCBSP_WRITE(io_base
, DXR2
, word
>> 16);
508 OMAP_MCBSP_WRITE(io_base
, DXR1
, word
& 0xffff);
510 /* We wait for the receiver to be ready */
511 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
512 while (!(spcr1
& RRDY
)) {
513 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
514 if (attempts
++ > 1000) {
515 /* We must reset the receiver */
516 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
& (~RRST
));
518 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
| RRST
);
520 dev_err(mcbsp
[id
].dev
, "McBSP%d receiver not "
521 "ready\n", mcbsp
[id
].id
);
526 /* Receiver is ready, let's read the dummy data */
527 if (rx_word_length
> OMAP_MCBSP_WORD_16
)
528 word_msb
= OMAP_MCBSP_READ(io_base
, DRR2
);
529 word_lsb
= OMAP_MCBSP_READ(io_base
, DRR1
);
533 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll
);
535 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id
, u32
*word
)
537 u32 io_base
, clock_word
= 0;
538 omap_mcbsp_word_length tx_word_length
;
539 omap_mcbsp_word_length rx_word_length
;
540 u16 spcr2
, spcr1
, attempts
= 0, word_lsb
, word_msb
= 0;
542 if (!omap_mcbsp_check_valid_id(id
)) {
543 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
547 io_base
= mcbsp
[id
].io_base
;
548 tx_word_length
= mcbsp
[id
].tx_word_length
;
549 rx_word_length
= mcbsp
[id
].rx_word_length
;
551 if (tx_word_length
!= rx_word_length
)
554 /* First we wait for the transmitter to be ready */
555 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
556 while (!(spcr2
& XRDY
)) {
557 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
558 if (attempts
++ > 1000) {
559 /* We must reset the transmitter */
560 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
& (~XRST
));
562 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
| XRST
);
564 dev_err(mcbsp
[id
].dev
, "McBSP%d transmitter not "
565 "ready\n", mcbsp
[id
].id
);
570 /* We first need to enable the bus clock */
571 if (tx_word_length
> OMAP_MCBSP_WORD_16
)
572 OMAP_MCBSP_WRITE(io_base
, DXR2
, clock_word
>> 16);
573 OMAP_MCBSP_WRITE(io_base
, DXR1
, clock_word
& 0xffff);
575 /* We wait for the receiver to be ready */
576 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
577 while (!(spcr1
& RRDY
)) {
578 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
579 if (attempts
++ > 1000) {
580 /* We must reset the receiver */
581 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
& (~RRST
));
583 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
| RRST
);
585 dev_err(mcbsp
[id
].dev
, "McBSP%d receiver not "
586 "ready\n", mcbsp
[id
].id
);
591 /* Receiver is ready, there is something for us */
592 if (rx_word_length
> OMAP_MCBSP_WORD_16
)
593 word_msb
= OMAP_MCBSP_READ(io_base
, DRR2
);
594 word_lsb
= OMAP_MCBSP_READ(io_base
, DRR1
);
596 word
[0] = (word_lsb
| (word_msb
<< 16));
600 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll
);
603 * Simple DMA based buffer rx/tx routines.
604 * Nothing fancy, just a single buffer tx/rx through DMA.
605 * The DMA resources are released once the transfer is done.
606 * For anything fancier, you should use your own customized DMA
607 * routines and callbacks.
609 int omap_mcbsp_xmit_buffer(unsigned int id
, dma_addr_t buffer
,
617 if (!omap_mcbsp_check_valid_id(id
)) {
618 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
622 if (omap_request_dma(mcbsp
[id
].dma_tx_sync
, "McBSP TX",
623 omap_mcbsp_tx_dma_callback
,
626 dev_err(mcbsp
[id
].dev
, " Unable to request DMA channel for "
627 "McBSP%d TX. Trying IRQ based TX\n",
631 mcbsp
[id
].dma_tx_lch
= dma_tx_ch
;
633 dev_err(mcbsp
[id
].dev
, "McBSP%d TX DMA on channel %d\n", mcbsp
[id
].id
,
636 init_completion(&(mcbsp
[id
].tx_dma_completion
));
638 if (cpu_class_is_omap1()) {
639 src_port
= OMAP_DMA_PORT_TIPB
;
640 dest_port
= OMAP_DMA_PORT_EMIFF
;
642 if (cpu_class_is_omap2())
643 sync_dev
= mcbsp
[id
].dma_tx_sync
;
645 omap_set_dma_transfer_params(mcbsp
[id
].dma_tx_lch
,
646 OMAP_DMA_DATA_TYPE_S16
,
648 OMAP_DMA_SYNC_ELEMENT
,
651 omap_set_dma_dest_params(mcbsp
[id
].dma_tx_lch
,
653 OMAP_DMA_AMODE_CONSTANT
,
654 mcbsp
[id
].phys_base
+ OMAP_MCBSP_REG_DXR1
,
657 omap_set_dma_src_params(mcbsp
[id
].dma_tx_lch
,
659 OMAP_DMA_AMODE_POST_INC
,
663 omap_start_dma(mcbsp
[id
].dma_tx_lch
);
664 wait_for_completion(&(mcbsp
[id
].tx_dma_completion
));
668 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer
);
670 int omap_mcbsp_recv_buffer(unsigned int id
, dma_addr_t buffer
,
678 if (!omap_mcbsp_check_valid_id(id
)) {
679 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
683 if (omap_request_dma(mcbsp
[id
].dma_rx_sync
, "McBSP RX",
684 omap_mcbsp_rx_dma_callback
,
687 dev_err(mcbsp
[id
].dev
, "Unable to request DMA channel for "
688 "McBSP%d RX. Trying IRQ based RX\n",
692 mcbsp
[id
].dma_rx_lch
= dma_rx_ch
;
694 dev_err(mcbsp
[id
].dev
, "McBSP%d RX DMA on channel %d\n", mcbsp
[id
].id
,
697 init_completion(&(mcbsp
[id
].rx_dma_completion
));
699 if (cpu_class_is_omap1()) {
700 src_port
= OMAP_DMA_PORT_TIPB
;
701 dest_port
= OMAP_DMA_PORT_EMIFF
;
703 if (cpu_class_is_omap2())
704 sync_dev
= mcbsp
[id
].dma_rx_sync
;
706 omap_set_dma_transfer_params(mcbsp
[id
].dma_rx_lch
,
707 OMAP_DMA_DATA_TYPE_S16
,
709 OMAP_DMA_SYNC_ELEMENT
,
712 omap_set_dma_src_params(mcbsp
[id
].dma_rx_lch
,
714 OMAP_DMA_AMODE_CONSTANT
,
715 mcbsp
[id
].phys_base
+ OMAP_MCBSP_REG_DRR1
,
718 omap_set_dma_dest_params(mcbsp
[id
].dma_rx_lch
,
720 OMAP_DMA_AMODE_POST_INC
,
724 omap_start_dma(mcbsp
[id
].dma_rx_lch
);
725 wait_for_completion(&(mcbsp
[id
].rx_dma_completion
));
729 EXPORT_SYMBOL(omap_mcbsp_recv_buffer
);
733 * Since SPI setup is much simpler than the generic McBSP one,
734 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
735 * Once this is done, you can call omap_mcbsp_start().
737 void omap_mcbsp_set_spi_mode(unsigned int id
,
738 const struct omap_mcbsp_spi_cfg
*spi_cfg
)
740 struct omap_mcbsp_reg_cfg mcbsp_cfg
;
742 if (!omap_mcbsp_check_valid_id(id
)) {
743 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
747 memset(&mcbsp_cfg
, 0, sizeof(struct omap_mcbsp_reg_cfg
));
749 /* SPI has only one frame */
750 mcbsp_cfg
.rcr1
|= (RWDLEN1(spi_cfg
->word_length
) | RFRLEN1(0));
751 mcbsp_cfg
.xcr1
|= (XWDLEN1(spi_cfg
->word_length
) | XFRLEN1(0));
753 /* Clock stop mode */
754 if (spi_cfg
->clk_stp_mode
== OMAP_MCBSP_CLK_STP_MODE_NO_DELAY
)
755 mcbsp_cfg
.spcr1
|= (1 << 12);
757 mcbsp_cfg
.spcr1
|= (3 << 11);
759 /* Set clock parities */
760 if (spi_cfg
->rx_clock_polarity
== OMAP_MCBSP_CLK_RISING
)
761 mcbsp_cfg
.pcr0
|= CLKRP
;
763 mcbsp_cfg
.pcr0
&= ~CLKRP
;
765 if (spi_cfg
->tx_clock_polarity
== OMAP_MCBSP_CLK_RISING
)
766 mcbsp_cfg
.pcr0
&= ~CLKXP
;
768 mcbsp_cfg
.pcr0
|= CLKXP
;
770 /* Set SCLKME to 0 and CLKSM to 1 */
771 mcbsp_cfg
.pcr0
&= ~SCLKME
;
772 mcbsp_cfg
.srgr2
|= CLKSM
;
775 if (spi_cfg
->fsx_polarity
== OMAP_MCBSP_FS_ACTIVE_HIGH
)
776 mcbsp_cfg
.pcr0
&= ~FSXP
;
778 mcbsp_cfg
.pcr0
|= FSXP
;
780 if (spi_cfg
->spi_mode
== OMAP_MCBSP_SPI_MASTER
) {
781 mcbsp_cfg
.pcr0
|= CLKXM
;
782 mcbsp_cfg
.srgr1
|= CLKGDV(spi_cfg
->clk_div
- 1);
783 mcbsp_cfg
.pcr0
|= FSXM
;
784 mcbsp_cfg
.srgr2
&= ~FSGM
;
785 mcbsp_cfg
.xcr2
|= XDATDLY(1);
786 mcbsp_cfg
.rcr2
|= RDATDLY(1);
788 mcbsp_cfg
.pcr0
&= ~CLKXM
;
789 mcbsp_cfg
.srgr1
|= CLKGDV(1);
790 mcbsp_cfg
.pcr0
&= ~FSXM
;
791 mcbsp_cfg
.xcr2
&= ~XDATDLY(3);
792 mcbsp_cfg
.rcr2
&= ~RDATDLY(3);
795 mcbsp_cfg
.xcr2
&= ~XPHASE
;
796 mcbsp_cfg
.rcr2
&= ~RPHASE
;
798 omap_mcbsp_config(id
, &mcbsp_cfg
);
800 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode
);
803 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
804 * 730 has only 2 McBSP, and both of them are MPU peripherals.
806 static int __init
omap_mcbsp_probe(struct platform_device
*pdev
)
808 struct omap_mcbsp_platform_data
*pdata
= pdev
->dev
.platform_data
;
809 int id
= pdev
->id
- 1;
813 dev_err(&pdev
->dev
, "McBSP device initialized without"
819 dev_dbg(&pdev
->dev
, "Initializing OMAP McBSP (%d).\n", pdev
->id
);
821 if (id
>= OMAP_MAX_MCBSP_COUNT
) {
822 dev_err(&pdev
->dev
, "Invalid McBSP device id (%d)\n", id
);
827 spin_lock_init(&mcbsp
[id
].lock
);
828 mcbsp
[id
].id
= id
+ 1;
830 mcbsp
[id
].dma_tx_lch
= -1;
831 mcbsp
[id
].dma_rx_lch
= -1;
833 mcbsp
[id
].phys_base
= pdata
->phys_base
;
834 mcbsp
[id
].io_base
= pdata
->virt_base
;
835 /* Default I/O is IRQ based */
836 mcbsp
[id
].io_type
= OMAP_MCBSP_IRQ_IO
;
837 mcbsp
[id
].tx_irq
= pdata
->tx_irq
;
838 mcbsp
[id
].rx_irq
= pdata
->rx_irq
;
839 mcbsp
[id
].dma_rx_sync
= pdata
->dma_rx_sync
;
840 mcbsp
[id
].dma_tx_sync
= pdata
->dma_tx_sync
;
843 mcbsp
[id
].clk
= clk_get(&pdev
->dev
, pdata
->clk_name
);
844 if (IS_ERR(mcbsp
[id
].clk
)) {
847 "Invalid clock configuration for McBSP%d.\n",
853 mcbsp
[id
].pdata
= pdata
;
854 mcbsp
[id
].dev
= &pdev
->dev
;
855 platform_set_drvdata(pdev
, &mcbsp
[id
]);
861 static int omap_mcbsp_remove(struct platform_device
*pdev
)
863 struct omap_mcbsp
*mcbsp
= platform_get_drvdata(pdev
);
865 platform_set_drvdata(pdev
, NULL
);
868 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&&
869 mcbsp
->pdata
->ops
->free
)
870 mcbsp
->pdata
->ops
->free(mcbsp
->id
);
872 clk_disable(mcbsp
->clk
);
883 static struct platform_driver omap_mcbsp_driver
= {
884 .probe
= omap_mcbsp_probe
,
885 .remove
= omap_mcbsp_remove
,
887 .name
= "omap-mcbsp",
891 int __init
omap_mcbsp_init(void)
893 /* Register the McBSP driver */
894 return platform_driver_register(&omap_mcbsp_driver
);