2 * linux/arch/arm/mach-pxa/pxa3xx.c
4 * code specific to pxa3xx aka Monahans
6 * Copyright (C) 2006 Marvell International Ltd.
8 * 2007-09-02: eric miao <eric.miao@marvell.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/irq.h>
23 #include <linux/sysdev.h>
25 #include <mach/hardware.h>
26 #include <mach/pxa3xx-regs.h>
27 #include <mach/reset.h>
28 #include <mach/ohci.h>
38 /* Crystal clock: 13MHz */
39 #define BASE_CLK 13000000
41 /* Ring Oscillator Clock: 60MHz */
42 #define RO_CLK 60000000
44 #define ACCR_D0CS (1 << 26)
45 #define ACCR_PCCE (1 << 11)
47 /* crystal frequency to static memory controller multiplier (SMCFS) */
48 static unsigned char smcfs_mult
[8] = { 6, 0, 8, 0, 0, 16, };
50 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
51 static unsigned char hss_mult
[4] = { 8, 12, 16, 0 };
54 * Get the clock frequency as reflected by CCSR and the turbo flag.
55 * We assume these values have been applied via a fcs.
56 * If info is not 0 we also display the current settings.
58 unsigned int pxa3xx_get_clk_frequency_khz(int info
)
60 unsigned long acsr
, xclkcfg
;
61 unsigned int t
, xl
, xn
, hss
, ro
, XL
, XN
, CLK
, HSS
;
63 /* Read XCLKCFG register turbo bit */
64 __asm__
__volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg
));
70 xn
= (acsr
>> 8) & 0x7;
71 hss
= (acsr
>> 14) & 0x3;
76 ro
= acsr
& ACCR_D0CS
;
78 CLK
= (ro
) ? RO_CLK
: ((t
) ? XN
: XL
);
79 HSS
= (ro
) ? RO_CLK
: hss_mult
[hss
] * BASE_CLK
;
82 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
83 RO_CLK
/ 1000000, (RO_CLK
% 1000000) / 10000,
85 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
86 XL
/ 1000000, (XL
% 1000000) / 10000, xl
);
87 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
88 XN
/ 1000000, (XN
% 1000000) / 10000, xn
,
90 pr_info("HSIO bus clock: %d.%02dMHz\n",
91 HSS
/ 1000000, (HSS
% 1000000) / 10000);
98 * Return the current static memory controller clock frequency
101 unsigned int pxa3xx_get_memclk_frequency_10khz(void)
104 unsigned int smcfs
, clk
= 0;
108 smcfs
= (acsr
>> 23) & 0x7;
109 clk
= (acsr
& ACCR_D0CS
) ? RO_CLK
: smcfs_mult
[smcfs
] * BASE_CLK
;
111 return (clk
/ 10000);
114 void pxa3xx_clear_reset_status(unsigned int mask
)
116 /* RESET_STATUS_* has a 1:1 mapping with ARSR */
121 * Return the current AC97 clock frequency.
123 static unsigned long clk_pxa3xx_ac97_getrate(struct clk
*clk
)
125 unsigned long rate
= 312000000;
126 unsigned long ac97_div
;
130 /* This may loose precision for some rates but won't for the
131 * standard 24.576MHz.
133 rate
/= (ac97_div
>> 12) & 0x7fff;
134 rate
*= (ac97_div
& 0xfff);
140 * Return the current HSIO bus clock frequency
142 static unsigned long clk_pxa3xx_hsio_getrate(struct clk
*clk
)
145 unsigned int hss
, hsio_clk
;
149 hss
= (acsr
>> 14) & 0x3;
150 hsio_clk
= (acsr
& ACCR_D0CS
) ? RO_CLK
: hss_mult
[hss
] * BASE_CLK
;
155 void clk_pxa3xx_cken_enable(struct clk
*clk
)
157 unsigned long mask
= 1ul << (clk
->cken
& 0x1f);
165 void clk_pxa3xx_cken_disable(struct clk
*clk
)
167 unsigned long mask
= 1ul << (clk
->cken
& 0x1f);
175 const struct clkops clk_pxa3xx_cken_ops
= {
176 .enable
= clk_pxa3xx_cken_enable
,
177 .disable
= clk_pxa3xx_cken_disable
,
180 static const struct clkops clk_pxa3xx_hsio_ops
= {
181 .enable
= clk_pxa3xx_cken_enable
,
182 .disable
= clk_pxa3xx_cken_disable
,
183 .getrate
= clk_pxa3xx_hsio_getrate
,
186 static const struct clkops clk_pxa3xx_ac97_ops
= {
187 .enable
= clk_pxa3xx_cken_enable
,
188 .disable
= clk_pxa3xx_cken_disable
,
189 .getrate
= clk_pxa3xx_ac97_getrate
,
192 static void clk_pout_enable(struct clk
*clk
)
197 static void clk_pout_disable(struct clk
*clk
)
202 static const struct clkops clk_pout_ops
= {
203 .enable
= clk_pout_enable
,
204 .disable
= clk_pout_disable
,
207 static void clk_dummy_enable(struct clk
*clk
)
211 static void clk_dummy_disable(struct clk
*clk
)
215 static const struct clkops clk_dummy_ops
= {
216 .enable
= clk_dummy_enable
,
217 .disable
= clk_dummy_disable
,
220 static struct clk pxa3xx_clks
[] = {
223 .ops
= &clk_pout_ops
,
228 /* Power I2C clock is always on */
231 .ops
= &clk_dummy_ops
,
232 .dev
= &pxa3xx_device_i2c_power
.dev
,
235 PXA3xx_CK("LCDCLK", LCD
, &clk_pxa3xx_hsio_ops
, &pxa_device_fb
.dev
),
236 PXA3xx_CK("CAMCLK", CAMERA
, &clk_pxa3xx_hsio_ops
, NULL
),
237 PXA3xx_CK("AC97CLK", AC97
, &clk_pxa3xx_ac97_ops
, NULL
),
239 PXA3xx_CKEN("UARTCLK", FFUART
, 14857000, 1, &pxa_device_ffuart
.dev
),
240 PXA3xx_CKEN("UARTCLK", BTUART
, 14857000, 1, &pxa_device_btuart
.dev
),
241 PXA3xx_CKEN("UARTCLK", STUART
, 14857000, 1, NULL
),
243 PXA3xx_CKEN("I2CCLK", I2C
, 32842000, 0, &pxa_device_i2c
.dev
),
244 PXA3xx_CKEN("UDCCLK", UDC
, 48000000, 5, &pxa27x_device_udc
.dev
),
245 PXA3xx_CKEN("USBCLK", USBH
, 48000000, 0, &pxa27x_device_ohci
.dev
),
246 PXA3xx_CKEN("KBDCLK", KEYPAD
, 32768, 0, &pxa27x_device_keypad
.dev
),
248 PXA3xx_CKEN("SSPCLK", SSP1
, 13000000, 0, &pxa27x_device_ssp1
.dev
),
249 PXA3xx_CKEN("SSPCLK", SSP2
, 13000000, 0, &pxa27x_device_ssp2
.dev
),
250 PXA3xx_CKEN("SSPCLK", SSP3
, 13000000, 0, &pxa27x_device_ssp3
.dev
),
251 PXA3xx_CKEN("SSPCLK", SSP4
, 13000000, 0, &pxa3xx_device_ssp4
.dev
),
252 PXA3xx_CKEN("PWMCLK", PWM0
, 13000000, 0, &pxa27x_device_pwm0
.dev
),
253 PXA3xx_CKEN("PWMCLK", PWM1
, 13000000, 0, &pxa27x_device_pwm1
.dev
),
255 PXA3xx_CKEN("MMCCLK", MMC1
, 19500000, 0, &pxa_device_mci
.dev
),
256 PXA3xx_CKEN("MMCCLK", MMC2
, 19500000, 0, &pxa3xx_device_mci2
.dev
),
261 #define ISRAM_START 0x5c000000
262 #define ISRAM_SIZE SZ_256K
264 static void __iomem
*sram
;
265 static unsigned long wakeup_src
;
267 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
268 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
270 enum { SLEEP_SAVE_CKENA
,
277 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save
)
284 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save
)
292 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
293 * memory controller has to be reinitialised, so we place some code
294 * in the SRAM to perform this function.
296 * We disable FIQs across the standby - otherwise, we might receive a
297 * FIQ while the SDRAM is unavailable.
299 static void pxa3xx_cpu_standby(unsigned int pwrmode
)
301 extern const char pm_enter_standby_start
[], pm_enter_standby_end
[];
302 void (*fn
)(unsigned int) = (void __force
*)(sram
+ 0x8000);
304 memcpy_toio(sram
+ 0x8000, pm_enter_standby_start
,
305 pm_enter_standby_end
- pm_enter_standby_start
);
309 AD2D0ER
= wakeup_src
;
323 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
324 * PXA3xx development kits assumes that the resuming process continues
325 * with the address stored within the first 4 bytes of SDRAM. The PSPR
326 * register is used privately by BootROM and OBM, and _must_ be set to
327 * 0x5c014000 for the moment.
329 static void pxa3xx_cpu_pm_suspend(void)
331 volatile unsigned long *p
= (volatile void *)0xc0000000;
332 unsigned long saved_data
= *p
;
334 extern void pxa3xx_cpu_suspend(void);
335 extern void pxa3xx_cpu_resume(void);
337 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
338 CKENA
|= (1 << CKEN_BOOT
) | (1 << CKEN_TPM
);
339 CKENB
|= 1 << (CKEN_HSIO2
& 0x1f);
341 /* clear and setup wakeup source */
347 PCFR
|= (1u << 13); /* L1_DIS */
348 PCFR
&= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
352 /* overwrite with the resume address */
353 *p
= virt_to_phys(pxa3xx_cpu_resume
);
355 pxa3xx_cpu_suspend();
362 static void pxa3xx_cpu_pm_enter(suspend_state_t state
)
365 * Don't sleep if no wakeup sources are defined
367 if (wakeup_src
== 0) {
368 printk(KERN_ERR
"Not suspending: no wakeup sources\n");
373 case PM_SUSPEND_STANDBY
:
374 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2
);
378 pxa3xx_cpu_pm_suspend();
383 static int pxa3xx_cpu_pm_valid(suspend_state_t state
)
385 return state
== PM_SUSPEND_MEM
|| state
== PM_SUSPEND_STANDBY
;
388 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns
= {
389 .save_count
= SLEEP_SAVE_COUNT
,
390 .save
= pxa3xx_cpu_pm_save
,
391 .restore
= pxa3xx_cpu_pm_restore
,
392 .valid
= pxa3xx_cpu_pm_valid
,
393 .enter
= pxa3xx_cpu_pm_enter
,
396 static void __init
pxa3xx_init_pm(void)
398 sram
= ioremap(ISRAM_START
, ISRAM_SIZE
);
400 printk(KERN_ERR
"Unable to map ISRAM: disabling standby/suspend\n");
405 * Since we copy wakeup code into the SRAM, we need to ensure
406 * that it is preserved over the low power modes. Note: bit 8
407 * is undocumented in the developer manual, but must be set.
409 AD1R
|= ADXR_L2
| ADXR_R0
;
410 AD2R
|= ADXR_L2
| ADXR_R0
;
411 AD3R
|= ADXR_L2
| ADXR_R0
;
414 * Clear the resume enable registers.
421 pxa_cpu_pm_fns
= &pxa3xx_cpu_pm_fns
;
424 static int pxa3xx_set_wake(unsigned int irq
, unsigned int on
)
426 unsigned long flags
, mask
= 0;
430 mask
= ADXER_MFP_WSSP3
;
443 mask
= ADXER_MFP_WAC97
;
449 mask
= ADXER_MFP_WSSP2
;
452 mask
= ADXER_MFP_WI2C
;
455 mask
= ADXER_MFP_WUART3
;
458 mask
= ADXER_MFP_WUART2
;
461 mask
= ADXER_MFP_WUART1
;
464 mask
= ADXER_MFP_WMMC1
;
467 mask
= ADXER_MFP_WSSP1
;
473 mask
= ADXER_MFP_WSSP4
;
482 mask
= ADXER_MFP_WMMC2
;
485 mask
= ADXER_MFP_WFLASH
;
491 mask
= ADXER_WEXTWAKE0
;
494 mask
= ADXER_WEXTWAKE1
;
497 mask
= ADXER_MFP_GEN12
;
503 local_irq_save(flags
);
508 local_irq_restore(flags
);
513 static inline void pxa3xx_init_pm(void) {}
514 #define pxa3xx_set_wake NULL
517 void __init
pxa3xx_init_irq(void)
519 /* enable CP6 access */
521 __asm__
__volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value
));
523 __asm__
__volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value
));
525 pxa_init_irq(56, pxa3xx_set_wake
);
526 pxa_init_gpio(128, NULL
);
530 * device registration specific to PXA3xx.
533 void __init
pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data
*info
)
535 pxa_register_device(&pxa3xx_device_i2c_power
, info
);
538 static struct platform_device
*devices
[] __initdata
= {
539 /* &pxa_device_udc, The UDC driver is PXA25x only */
553 static struct sys_device pxa3xx_sysdev
[] = {
555 .cls
= &pxa_irq_sysclass
,
557 .cls
= &pxa3xx_mfp_sysclass
,
559 .cls
= &pxa_gpio_sysclass
,
563 static int __init
pxa3xx_init(void)
567 if (cpu_is_pxa3xx()) {
572 * clear RDH bit every time after reset
574 * Note: the last 3 bits DxS are write-1-to-clear so carefully
575 * preserve them here in case they will be referenced later
577 ASCR
&= ~(ASCR_RDH
| ASCR_D1S
| ASCR_D2S
| ASCR_D3S
);
579 clks_register(pxa3xx_clks
, ARRAY_SIZE(pxa3xx_clks
));
581 if ((ret
= pxa_init_dma(32)))
586 for (i
= 0; i
< ARRAY_SIZE(pxa3xx_sysdev
); i
++) {
587 ret
= sysdev_register(&pxa3xx_sysdev
[i
]);
589 pr_err("failed to register sysdev[%d]\n", i
);
592 ret
= platform_add_devices(devices
, ARRAY_SIZE(devices
));
598 postcore_initcall(pxa3xx_init
);