arch/arm/mach-mx5/mm.c

   1 /*
   2  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License.  You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  *
  11  * Create static mapping between physical to virtual memory.
  12  */
  13
  14 #include <linux/mm.h>
  15 #include <linux/init.h>
  16
  17 #include <asm/mach/map.h>
  18
  19 #include <mach/hardware.h>
  20 #include <mach/common.h>
  21 #include <mach/devices-common.h>
  22 #include <mach/iomux-v3.h>
  23
  24 static void imx5_idle(void)
  25 {
  26         mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
  27 }
  28
  29 /*
  30  * Define the MX50 memory map.
  31  */
  32 static struct map_desc mx50_io_desc[] __initdata = {
  33         imx_map_entry(MX50, TZIC, MT_DEVICE),
  34         imx_map_entry(MX50, SPBA0, MT_DEVICE),
  35         imx_map_entry(MX50, AIPS1, MT_DEVICE),
  36         imx_map_entry(MX50, AIPS2, MT_DEVICE),
  37 };
  38
  39 /*
  40  * Define the MX51 memory map.
  41  */
  42 static struct map_desc mx51_io_desc[] __initdata = {
  43         imx_map_entry(MX51, TZIC, MT_DEVICE),
  44         imx_map_entry(MX51, IRAM, MT_DEVICE),
  45         imx_map_entry(MX51, AIPS1, MT_DEVICE),
  46         imx_map_entry(MX51, SPBA0, MT_DEVICE),
  47         imx_map_entry(MX51, AIPS2, MT_DEVICE),
  48 };
  49
  50 /*
  51  * Define the MX53 memory map.
  52  */
  53 static struct map_desc mx53_io_desc[] __initdata = {
  54         imx_map_entry(MX53, TZIC, MT_DEVICE),
  55         imx_map_entry(MX53, AIPS1, MT_DEVICE),
  56         imx_map_entry(MX53, SPBA0, MT_DEVICE),
  57         imx_map_entry(MX53, AIPS2, MT_DEVICE),
  58 };
  59
  60 /*
  61  * This function initializes the memory map. It is called during the
  62  * system startup to create static physical to virtual memory mappings
  63  * for the IO modules.
  64  */
  65 void __init mx50_map_io(void)
  66 {
  67         iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
  68 }
  69
  70 void __init mx51_map_io(void)
  71 {
  72         iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
  73 }
  74
  75 void __init mx53_map_io(void)
  76 {
  77         iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
  78 }
  79
  80 void __init imx50_init_early(void)
  81 {
  82         mxc_set_cpu_type(MXC_CPU_MX50);
  83         mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
  84         mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
  85 }
  86
  87 void __init imx51_init_early(void)
  88 {
  89         mxc_set_cpu_type(MXC_CPU_MX51);
  90         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
  91         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
  92         imx_idle = imx5_idle;
  93 }
  94
  95 void __init imx53_init_early(void)
  96 {
  97         mxc_set_cpu_type(MXC_CPU_MX53);
  98         mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
  99         mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
 100 }
 101
 102 void __init mx50_init_irq(void)
 103 {
 104         tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
 105 }
 106
 107 void __init mx51_init_irq(void)
 108 {
 109         tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
 110 }
 111
 112 void __init mx53_init_irq(void)
 113 {
 114         tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
 115 }
 116
 117 static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
 118         .ap_2_ap_addr = 642,
 119         .uart_2_mcu_addr = 817,
 120         .mcu_2_app_addr = 747,
 121         .mcu_2_shp_addr = 961,
 122         .ata_2_mcu_addr = 1473,
 123         .mcu_2_ata_addr = 1392,
 124         .app_2_per_addr = 1033,
 125         .app_2_mcu_addr = 683,
 126         .shp_2_per_addr = 1251,
 127         .shp_2_mcu_addr = 892,
 128 };
 129
 130 static struct sdma_platform_data imx51_sdma_pdata __initdata = {
 131         .fw_name = "sdma-imx51.bin",
 132         .script_addrs = &imx51_sdma_script,
 133 };
 134
 135 static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
 136         .ap_2_ap_addr = 642,
 137         .app_2_mcu_addr = 683,
 138         .mcu_2_app_addr = 747,
 139         .uart_2_mcu_addr = 817,
 140         .shp_2_mcu_addr = 891,
 141         .mcu_2_shp_addr = 960,
 142         .uartsh_2_mcu_addr = 1032,
 143         .spdif_2_mcu_addr = 1100,
 144         .mcu_2_spdif_addr = 1134,
 145         .firi_2_mcu_addr = 1193,
 146         .mcu_2_firi_addr = 1290,
 147 };
 148
 149 static struct sdma_platform_data imx53_sdma_pdata __initdata = {
 150         .fw_name = "sdma-imx53.bin",
 151         .script_addrs = &imx53_sdma_script,
 152 };
 153
 154 void __init imx50_soc_init(void)
 155 {
 156         /* i.mx50 has the i.mx31 type gpio */
 157         mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
 158         mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
 159         mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
 160         mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
 161         mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
 162         mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
 163 }
 164
 165 void __init imx51_soc_init(void)
 166 {
 167         /* i.mx51 has the i.mx31 type gpio */
 168         mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
 169         mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
 170         mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
 171         mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
 172
 173         /* i.mx51 has the i.mx35 type sdma */
 174         imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
 175 }
 176
 177 void __init imx53_soc_init(void)
 178 {
 179         /* i.mx53 has the i.mx31 type gpio */
 180         mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
 181         mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
 182         mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
 183         mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
 184         mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
 185         mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
 186         mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
 187
 188         /* i.mx53 has the i.mx35 type sdma */
 189         imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
 190 }