12 // complete init sequence taken from bootmii's ppc skeleton. thanks to segher
13 // after a talk with dhewg we came to that point that it's good to wipe+setup BATS correctly
17 // bus checkstops off, sleep modes off,
18 // caches off, caches invalidate,
19 // store gathering off, enable data cache
20 // flush assist, enable branch target cache,
21 // enable branch history table
28 ori r4,r4,MSR_FP // MSR = 00002000 (FP on)
31 ori r3,r3,0xc000 // d-cache & i-cache enable
36 lis r3,0x8200 //bits set: H4A(HID4 access), SBE(2nd BAT enabled)
43 mtspr IBAT0U,r0; mtspr IBAT1U,r0; mtspr IBAT2U,r0; mtspr IBAT3U,r0 // IBAT0...3
44 mtspr DBAT0U,r0; mtspr DBAT1U,r0; mtspr DBAT2U,r0; mtspr DBAT3U,r0 // DBAT0...3
46 mtspr IBAT4U,r0; mtspr IBAT5U,r0; mtspr IBAT6U,r0; mtspr IBAT7U,r0 // IBAT4...7
47 mtspr DBAT4U,r0; mtspr DBAT5U,r0; mtspr DBAT6U,r0; mtspr DBAT7U,r0 // DBAT4...7
53 mtsr 0,r0; mtsr 1,r0; mtsr 2,r0; mtsr 3,r0; mtsr 4,r0; mtsr 5,r0; mtsr 6,r0
54 mtsr 7,r0; mtsr 8,r0; mtsr 9,r0; mtsr 10,r0; mtsr 11,r0; mtsr 12,r0; mtsr 13,r0
55 mtsr 14,r0; mtsr 15,r0
58 // set [DI]BAT0 for 256MB@80000000,
59 // real 00000000, WIMG=0000, R/W
70 // set [DI]BAT4 for 256MB@90000000,
71 // real 10000000, WIMG=0000, R/W
81 // set DBAT1 for 256MB@c0000000,
82 // real 00000000, WIMG=0101, R/W
91 // set DBAT5 for 256MB@d0000000,
92 // real 10000000, WIMG=0101, R/W
101 ori r3,r3,MSR_DR|MSR_IR
107 .globl __configMEM1_24Mb
109 // set [DI]BAT0 for 16Mb@80000000
110 // real 00000000, WIMG=0000, R/W
124 // set [DI]BAT2 for 8Mb@81000000
125 // real 01000000, WIMG=0000, R/W
139 ori r3,r3,MSR_DR|MSR_IR
145 .globl __configMEM1_48Mb
147 // set [DI]BAT0 for 32Mb@80000000
148 // real 00000000, WIMG=0000, R/W
162 // set [DI]BAT2 for 16Mb@82000000
163 // real 02000000, WIMG=0000, R/W
177 ori r3,r3,MSR_DR|MSR_IR
184 .globl __configMEM2_64Mb
186 // set [DI]BAT4 for 64Mb@90000000
187 // real 10000000, WIMG=0000, R/W
202 // set DBAT5 for 64Mb@d0000000
203 // real 10000000, WIMG=0101, R/W
212 ori r3,r3,MSR_DR|MSR_IR
218 .globl __configMEM2_128Mb
220 // set [DI]BAT4 for 128Mb@90000000
221 // real 10000000, WIMG=0000, R/W
236 // set DBAT5 for 128Mb@d0000000
237 // real 10000000, WIMG=0101, R/W
246 ori r3,r3,MSR_DR|MSR_IR
253 .extern ICFlashInvalidate
282 mfspr r3,HID0 # (HID0)
283 rlwinm r0,r3, 0, 16, 16
284 cmplwi r0, 0x0000 # Check if the Instruction Cache has been enabled or not.
289 mfspr r3, HID0 # bl PPCMfhid0
290 rlwinm r0, r3, 0, 17, 17
291 cmplwi r0, 0x0000 # Check if the Data Cache has been enabled or not.
297 mfspr r3, L2CR # (L2CR)
298 clrrwi r0, r3, 31 # Clear all of the bits except 31
306 # Restore the non-volatile registers to their previous values and return.
322 # Disable interrupts!
328 # Clear various SPR's
338 lis r3,0x8390 //bits set: H4A(HID4 access), SBE(2nd BAT enabled), SR0(store 0), LPE(PS LE exception), L2CFI(L2 castout prior to L2 inv. flash)
342 # Disable Speculative Bus Accesses to non-guarded space from both caches.
347 # Set the Non-IEEE mode in the FPSCR
350 mfspr r3,HID2 # (HID2)
351 rlwinm r3, r3, 0, 2, 0
352 mtspr HID2,r3 # (HID2)
354 # Restore the non-volatile registers to their previous values and return.
410 .globl SYS_SwitchFiber
428 lis r3,__configBATS@h
429 ori r3,r3,__configBATS@l