patch to make enabling 64B L2 cache optional (tueidj)
[libogc.git] / libogc / lwp_sema.inl
blob0f57c6dcda0548a9cd367feca5a51b0a2e184b8f
1 #ifndef __LWP_SEMA_INL__
2 #define __LWP_SEMA_INL__
4 static __inline__ u32 __lwp_sema_ispriority(lwp_semattr *attr)
6         return (attr->mode==LWP_SEMA_MODEPRIORITY);
9 static __inline__ void __lwp_sema_seize_isrdisable(lwp_sema *sema,u32 id,u32 wait,u32 *isrlevel)
11         lwp_cntrl *exec;
12         u32 level = *isrlevel;
14         exec = _thr_executing;
15         exec->wait.ret_code = LWP_SEMA_SUCCESSFUL;
16         if(sema->count!=0) {
17                 --sema->count;
18                 _CPU_ISR_Restore(level);
19                 return;
20         }
22         if(!wait) {
23                 _CPU_ISR_Restore(level);
24                 exec->wait.ret_code = LWP_SEMA_UNSATISFIED_NOWAIT;
25                 return;
26         }
28         __lwp_thread_dispatchdisable();
29         __lwp_threadqueue_csenter(&sema->wait_queue);
30         exec->wait.queue = &sema->wait_queue;
31         exec->wait.id = id;
32         _CPU_ISR_Restore(level);
34         __lwp_threadqueue_enqueue(&sema->wait_queue,0);
35         __lwp_thread_dispatchenable();
38 #endif