| commit | 24bc03de3f873a7b205b3c58f6c9d8aa6e9a0aaf | |
| author | torne <torne@a1c6a512-1295-4272-9138-f99709370657> | |
| Mon, 1 Feb 2010 17:16:39 +0000 (1 17:16 +0000) | ||
| committer | torne <torne@a1c6a512-1295-4272-9138-f99709370657> | |
| Mon, 1 Feb 2010 17:16:39 +0000 (1 17:16 +0000) | ||
| tree | 73172a91e509788d41ffc8f75d5d6ba3af7b21fb | treesnapshot (tar.gz zip) |
| parent | 8cf527781c571d27bf8103718d8ea8e91deeae6a | commitdiff |
Align addresses in the buffering code to STORAGE_ALIGN_MASK if the target has one.
The PP502x DMA controller can only deal with doing DMA to 16-byte-aligned
addresses because we have inadequate control over the cache to prevent
interference. Other targets may also *prefer* cacheline aligned DMAs to
reduce the number of cache operations required. Almost all disk reads in
buffering.c will now be suitably aligned, allowing DMA to be used on PP502x.
Original change from FS#9708 by Boris Gjenero (dreamlayers).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24440 a1c6a512-1295-4272-9138-f99709370657
The PP502x DMA controller can only deal with doing DMA to 16-byte-aligned
addresses because we have inadequate control over the cache to prevent
interference. Other targets may also *prefer* cacheline aligned DMAs to
reduce the number of cache operations required. Almost all disk reads in
buffering.c will now be suitably aligned, allowing DMA to be used on PP502x.
Original change from FS#9708 by Boris Gjenero (dreamlayers).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24440 a1c6a512-1295-4272-9138-f99709370657
| apps/buffering.c | diffblobblamehistory | |
| firmware/export/config.h | diffblobblamehistory |