1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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3 ;; Copyright (C) KolibriOS team 2004-2018. All rights reserved. ;;
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4 ;; Distributed under terms of the GNU General Public License ;;
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6 ;; GNU GENERAL PUBLIC LICENSE ;;
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7 ;; Version 2, June 1991 ;;
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9 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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13 vendor_id dw ? ; 0x00
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14 device_id dw ? ; 0x02
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17 revision_id db ? ; 0x08
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19 subclass db ? ; 0x0A
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20 class_code db ? ; 0x0B
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21 cache_line_size db ? ; 0x0C
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22 latency_timer db ? ; 0x0D
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23 header_type db ? ; 0x0E
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28 struct PCI_header00 PCI_header
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30 base_addr_0 dd ? ; 0x10
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31 base_addr_1 dd ? ; 0x14
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32 base_addr_2 dd ? ; 0x18
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33 base_addr_3 dd ? ; 0x1C
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34 base_addr_4 dd ? ; 0x20
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35 base_addr_5 dd ? ; 0x24
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36 cardbus_cis_ptr dd ? ; 0x28
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37 subsys_vendor dw ? ; 0x2C
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38 subsys_id dw ? ; 0x2E
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39 exp_rom_addr dd ? ; 0x30
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42 interrupt_line db ? ; 0x3C
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43 interrupt_pin db ? ; 0x3D
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44 min_grant db ? ; 0x3E
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45 max_latency db ? ; 0x3F
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49 struct PCI_header01 PCI_header
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51 base_addr_0 dd ? ; 0x10
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52 base_addr_1 dd ? ; 0x14
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53 prim_bus_nr db ? ; 0x18
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54 sec_bus_nr db ? ; 0x19
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55 sub_bus_nr db ? ; 0x1A
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56 sec_lat_tmr db ? ; 0x1B
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58 io_limit db ? ; 0x1D
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59 sec_status dw ? ; 0x1E
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60 mem_base dw ? ; 0x20
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61 mem_limit dw ? ; 0x22
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62 pref_mem_base dw ? ; 0x24
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63 pref_mem_limit dw ? ; 0x26
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64 pref_base_up dd ? ; 0x28
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65 pref_limit_up dd ? ; 0x2C
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66 io_base_up dw ? ; 0x30
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67 io_limit_up dw ? ; 0x32
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70 exp_rom_addr dd ? ; 0x38
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71 interrupt_line db ? ; 0x3C
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72 interrupt_pin db ? ; 0x3E
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73 bridge_ctrl dw ? ; 0x3F
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77 struct PCI_header02 PCI_header
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79 base_addr dd ? ; 0x10
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80 cap_list_offs db ? ; 0x14
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82 sec_stat dw ? ; 0x16
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83 pci_bus_nr db ? ; 0x18
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84 cardbus_bus_nr db ? ; 0x19
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85 sub_bus_nr db ? ; 0x1A
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86 cardbus_lat_tmr db ? ; 0x1B
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88 mlimit_0 dd ? ; 0x20
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90 mlimit_1 dd ? ; 0x28
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92 iolimit_0 dd ? ; 0x30
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94 iolimit_1 dd ? ; 0x38
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95 interrupt_line db ? ; 0x3C
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96 interrupt_pin db ? ; 0x3D
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97 bridge_ctrl dw ? ; 0x3E
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98 subs_did dw ? ; 0x40
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99 subs_vid dw ? ; 0x42
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100 legacy_bar dd ? ; 0x44
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104 ; Base address bits
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105 PCI_BASE_ADDRESS_SPACE_IO = 0x01
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106 PCI_BASE_ADDRESS_IO_MASK = 0xFFFFFFFC
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107 PCI_BASE_ADDRESS_MEM_MASK = 0xFFFFFFF0
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108 PCI_BASE_ADDRESS_MEM_TYPE_MASK = 0x00000006
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109 PCI_BASE_ADDRESS_MEM_TYPE_32 = 0x0
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110 PCI_BASE_ADDRESS_MEM_TYPE_RESERVED = 0x02
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111 PCI_BASE_ADDRESS_MEM_TYPE_64 = 0x4
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115 PCI_CMD_PIO = 0x01 ; bit0: io space control
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116 PCI_CMD_MMIO = 0x02 ; bit1: memory space control
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117 PCI_CMD_MASTER = 0x04 ; bit2: device acts as a PCI master
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118 PCI_CMD_INTX_DISABLE = 0x400 ; INTx emulation disable
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121 PCI_STATUS_CAPA = 0x10 ; bit4: new capabilities available
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124 if used PCI_find_io
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125 proc PCI_find_io stdcall bus, dev
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129 mov esi, PCI_header00.base_addr_0
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131 invoke PciRead32, [bus], [dev], esi
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132 test eax, PCI_BASE_ADDRESS_IO_MASK
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134 test eax, PCI_BASE_ADDRESS_SPACE_IO
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136 and eax, PCI_BASE_ADDRESS_IO_MASK
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142 cmp esi, PCI_header00.base_addr_5
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152 if used PCI_find_mmio
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153 proc PCI_find_mmio stdcall bus, dev
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156 mov esi, PCI_header00.base_addr_0
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158 invoke PciRead32, [bus], [dev], esi
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159 DEBUGF 1, "BAR: 0x%x\n", eax
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161 test eax, PCI_BASE_ADDRESS_SPACE_IO ; MMIO address?
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163 and ebx, PCI_BASE_ADDRESS_MEM_TYPE_MASK
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164 cmp bl, PCI_BASE_ADDRESS_MEM_TYPE_64
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166 cmp bl, PCI_BASE_ADDRESS_MEM_TYPE_32
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168 ; Ok, we have a 32-bit BAR.
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169 and eax, PCI_BASE_ADDRESS_MEM_MASK
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171 DEBUGF 1, "32-bit MMIO address found: 0x%x\n", eax
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175 ; Ok, we have a 64-bit BAR, check if the upper 32-bits are 0, then we can use it..
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178 cmp esi, PCI_header00.base_addr_5
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180 invoke PciRead32, [bus], [dev], esi
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184 and eax, PCI_BASE_ADDRESS_MEM_MASK
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186 DEBUGF 1, "64-bit MMIO address found: 0x00000000%x\n", eax
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191 cmp esi, PCI_header00.base_addr_5
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196 DEBUGF 1, "No usable MMIO addresses found!\n"
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