kstars/kstars/indi/apogee/FpgaRegs.h

   1
   2 #ifndef __FPGAREGS_H__APOGEE_APN__
   3 #define __FPGAREGS_H__APOGEE_APN__
   4
   5
   6 #define FPGA_TOTAL_REGISTER_COUNT                       103
   7
   8
   9 #define FPGA_REG_COMMAND_A                                      0
  10 #define         FPGA_BIT_CMD_EXPOSE                             0x0001
  11 #define         FPGA_BIT_CMD_DARK                               0x0002
  12 #define         FPGA_BIT_CMD_TEST                               0x0004
  13 #define         FPGA_BIT_CMD_TDI                                0x0008
  14 #define         FPGA_BIT_CMD_FLUSH                              0x0010
  15 #define         FPGA_BIT_CMD_TRIGGER_EXPOSE             0x0020
  16
  17 #define FPGA_REG_COMMAND_B                                      1
  18 #define         FPGA_BIT_CMD_RESET                              0x0002
  19 #define         FPGA_BIT_CMD_CLEAR_ALL                  0x0010
  20 #define         FPGA_BIT_CMD_END_EXPOSURE               0x0080
  21 #define         FPGA_BIT_CMD_RAMP_TO_SETPOINT   0x0200
  22 #define         FPGA_BIT_CMD_RAMP_TO_AMBIENT    0x0400
  23 #define         FPGA_BIT_CMD_START_TEMP_READ    0x2000
  24 #define         FPGA_BIT_CMD_DAC_LOAD                   0x4000
  25 #define         FPGA_BIT_CMD_AD_CONFIG                  0x8000
  26
  27 #define FPGA_REG_OP_A                                           2
  28 #define         FPGA_BIT_LED_DISABLE                    0x0001
  29 #define         FPGA_BIT_PAUSE_TIMER                    0x0002
  30 #define         FPGA_BIT_RATIO                                  0x0004
  31 #define         FPGA_BIT_DELAY_MODE                             0x0008
  32 #define         FPGA_BIT_P_CLK_MODE                             0x0010
  33 #define         FPGA_BIT_LED_EXPOSE_DISABLE             0x0020
  34 #define         FPGA_BIT_DISABLE_H_CLK                  0x0040
  35 #define         FPGA_BIT_SHUTTER_AMP_CONTROL    0x0080
  36 #define         FPGA_BIT_HALT_DISABLE                   0x0100
  37 #define         FPGA_BIT_SHUTTER_MODE                   0x0200
  38 #define         FPGA_BIT_DIGITIZATION_RES               0x0400
  39 #define         FPGA_BIT_FORCE_SHUTTER                  0x0800
  40 #define         FPGA_BIT_DISABLE_SHUTTER                0x1000
  41 #define         FPGA_BIT_TEMP_SUSPEND                   0x2000
  42 #define         FPGA_BIT_SHUTTER_SOURCE                 0x4000
  43 #define         FPGA_BIT_TEST_MODE                              0x8000
  44
  45 #define FPGA_REG_OP_B                                           3
  46 #define         FPGA_BIT_HCLAMP_ENABLE                  0x0008
  47 #define         FPGA_BIT_HSKIP_ENABLE                   0x0010
  48 #define         FPGA_BIT_HRAM_ENABLE                    0x0020
  49 #define         FPGA_BIT_VRAM_ENABLE                    0x0040
  50 #define         FPGA_BIT_DAC_SELECT_ZERO                0x0080
  51 #define         FPGA_BIT_DAC_SELECT_ONE                 0x0100
  52 #define         FPGA_BIT_AD_SIMULATION                  0x8000
  53
  54 #define FPGA_REG_TIMER_UPPER                            4
  55 #define FPGA_REG_TIMER_LOWER                            5
  56
  57 #define FPGA_REG_HRAM_INPUT                                     6
  58 #define FPGA_REG_VRAM_INPUT                                     7
  59
  60 #define FPGA_REG_HRAM_INV_MASK                          8
  61 #define FPGA_REG_VRAM_INV_MASK                          9
  62
  63 #define FPGA_REG_HCLAMP_INPUT                           10
  64 #define FPGA_REG_HSKIP_INPUT                            11
  65
  66 #define FPGA_REG_PRECLAMP_SKIP_COUNT            12
  67 #define FPGA_REG_CLAMP_COUNT                            13
  68 #define FPGA_REG_PREROI_SKIP_COUNT                      14
  69 #define FPGA_REG_ROI_COUNT                                      15
  70 #define FPGA_REG_POSTROI_SKIP_COUNT                     16
  71 #define FPGA_REG_OVERSCAN_COUNT                         17
  72 #define FPGA_REG_IMAGE_COUNT                            18
  73
  74 #define FPGA_REG_VFLUSH_BINNING                         19
  75
  76 #define FPGA_REG_SHUTTER_CLOSE_DELAY            20
  77
  78 #define FPGA_REG_POSTOVERSCAN_SKIP_COUNT        21
  79
  80 #define FPGA_REG_SHUTTER_STROBE_POSITION        23
  81 #define FPGA_REG_SHUTTER_STROBE_PERIOD          24
  82
  83 #define FPGA_REG_FAN_SPEED_CONTROL                      25
  84 #define FPGA_REG_LED_DRIVE                                      26
  85 #define FPGA_REG_SUBSTRATE_ADJUST                       27
  86 #define FPGA_MASK_FAN_SPEED_CONTROL                     0x0FFF
  87 #define FPGA_MASK_LED_ILLUMINATION                      0x0FFF
  88 #define FPGA_MASK_SUBSTRATE_ADJUST                      0x0FFF
  89
  90 #define FPGA_REG_TEST_COUNT_UPPER                       28
  91 #define FPGA_REG_TEST_COUNT_LOWER                       29
  92
  93 #define FPGA_REG_A1_ROW_COUNT                           30
  94 #define FPGA_REG_A1_VBINNING                            31
  95 #define FPGA_REG_A2_ROW_COUNT                           32
  96 #define FPGA_REG_A2_VBINNING                            33
  97 #define FPGA_REG_A3_ROW_COUNT                           34
  98 #define FPGA_REG_A3_VBINNING                            35
  99
 100 #define FPGA_MASK_VBINNING                                      0x0FFF
 101 #define FPGA_BIT_ARRAY_DIGITIZE                         0x1000
 102 #define FPGA_BIT_ARRAY_FASTDUMP                         0x4000
 103
 104 #define FPGA_REG_SEQUENCE_DELAY                         47
 105 #define FPGA_REG_TDI_RATE                                       48
 106
 107 #define FPGA_REG_IO_PORT_WRITE                          49
 108
 109 #define FPGA_REG_IO_PORT_DIRECTION                      50
 110 #define FPGA_MASK_IO_PORT_DIRECTION                     0x003F
 111
 112 #define FPGA_REG_IO_PORT_ASSIGNMENT                     51
 113 #define FPGA_MASK_IO_PORT_ASSIGNMENT            0x003F
 114
 115 #define FPGA_REG_LED_SELECT                                     52
 116 #define FPGA_MASK_LED_SELECT_A                          0x000F
 117 #define FPGA_MASK_LED_SELECT_B                          0x00F0
 118 #define         FPGA_BIT_LED_EXPOSE                             0x0001
 119 #define         FPGA_BIT_LED_IMAGE_ACTIVE               0x0002
 120 #define         FPGA_BIT_LED_FLUSHING                   0x0004
 121 #define         FPGA_BIT_LED_TRIGGER_WAIT               0x0008
 122 #define         FPGA_BIT_LED_EXT_TRIGGER                0x0010
 123 #define         FPGA_BIT_LED_EXT_SHUTTER_INPUT  0x0020
 124 #define         FPGA_BIT_LED_EXT_START_READOUT  0x0040
 125 #define         FPGA_BIT_LED_AT_TEMP                    0x0080
 126
 127 #define FPGA_REG_SCRATCH                                        53
 128
 129 #define FPGA_REG_TDI_COUNT                                      54
 130
 131 #define FPGA_REG_TEMP_DESIRED                           55
 132
 133 #define FPGA_REG_TEMP_RAMP_DOWN_A                       57
 134 #define FPGA_REG_TEMP_RAMP_DOWN_B                       58
 135 #define FPGA_REG_TEMP_BACKOFF                           60
 136 #define FPGA_REG_TEMP_COOLER_OVERRIDE           61
 137 #define FPGA_MASK_TEMP_PARAMS                           0x0FFF          // 12 bits
 138
 139 #define FPGA_REG_AD_CONFIG_DATA                         62
 140 #define FPGA_MASK_AD_GAIN                                       0x07FF          // 11 bits
 141
 142 #define FPGA_REG_IO_PORT_READ                           90
 143 #define FPGA_MASK_IO_PORT_DATA                          0x003F
 144
 145 #define FPGA_REG_GENERAL_STATUS                                 91
 146 #define         FPGA_BIT_STATUS_IMAGE_EXPOSING          0x0001
 147 #define         FPGA_BIT_STATUS_IMAGING_ACTIVE          0x0002
 148 #define         FPGA_BIT_STATUS_DATA_HALTED                     0x0004
 149 #define         FPGA_BIT_STATUS_IMAGE_DONE                      0x0008
 150 #define         FPGA_BIT_STATUS_FLUSHING                        0x0010
 151 #define         FPGA_BIT_STATUS_WAITING_TRIGGER         0x0020
 152 #define         FPGA_BIT_STATUS_SHUTTER_OPEN            0x0040
 153 #define         FPGA_BIT_STATUS_PATTERN_ERROR           0x0080
 154 #define         FPGA_BIT_STATUS_TEMP_SUSPEND_ACK        0x0100
 155 #define         FPGA_BIT_STATUS_TEMP_REVISION           0x2000
 156 #define         FPGA_BIT_STATUS_TEMP_AT_TEMP            0x4000
 157 #define         FPGA_BIT_STATUS_TEMP_ACTIVE                     0x8000
 158
 159 #define FPGA_REG_TEMP_HEATSINK                          93
 160 #define FPGA_REG_TEMP_CCD                                       94
 161 #define FPGA_REG_TEMP_DRIVE                                     95
 162
 163 #define FPGA_REG_INPUT_VOLTAGE                          96
 164 #define FPGA_MASK_INPUT_VOLTAGE                         0x0FFF
 165
 166 #define FPGA_REG_TEMP_REVISED                           97
 167
 168 #define FPGA_REG_FIFO_DATA                                      98
 169 #define FPGA_REG_FIFO_STATUS                            99
 170
 171 #define FPGA_REG_CAMERA_ID                                      100
 172 #define FPGA_MASK_CAMERA_ID                                     0x007F
 173
 174 #define FPGA_REG_FIRMWARE_REV                           101
 175
 176 #define FPGA_REG_FIFO_FULL_COUNT                        102
 177 #define FPGA_REG_FIFO_EMPTY_COUNT                       103
 178
 179 #define FPGA_REG_TDI_COUNTER                            104
 180 #define FPGA_REG_SEQUENCE_COUNTER                       105
 181
 182 #endif