src/arch/powerpc.h

   1 /*
   2  * Copyright (C) 2003, 2004, 2005, 2006, 2007
   3  * Robert Lougher <rob@lougher.org.uk>.
   4  *
   5  * This file is part of JamVM.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2,
  10  * or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  20  */
  21
  22 #define OS_ARCH "ppc"
  23
  24 #define HANDLER_TABLE_T static const void
  25 #define DOUBLE_1_BITS 0x3ff0000000000000LL
  26
  27 #define READ_DBL(v,p,l) v = ((u8)p[0]<<56)|((u8)p[1]<<48)|((u8)p[2]<<40) \
  28                             |((u8)p[3]<<32)|((u8)p[4]<<24)|((u8)p[5]<<16) \
  29                             |((u8)p[6]<<8)|(u8)p[7]; p+=8
  30
  31 /* Needed for i386 -- empty here */
  32 #define FPU_HACK
  33
  34 #ifdef __ppc64__
  35 #define COMPARE_AND_SWAP(addr, old_val, new_val)    \
  36 ({                                                  \
  37     int result, read_val;                           \
  38     __asm__ __volatile__ ("                         \
  39                 li %0,0\n                           \
  40         1:      ldarx %1,0,%2\n                     \
  41                 cmpd %3,%1\n                        \
  42                 bne- 2f\n                           \
  43                 stdcx. %4,0,%2\n                    \
  44                 bne- 1b\n                           \
  45                 li %0,1\n                           \
  46         2:"                                         \
  47     : "=&r" (result), "=&r" (read_val)              \
  48     : "r" (addr), "r" (old_val), "r" (new_val)      \
  49     : "cc", "memory");                              \
  50     result;                                         \
  51 })
  52
  53 #define COMPARE_AND_SWAP_64(addr, old_val, new_val) \
  54         COMPARE_AND_SWAP(addr, old_val, new_val)
  55
  56 #else
  57 #define COMPARE_AND_SWAP(addr, old_val, new_val)    \
  58 ({                                                  \
  59     int result, read_val;                           \
  60     __asm__ __volatile__ ("                         \
  61                 li %0,0\n                           \
  62         1:      lwarx %1,0,%2\n                     \
  63                 cmpw %3,%1\n                        \
  64                 bne- 2f\n                           \
  65                 stwcx. %4,0,%2\n                    \
  66                 bne- 1b\n                           \
  67                 li %0,1\n                           \
  68         2:"                                         \
  69     : "=&r" (result), "=&r" (read_val)              \
  70     : "r" (addr), "r" (old_val), "r" (new_val)      \
  71     : "cc", "memory");                              \
  72     result;                                         \
  73 })
  74 #endif
  75
  76 #define LOCKWORD_READ(addr) *addr
  77 #define LOCKWORD_WRITE(addr, value) *addr = value
  78 #define LOCKWORD_COMPARE_AND_SWAP(addr, old_val, new_val) \
  79         COMPARE_AND_SWAP(addr, old_val, new_val)
  80
  81 #define CACHE_LINE_LEN 32
  82
  83 #define FLUSH_CACHE(addr, length)                   \
  84 {                                                   \
  85     uintptr_t end = ((uintptr_t) addr) + length;    \
  86     uintptr_t start = ((uintptr_t) addr)            \
  87                       & ~(CACHE_LINE_LEN - 1);      \
  88     uintptr_t i;                                    \
  89                                                     \
  90     for(i = start; i < end; i += CACHE_LINE_LEN)    \
  91         __asm__ ("dcbst 0, %0" :: "r" (i));         \
  92                                                     \
  93     __asm__ ("sync");                               \
  94                                                     \
  95     for(i = start; i < end; i += CACHE_LINE_LEN)    \
  96         __asm__ ("icbi 0, %0" :: "r" (i));          \
  97                                                     \
  98     __asm__ ("sync; isync");                        \
  99 }
 100
 101 #define MBARRIER() __asm__ __volatile__ ("sync" ::: "memory")
 102 #define UNLOCK_MBARRIER() __asm__ __volatile__ ("sync" ::: "memory")
 103 #define JMM_LOCK_MBARRIER() __asm__ __volatile__ ("isync" ::: "memory")
 104 #define JMM_UNLOCK_MBARRIER() __asm__ __volatile__ ("lwsync" ::: "memory")