Fix LDC, LDC_W, and INSTANCEOF opcodes, more debugging
[jamvm-avr32-jem.git] / src / arch / arm.h
blobccf68c4a0ea3c98128edb0ccb48db12769f26f8c
1 /*
2 * Copyright (C) 2003, 2004, 2005, 2006, 2007
3 * Robert Lougher <rob@lougher.org.uk>.
5 * This file is part of JamVM.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2,
10 * or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 #define OS_ARCH "arm"
24 /* Override default min and max heap sizes. ARM machines are
25 usually embedded, and the standard defaults are too large. */
26 #define DEFAULT_MAX_HEAP 16*MB
27 #define DEFAULT_MIN_HEAP 1*MB
29 #ifdef DIRECT
30 #define HANDLER_TABLE_T static const void
31 #else
32 #define HANDLER_TABLE_T void
33 #endif
35 #if defined(__VFP_FP__) || defined(__ARMEB__)
36 #define DOUBLE_1_BITS 0x3ff0000000000000LL
37 #else
38 #define DOUBLE_1_BITS 0x000000003ff00000LL
39 #endif
41 #if defined(__VFP_FP__) || defined(__ARMEB__)
42 #define READ_DBL(v,p,l) v = ((u8)p[0]<<56)|((u8)p[1]<<48)|((u8)p[2]<<40) \
43 |((u8)p[3]<<32)|((u8)p[4]<<24)|((u8)p[5]<<16) \
44 |((u8)p[6]<<8)|(u8)p[7]; p+=8
45 #else
46 #define READ_DBL(v,p,l) v = ((u8)p[4]<<56)|((u8)p[5]<<48)|((u8)p[6]<<40) \
47 |((u8)p[7]<<32)|((u8)p[0]<<24)|((u8)p[1]<<16) \
48 |((u8)p[2]<<8)|(u8)p[3]; p+=8
49 #endif
51 /* Needed for i386 -- empty here */
52 #define FPU_HACK
54 #define LOCKWORD_COMPARE_AND_SWAP(addr, old_val, new_val) \
55 ({ \
56 int result, read_val; \
57 __asm__ __volatile__ (" \
58 mvn %1, #1; \
59 1: swp %1, %1, [%2]; \
60 cmn %1, #2; \
61 beq 1b; \
62 cmp %3, %1; \
63 strne %1, [%2]; \
64 movne %0, #0; \
65 streq %4, [%2]; \
66 moveq %0, #1;" \
67 : "=&r" (result), "=&r" (read_val) \
68 : "r" (addr), "r" (old_val), "r" (new_val) \
69 : "cc", "memory"); \
70 result; \
73 #define LOCKWORD_READ(addr) \
74 ({ \
75 int read_val; \
76 __asm__ __volatile__ (" \
77 1: ldr %0, [%1]; \
78 cmn %0, #2; \
79 beq 1b;" \
80 : "=&r" (read_val) : "r" (addr) : "cc"); \
81 read_val; \
84 #define LOCKWORD_WRITE(addr, new_val) \
85 do { \
86 int read_val; \
87 __asm__ __volatile__ (" \
88 mvn %0, #1; \
89 1: swp %0, %0, [%1]; \
90 cmn %0, #2; \
91 beq 1b; \
92 str %2, [%1];" \
93 : "=&r" (read_val) \
94 : "r" (addr), "r" (new_val) \
95 : "cc", "memory"); \
96 } while(0)
99 #ifdef __ARM_EABI__
100 #define FLUSH_CACHE(addr, length) \
102 __asm__ __volatile__ (" \
103 mov r0, %0\n \
104 mov r1, %1\n \
105 mov r2, #0\n \
106 mov r7, #0xf0000\n \
107 add r7, r7, #2\n \
108 swi 0\n \
109 ": \
110 : "r" (addr), "r" (addr + length - 1) \
111 : "r0", "r1", "r2", "r7"); \
113 #else
114 #define FLUSH_CACHE(addr, length) \
116 __asm__ __volatile__ (" \
117 mov r0, %0\n \
118 mov r1, %1\n \
119 mov r2, #0\n \
120 swi 0x9f0002\n \
121 ": \
122 : "r" (addr), "r" (addr + length - 1) \
123 : "r0", "r1", "r2"); \
125 #endif
127 #define MBARRIER() __asm__ __volatile__ ("" ::: "memory")
128 #define UNLOCK_MBARRIER() __asm__ __volatile__ ("" ::: "memory")
129 #define JMM_LOCK_MBARRIER() __asm__ __volatile__ ("" ::: "memory")
130 #define JMM_UNLOCK_MBARRIER() __asm__ __volatile__ ("" ::: "memory")