isl_38xx.h

   1 /*  $Header: /var/lib/cvs/prism54-usb/isl_38xx.h,v 1.1.1.1 2004/04/16 18:12:11 mcgrof Exp $
   2  *
   3  *  Copyright (C) 2002 Intersil Americas Inc.
   4  *
   5  *  This program is free software; you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License as published by
   7  *  the Free Software Foundation; either version 2 of the License
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, write to the Free Software
  16  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  17  *
  18  */
  19
  20 #ifndef _ISL_38XX_H
  21 #define _ISL_38XX_H
  22
  23 #include <linux/version.h>
  24 #include <asm/io.h>
  25
  26 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,75))
  27 #include <linux/device.h>
  28 # define _REQ_FW_DEV_T struct device *
  29 #else
  30 # define _REQ_FW_DEV_T char *
  31 #endif
  32
  33 #include <asm/byteorder.h>
  34
  35 #define ISL38XX_CB_RX_QSIZE                     8
  36 #define ISL38XX_CB_TX_QSIZE                     32
  37
  38 /* ISL38XX Access Point Specific definitions */
  39 #define ISL38XX_MAX_WDS_LINKS                   8
  40
  41 /* ISL38xx Client Specific definitions */
  42 #define ISL38XX_PSM_ACTIVE_STATE                0
  43 #define ISL38XX_PSM_POWERSAVE_STATE             1
  44
  45 /* ISL38XX Host Interface Definitions */
  46 #define ISL38XX_PCI_MEM_SIZE                    0x02000
  47 #define ISL38XX_MEMORY_WINDOW_SIZE              0x01000
  48 #define ISL38XX_DEV_FIRMWARE_ADDRES             0x20000
  49 #define ISL38XX_WRITEIO_DELAY                   10      /* in us */
  50 #define ISL38XX_RESET_DELAY                     50      /* in ms */
  51 #define ISL38XX_WAIT_CYCLE                      10      /* in 10ms */
  52 #define ISL38XX_MAX_WAIT_CYCLES                 10
  53
  54 /* PCI Memory Area */
  55 #define ISL38XX_HARDWARE_REG                    0x0000
  56 #define ISL38XX_CARDBUS_CIS                     0x0800
  57 #define ISL38XX_DIRECT_MEM_WIN                  0x1000
  58
  59 /* Hardware registers */
  60 #define ISL38XX_DEV_INT_REG                     0x0000
  61 #define ISL38XX_INT_IDENT_REG                   0x0010
  62 #define ISL38XX_INT_ACK_REG                     0x0014
  63 #define ISL38XX_INT_EN_REG                      0x0018
  64 #define ISL38XX_GEN_PURP_COM_REG_1              0x0020
  65 #define ISL38XX_GEN_PURP_COM_REG_2              0x0024
  66 #define ISL38XX_CTRL_BLK_BASE_REG               ISL38XX_GEN_PURP_COM_REG_1
  67 #define ISL38XX_DIR_MEM_BASE_REG                0x0030
  68 #define ISL38XX_CTRL_STAT_REG                   0x0078
  69
  70 /* High end mobos queue up pci writes, the following
  71  * is used to "read" from after a write to force flush */
  72 #define ISL38XX_PCI_POSTING_FLUSH               ISL38XX_INT_EN_REG
  73
  74 /**
  75  * isl38xx_w32_flush - PCI iomem write helper
  76  * @base: (host) memory base address of the device
  77  * @val: 32bit value (host order) to write
  78  * @offset: byte offset into @base to write value to
  79  *
  80  *  This helper takes care of writing a 32bit datum to the
  81  *  specified offset into the device's pci memory space, and making sure
  82  *  the pci memory buffers get flushed by performing one harmless read
  83  *  from the %ISL38XX_PCI_POSTING_FLUSH offset.
  84  */
  85 static inline void
  86 isl38xx_w32_flush(void *base, u32 val, unsigned long offset)
  87 {
  88         writel(val, base + offset);
  89         (void) readl(base + ISL38XX_PCI_POSTING_FLUSH);
  90 }
  91
  92 /* Device Interrupt register bits */
  93 #define ISL38XX_DEV_INT_RESET                   0x0001
  94 #define ISL38XX_DEV_INT_UPDATE                  0x0002
  95 #define ISL38XX_DEV_INT_WAKEUP                  0x0008
  96 #define ISL38XX_DEV_INT_SLEEP                   0x0010
  97 #define ISL38XX_DEV_INT_ABORT                   (1 << 5)
  98 #define ISL38XX_DEV_INT_DATA                    0x0040
  99 #define ISL38XX_DEV_INT_MGMT                    0x0080
 100 #define ISL38XX_DEV_INT_PCIUART_CTS             (1 << 14)
 101 #define ISL38XX_DEV_INT_PCIUART_DR              (1 << 15)
 102
 103
 104 /* Interrupt Identification/Acknowledge/Enable register bits */
 105 #define ISL38XX_INT_IDENT_UPDATE                0x0002
 106 #define ISL38XX_INT_IDENT_INIT                  0x0004
 107 #define ISL38XX_INT_IDENT_WAKEUP                0x0008
 108 #define ISL38XX_INT_IDENT_SLEEP                 0x0010
 109 #define ISL38XX_INT_IDENT_PCIUART_CTS           (1 << 14)
 110 #define ISL38XX_INT_IDENT_PCIUART_DR            (1 << 15)
 111 #define ISL38XX_INT_SOURCES                     0x001E
 112
 113 /* Control/Status register bits */
 114 #define ISL38XX_CTRL_STAT_SLEEPMODE             0x00000200
 115 #define ISL38XX_CTRL_STAT_CLKRUN                0x00800000
 116 #define ISL38XX_CTRL_STAT_RESET                 0x10000000
 117 #define ISL38XX_CTRL_STAT_RAMBOOT               0x20000000
 118 #define ISL38XX_CTRL_STAT_STARTHALTED           0x40000000
 119 #define ISL38XX_CTRL_STAT_HOST_OVERRIDE         0x80000000
 120
 121 /* Control Block definitions */
 122 #define ISL38XX_CB_RX_DATA_LQ                   0
 123 #define ISL38XX_CB_TX_DATA_LQ                   1
 124 #define ISL38XX_CB_RX_DATA_HQ                   2
 125 #define ISL38XX_CB_TX_DATA_HQ                   3
 126 #define ISL38XX_CB_RX_MGMTQ                     4
 127 #define ISL38XX_CB_TX_MGMTQ                     5
 128 #define ISL38XX_CB_QCOUNT                       6
 129 #define ISL38XX_CB_MGMT_QSIZE                   4
 130 #define ISL38XX_MIN_QTHRESHOLD                  4       /* fragments */
 131
 132 /* Memory Manager definitions */
 133 #define MGMT_FRAME_SIZE                         1500    /* >= size struct obj_bsslist */
 134 #define MGMT_TX_FRAME_COUNT                     24      /* max 4 + spare 4 + 8 init */
 135 #define MGMT_RX_FRAME_COUNT                     24      /* 4*4 + spare 8 */
 136 #define MGMT_FRAME_COUNT                        (MGMT_TX_FRAME_COUNT + MGMT_RX_FRAME_COUNT)
 137 #define CONTROL_BLOCK_SIZE                      1024    /* should be enough */
 138 #define PSM_FRAME_SIZE                          1536
 139 #define PSM_MINIMAL_STATION_COUNT               64
 140 #define PSM_FRAME_COUNT                         PSM_MINIMAL_STATION_COUNT
 141 #define PSM_BUFFER_SIZE                         PSM_FRAME_SIZE * PSM_FRAME_COUNT
 142 #define MAX_TRAP_RX_QUEUE                       4
 143 #define HOST_MEM_BLOCK                          CONTROL_BLOCK_SIZE + PSM_BUFFER_SIZE
 144
 145 /* Fragment package definitions */
 146 #define FRAGMENT_FLAG_MF                        0x0001
 147 #define MAX_FRAGMENT_SIZE                       1536
 148
 149 /* In monitor mode frames have a header. I don't know exactly how big those
 150  * frame can be but I've never seen any frame bigger than 1584... :
 151  */
 152 #define MAX_FRAGMENT_SIZE_RX                    1600
 153
 154 typedef struct {
 155         u32 address;            /* physical address on host */
 156         u16 size;               /* packet size */
 157         u16 flags;              /* set of bit-wise flags */
 158 } isl38xx_fragment;
 159
 160 struct isl38xx_cb {
 161         u32 driver_curr_frag[ISL38XX_CB_QCOUNT];
 162         u32 device_curr_frag[ISL38XX_CB_QCOUNT];
 163         isl38xx_fragment rx_data_low[ISL38XX_CB_RX_QSIZE];
 164         isl38xx_fragment tx_data_low[ISL38XX_CB_TX_QSIZE];
 165         isl38xx_fragment rx_data_high[ISL38XX_CB_RX_QSIZE];
 166         isl38xx_fragment tx_data_high[ISL38XX_CB_TX_QSIZE];
 167         isl38xx_fragment rx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
 168         isl38xx_fragment tx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
 169 };
 170
 171 typedef struct isl38xx_cb isl38xx_control_block;
 172
 173 /* determine number of entries currently in queue */
 174 int isl38xx_in_queue(isl38xx_control_block *cb, int queue);
 175
 176 void isl38xx_disable_interrupts(void *);
 177 void isl38xx_enable_common_interrupts(void *);
 178
 179 void isl38xx_handle_sleep_request(isl38xx_control_block *, int *,
 180                                   void *);
 181 void isl38xx_handle_wakeup(isl38xx_control_block *, int *, void *);
 182 void isl38xx_trigger_device(int, void *);
 183 void isl38xx_interface_reset(void *, dma_addr_t);
 184
 185 int isl38xx_upload_firmware(char *, _REQ_FW_DEV_T, void *, dma_addr_t);
 186
 187 #endif                          /* _ISL_38XX_H */