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57 #ifndef _E1000_REGS_H_
58 #define _E1000_REGS_H_
64 #define E1000_CTRL 0x00000 /* Device Control - RW */
65 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
66 #define E1000_STATUS 0x00008 /* Device Status - RO */
67 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
68 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
69 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
70 #define E1000_FLA 0x0001C /* Flash Access - RW */
71 #define E1000_MDIC 0x00020 /* MDI Control - RW */
72 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
73 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
74 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
75 #define E1000_FEXT 0x0002C /* Future Extended - RW */
76 #define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
77 #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */
78 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
79 #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
80 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
81 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
82 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
83 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
84 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
85 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
86 #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
87 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
88 #define E1000_SVCR 0x000F0
89 #define E1000_SVT 0x000F4
90 #define E1000_RCTL 0x00100 /* Rx Control - RW */
91 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
92 #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
93 #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
94 #define E1000_PBA_ECC 0x01100 /* PBA ECC Register */
95 #define E1000_TCTL 0x00400 /* Tx Control - RW */
96 #define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
97 #define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */
98 #define E1000_TBT 0x00448 /* Tx Burst Timer - RW */
99 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
100 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
101 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
102 #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
103 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
104 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
105 #define E1000_PBS 0x01008 /* Packet Buffer Size */
106 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
107 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
108 #define E1000_FLASHT 0x01028 /* FLASH Timer Register */
109 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
110 #define E1000_FLSWCTL 0x01030 /* FLASH control register */
111 #define E1000_FLSWDATA 0x01034 /* FLASH data register */
112 #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
113 #define E1000_FLOP 0x0103C /* FLASH Opcode Register */
114 #define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */
115 #define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
116 #define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */
117 #define E1000_SWDSTS 0x01044 /* SW Device Status - RW */
118 #define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */
119 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
120 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
121 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
122 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
123 #define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n)))
124 #define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
125 #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
126 /* Split and Replication Rx Control - RW */
127 #define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */
128 #define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */
129 #define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */
130 #define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */
131 #define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */
132 #define E1000_RXCTL(_n) (0x0C014 + (0x40 * (_n)))
133 #define E1000_RQDPC(_n) (0x0C030 + (0x40 * (_n)))
134 #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */
135 #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
139 * Note: "_n" is the queue number of the register to be written to.
142 * E1000_RDBAL_REG(current_rx_queue)
144 #define E1000_RDBAL(_n) \
145 ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : (0x0C000 + ((_n) * 0x40)))
146 #define E1000_RDBAH(_n) \
147 ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : (0x0C004 + ((_n) * 0x40)))
148 #define E1000_RDLEN(_n) \
149 ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : (0x0C008 + ((_n) * 0x40)))
150 #define E1000_SRRCTL(_n) \
151 ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : (0x0C00C + ((_n) * 0x40)))
152 #define E1000_RDH(_n) \
153 ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : (0x0C010 + ((_n) * 0x40)))
154 #define E1000_RDT(_n) \
155 ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : (0x0C018 + ((_n) * 0x40)))
156 #define E1000_RXDCTL(_n) \
157 ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : (0x0C028 + ((_n) * 0x40)))
158 #define E1000_TDBAL(_n) \
159 ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : (0x0E000 + ((_n) * 0x40)))
160 #define E1000_TDBAH(_n) \
161 ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : (0x0E004 + ((_n) * 0x40)))
162 #define E1000_TDLEN(_n) \
163 ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : (0x0E008 + ((_n) * 0x40)))
164 #define E1000_TDH(_n) \
165 ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : (0x0E010 + ((_n) * 0x40)))
166 #define E1000_TDT(_n) \
167 ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : (0x0E018 + ((_n) * 0x40)))
168 #define E1000_TXDCTL(_n) \
169 ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : (0x0E028 + ((_n) * 0x40)))
170 #define E1000_TARC(_n) (0x03840 + (_n << 8))
171 #define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))
172 #define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))
173 #define E1000_TDWBAL(_n) \
174 ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : (0x0E038 + ((_n) * 0x40)))
175 #define E1000_TDWBAH(_n) \
176 ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : (0x0E03C + ((_n) * 0x40)))
177 #define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */
178 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
179 #define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */
180 #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
181 #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4))
182 #define E1000_RAL(_i) \
183 (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x054E0 + ((_i - 16) * 8)))
184 #define E1000_RAH(_i) \
185 (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x054E4 + ((_i - 16) * 8)))
186 #define E1000_SHRAL(_i) (0x05438 + ((_i) * 8))
187 #define E1000_SHRAH(_i) (0x0543C + ((_i) * 8))
188 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
189 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
190 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
191 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
192 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
193 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
194 #define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
195 #define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
196 #define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
197 #define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
198 #define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
199 #define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */
200 #define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */
201 #define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */
202 #define E1000_TDPURD 0x03588 /* DMA Tx Descriptor uC Data Read - RW */
203 #define E1000_TDPUCTL 0x0358C /* DMA Tx Descriptor uC Control - RW */
204 #define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */
205 #define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */
206 #define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */
207 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
208 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
209 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
210 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
211 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
212 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
213 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
214 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
215 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
216 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
217 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
218 #define E1000_DC 0x04030 /* Defer Count - R/clr */
219 #define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */
220 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
221 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
222 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
223 #define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */
224 #define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */
225 #define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */
226 #define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */
227 #define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */
228 #define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */
229 #define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */
230 #define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */
231 #define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */
232 #define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */
233 #define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */
234 #define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */
235 #define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */
236 #define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */
237 #define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */
238 #define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */
239 #define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */
240 #define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */
241 #define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */
242 #define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */
243 #define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */
244 #define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */
245 #define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */
246 #define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */
247 #define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */
248 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
249 #define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */
250 #define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */
251 #define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */
252 #define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */
253 #define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */
254 #define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */
255 #define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */
256 #define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */
257 #define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */
258 #define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */
259 #define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */
260 #define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */
261 #define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */
262 #define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */
263 #define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */
264 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */
265 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */
266 #define E1000_IAC 0x04100 /* Interrupt Assertion Count */
267 /* Interrupt Cause Rx Pkt Timer Expire Count */
268 #define E1000_ICRXPTC 0x04104
269 /* Interrupt Cause Rx Abs Timer Expire Count */
270 #define E1000_ICRXATC 0x04108
271 /* Interrupt Cause Tx Pkt Timer Expire Count */
272 #define E1000_ICTXPTC 0x0410C
273 /* Interrupt Cause Tx Abs Timer Expire Count */
274 #define E1000_ICTXATC 0x04110
275 /* Interrupt Cause Tx Queue Empty Count */
276 #define E1000_ICTXQEC 0x04118
277 /* Interrupt Cause Tx Queue Min Thresh Count */
278 #define E1000_ICTXQMTC 0x0411C
279 /* Interrupt Cause Rx Desc Min Thresh Count */
280 #define E1000_ICRXDMTC 0x04120
281 /* Interrupt Cause Receiver Overrun Count */
282 #define E1000_ICRXOC 0x04124
284 #define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */
286 #define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */
287 #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */
288 #define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */
289 #define E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */
290 #define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */
291 #define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */
292 #define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */
293 #define E1000_RPTHC 0x04104 /* Rx Packets To Host */
294 #define E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */
295 #define E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */
296 #define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */
297 #define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */
298 #define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */
299 #define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */
300 #define E1000_LENERRS 0x04138 /* Length Errors Count */
301 #define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */
302 #define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */
303 #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */
304 #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
305 #define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */
306 #define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */
307 #define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Packet Count - RW */
308 #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */
309 #define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */
310 #define E1000_RFCTL 0x05008 /* Receive Filter Control */
311 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
312 #define E1000_RA 0x05400 /* Receive Address - RW Array */
313 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
314 #define E1000_VT_CTL 0x0581C /* VMDq Control - RW */
315 #define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */
316 #define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */
317 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
318 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
319 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
320 #define E1000_MANC 0x05820 /* Management Control - RW */
321 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
322 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
323 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
324 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
325 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
326 #define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */
327 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
328 #define E1000_HOST_IF 0x08800 /* Host Interface */
329 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
330 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
332 #define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
333 #define E1000_MDPHYA 0x0003C /* PHY address - RW */
334 #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
335 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
336 #define E1000_CCMCTL 0x05B48 /* CCM Control Register */
337 #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */
338 #define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */
339 #define E1000_GCR 0x05B00 /* PCI-Ex Control */
340 #define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */
341 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
342 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
343 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
344 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
345 #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
346 #define E1000_SWSM 0x05B50 /* SW Semaphore */
347 #define E1000_FWSM 0x05B54 /* FW Semaphore */
348 /* Driver-only SW semaphore (not used by BOOT agents) */
349 #define E1000_SWSM2 0x05B58
350 #define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */
351 #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */
352 #define E1000_FFLT_DBG 0x05F04 /* Debug Register */
353 #define E1000_HICR 0x08F00 /* Host Interface Control */
356 #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
357 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
358 #define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */
359 #define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext */
360 #define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */
361 /* MSI-X Allocation Register (_i) - RW */
362 #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4))
363 /* MSI-X Table entry addr low reg - RW */
364 #define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10))
365 /* MSI-X Table entry addr upper reg - RW */
366 #define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10))
367 /* MSI-X Table entry message reg - RW */
368 #define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10))
369 /* MSI-X Table entry vector ctrl reg - RW */
370 #define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10))
371 #define E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */
372 #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
373 #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
374 #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
375 #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
376 #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
377 #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */
383 #endif /* _E1000_REGS_H_ */
