usr/src/uts/common/io/e1000g/e1000_phy.h

   1 /*
   2  * This file is provided under a CDDLv1 license.  When using or
   3  * redistributing this file, you may do so under this license.
   4  * In redistributing this file this license must be included
   5  * and no other modification of this header file is permitted.
   6  *
   7  * CDDL LICENSE SUMMARY
   8  *
   9  * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
  10  *
  11  * The contents of this file are subject to the terms of Version
  12  * 1.0 of the Common Development and Distribution License (the "License").
  13  *
  14  * You should have received a copy of the License with this software.
  15  * You can obtain a copy of the License at
  16  *      http://www.opensolaris.org/os/licensing.
  17  * See the License for the specific language governing permissions
  18  * and limitations under the License.
  19  */
  20
  21 /*
  22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms of the CDDLv1.
  24  */
  25
  26 /*
  27  * Copyright (c) 2001-2010, Intel Corporation
  28  * All rights reserved.
  29  *
  30  * Redistribution and use in source and binary forms, with or without
  31  * modification, are permitted provided that the following conditions are met:
  32  *
  33  *  1. Redistributions of source code must retain the above copyright notice,
  34  *     this list of conditions and the following disclaimer.
  35  *
  36  *  2. Redistributions in binary form must reproduce the above copyright
  37  *     notice, this list of conditions and the following disclaimer in the
  38  *     documentation and/or other materials provided with the distribution.
  39  *
  40  *  3. Neither the name of the Intel Corporation nor the names of its
  41  *     contributors may be used to endorse or promote products derived from
  42  *     this software without specific prior written permission.
  43  *
  44  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  45  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  46  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  47  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  48  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  54  * POSSIBILITY OF SUCH DAMAGE.
  55  */
  56
  57 #ifndef _E1000_PHY_H_
  58 #define _E1000_PHY_H_
  59
  60 #ifdef __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 void e1000_init_phy_ops_generic(struct e1000_hw *hw);
  65 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
  66 void e1000_null_phy_generic(struct e1000_hw *hw);
  67 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active);
  68 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
  69 s32 e1000_check_downshift_generic(struct e1000_hw *hw);
  70 s32 e1000_check_polarity_m88(struct e1000_hw *hw);
  71 s32 e1000_check_polarity_igp(struct e1000_hw *hw);
  72 s32 e1000_check_polarity_ife(struct e1000_hw *hw);
  73 s32 e1000_check_reset_block_generic(struct e1000_hw *hw);
  74 s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
  75 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw);
  76 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw);
  77 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
  78 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
  79 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
  80 s32 e1000_get_cable_length_m88(struct e1000_hw *hw);
  81 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw);
  82 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw);
  83 s32 e1000_get_phy_id(struct e1000_hw *hw);
  84 s32 e1000_get_phy_info_igp(struct e1000_hw *hw);
  85 s32 e1000_get_phy_info_m88(struct e1000_hw *hw);
  86 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw);
  87 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
  88 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw);
  89 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
  90 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
  91 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
  92 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
  93 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
  94 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
  95 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
  96 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
  97 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw);
  98 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw);
  99 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
 100 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
 101 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
 102 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
 103 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
 104 s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
 105 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
 106     u32 usec_interval, bool *success);
 107 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw);
 108 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
 109 s32 e1000_determine_phy_address(struct e1000_hw *hw);
 110 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
 111 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
 112 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
 113 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
 114 void e1000_power_up_phy_copper(struct e1000_hw *hw);
 115 void e1000_power_down_phy_copper(struct e1000_hw *hw);
 116 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
 117 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
 118 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
 119 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
 120 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
 121 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
 122 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
 123 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
 124 s32 e1000_check_polarity_82577(struct e1000_hw *hw);
 125 s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
 126 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
 127 s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
 128
 129 #define E1000_MAX_PHY_ADDR              4
 130
 131 /* IGP01E1000 Specific Registers */
 132 #define IGP01E1000_PHY_PORT_CONFIG      0x10 /* Port Config */
 133 #define IGP01E1000_PHY_PORT_STATUS      0x11 /* Status */
 134 #define IGP01E1000_PHY_PORT_CTRL        0x12 /* Control */
 135 #define IGP01E1000_PHY_LINK_HEALTH      0x13 /* PHY Link Health */
 136 #define IGP01E1000_GMII_FIFO            0x14 /* GMII FIFO */
 137 #define IGP01E1000_PHY_CHANNEL_QUALITY  0x15 /* PHY Channel Quality */
 138 #define IGP02E1000_PHY_POWER_MGMT       0x19 /* Power Management */
 139 #define IGP01E1000_PHY_PAGE_SELECT      0x1F /* Page Select */
 140 #define BM_PHY_PAGE_SELECT              22   /* Page Select for BM */
 141 #define IGP_PAGE_SHIFT                  5
 142 #define PHY_REG_MASK                    0x1F
 143
 144 /* BM/HV Specific Registers */
 145 #define BM_PORT_CTRL_PAGE               769
 146 #define BM_PCIE_PAGE                    770
 147 #define BM_WUC_PAGE                     800
 148 #define BM_WUC_ADDRESS_OPCODE           0x11
 149 #define BM_WUC_DATA_OPCODE              0x12
 150 #define BM_WUC_ENABLE_PAGE              BM_PORT_CTRL_PAGE
 151 #define BM_WUC_ENABLE_REG               17
 152 #define BM_WUC_ENABLE_BIT               (1 << 2)
 153 #define BM_WUC_HOST_WU_BIT              (1 << 4)
 154
 155 #define PHY_UPPER_SHIFT                 21
 156 #define BM_PHY_REG(page, reg) \
 157         (((reg) & MAX_PHY_REG_ADDRESS) |\
 158         (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
 159         (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
 160 #define BM_PHY_REG_PAGE(offset) \
 161         ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
 162 #define BM_PHY_REG_NUM(offset) \
 163         ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
 164         (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
 165         ~MAX_PHY_REG_ADDRESS)))
 166
 167 #define HV_INTC_FC_PAGE_START           768
 168 #define I82578_ADDR_REG                 29
 169 #define I82577_ADDR_REG                 16
 170 #define I82577_CFG_REG                  22
 171 #define I82577_CFG_ASSERT_CRS_ON_TX     (1 << 15)
 172 #define I82577_CFG_ENABLE_DOWNSHIFT     (3 << 10) /* auto downshift 100/10 */
 173 #define I82577_CTRL_REG                 23
 174 #define I82577_CTRL_DOWNSHIFT_MASK      (7 << 10)
 175
 176 /* 82577 specific PHY registers */
 177 #define I82577_PHY_CTRL_2               18
 178 #define I82577_PHY_LBK_CTRL             19
 179 #define I82577_PHY_STATUS_2             26
 180 #define I82577_PHY_DIAG_STATUS          31
 181
 182 /* I82577 PHY Status 2 */
 183 #define I82577_PHY_STATUS2_REV_POLARITY         0x0400
 184 #define I82577_PHY_STATUS2_MDIX                 0x0800
 185 #define I82577_PHY_STATUS2_SPEED_MASK           0x0300
 186 #define I82577_PHY_STATUS2_SPEED_1000MBPS       0x0200
 187 #define I82577_PHY_STATUS2_SPEED_100MBPS        0x0100
 188
 189 /* I82577 PHY Control 2 */
 190 #define I82577_PHY_CTRL2_AUTO_MDIX              0x0400
 191 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX         0x0200
 192
 193 /* I82577 PHY Diagnostics Status */
 194 #define I82577_DSTATUS_CABLE_LENGTH             0x03FC
 195 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT       2
 196
 197 /* BM PHY Copper Specific Control 1 */
 198 #define BM_CS_CTRL1                     16
 199 #define BM_CS_CTRL1_ENERGY_DETECT       0x0300  /* Enable Energy Detect */
 200
 201 /* BM PHY Copper Specific Status */
 202 #define BM_CS_STATUS                    17
 203 #define BM_CS_STATUS_ENERGY_DETECT      0x0010  /* Energy Detect Status */
 204 #define BM_CS_STATUS_LINK_UP            0x0400
 205 #define BM_CS_STATUS_RESOLVED           0x0800
 206 #define BM_CS_STATUS_SPEED_MASK         0xC000
 207 #define BM_CS_STATUS_SPEED_1000         0x8000
 208
 209 /* 82577 Mobile Phy Status Register */
 210 #define HV_M_STATUS                     26
 211 #define HV_M_STATUS_AUTONEG_COMPLETE    0x1000
 212 #define HV_M_STATUS_SPEED_MASK          0x0300
 213 #define HV_M_STATUS_SPEED_1000          0x0200
 214 #define HV_M_STATUS_LINK_UP             0x0040
 215
 216 #define IGP01E1000_PHY_PCS_INIT_REG     0x00B4
 217 #define IGP01E1000_PHY_POLARITY_MASK    0x0078
 218
 219 #define IGP01E1000_PSCR_AUTO_MDIX       0x1000
 220 #define IGP01E1000_PSCR_FORCE_MDI_MDIX  0x2000  /* 0=MDI, 1=MDIX */
 221
 222 #define IGP01E1000_PSCFR_SMART_SPEED    0x0080
 223
 224 /* Enable flexible speed on link-up */
 225 #define IGP01E1000_GMII_FLEX_SPD        0x0010
 226 #define IGP01E1000_GMII_SPD             0x0020  /* Enable SPD */
 227
 228 #define IGP02E1000_PM_SPD               0x0001  /* Smart Power Down */
 229 #define IGP02E1000_PM_D0_LPLU           0x0002  /* For D0a states */
 230 #define IGP02E1000_PM_D3_LPLU           0x0004  /* For all other states */
 231
 232 #define IGP01E1000_PLHR_SS_DOWNGRADE    0x8000
 233
 234 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
 235 #define IGP01E1000_PSSR_MDIX            0x0800
 236 #define IGP01E1000_PSSR_SPEED_MASK      0xC000
 237 #define IGP01E1000_PSSR_SPEED_1000MBPS  0xC000
 238
 239 #define IGP02E1000_PHY_CHANNEL_NUM      4
 240 #define IGP02E1000_PHY_AGC_A            0x11B1
 241 #define IGP02E1000_PHY_AGC_B            0x12B1
 242 #define IGP02E1000_PHY_AGC_C            0x14B1
 243 #define IGP02E1000_PHY_AGC_D            0x18B1
 244
 245 #define IGP02E1000_AGC_LENGTH_SHIFT     9 /* Course - 15:13, Fine - 12:9 */
 246 #define IGP02E1000_AGC_LENGTH_MASK      0x7F
 247 #define IGP02E1000_AGC_RANGE            15
 248
 249 #define IGP03E1000_PHY_MISC_CTRL        0x1B
 250 #define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */
 251
 252 #define E1000_CABLE_LENGTH_UNDEFINED    0xFF
 253
 254 #define E1000_KMRNCTRLSTA_OFFSET        0x001F0000
 255 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT  16
 256 #define E1000_KMRNCTRLSTA_REN           0x00200000
 257 #define E1000_KMRNCTRLSTA_CTRL_OFFSET   0x1     /* Kumeran Control */
 258 #define E1000_KMRNCTRLSTA_DIAG_OFFSET   0x3     /* Kumeran Diagnostic */
 259 #define E1000_KMRNCTRLSTA_TIMEOUTS      0x4     /* Kumeran Timeouts */
 260 #define E1000_KMRNCTRLSTA_INBAND_PARAM  0x9     /* Kumeran InBand Parameters */
 261 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200  /* Kumeran IBIST Disable */
 262 #define E1000_KMRNCTRLSTA_DIAG_NELPBK   0x1000  /* Nearend Loopback mode */
 263 #define E1000_KMRNCTRLSTA_K1_CONFIG     0x7
 264 #define E1000_KMRNCTRLSTA_K1_ENABLE     0x0002
 265 #define E1000_KMRNCTRLSTA_HD_CTRL       0x10    /* Kumeran HD Control */
 266
 267 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
 268 #define IFE_PHY_SPECIAL_CONTROL         0x11 /* 100BaseTx PHY Special Control */
 269 #define IFE_PHY_SPECIAL_CONTROL_LED     0x1B /* PHY Special and LED Control */
 270 #define IFE_PHY_MDIX_CONTROL            0x1C /* MDI/MDI-X Control */
 271
 272 /* IFE PHY Extended Status Control */
 273 #define IFE_PESC_POLARITY_REVERSED      0x0100
 274
 275 /* IFE PHY Special Control */
 276 #define IFE_PSC_AUTO_POLARITY_DISABLE   0x0010
 277 #define IFE_PSC_FORCE_POLARITY          0x0020
 278 #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
 279
 280 /* IFE PHY Special Control and LED Control */
 281 #define IFE_PSCL_PROBE_MODE             0x0020
 282 #define IFE_PSCL_PROBE_LEDS_OFF         0x0006 /* Force LEDs 0 and 2 off */
 283 #define IFE_PSCL_PROBE_LEDS_ON          0x0007 /* Force LEDs 0 and 2 on */
 284
 285 /* IFE PHY MDIX Control */
 286 #define IFE_PMC_MDIX_STATUS     0x0020 /* 1=MDI-X, 0=MDI */
 287 #define IFE_PMC_FORCE_MDIX      0x0040 /* 1=force MDI-X, 0=force MDI */
 288 #define IFE_PMC_AUTO_MDIX       0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
 289
 290 #ifdef __cplusplus
 291 }
 292 #endif
 293
 294 #endif  /* _E1000_PHY_H_ */