2 * This file is provided under a CDDLv1 license. When using or
3 * redistributing this file, you may do so under this license.
4 * In redistributing this file this license must be included
5 * and no other modification of this header file is permitted.
9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
11 * The contents of this file are subject to the terms of Version
12 * 1.0 of the Common Development and Distribution License (the "License").
14 * You should have received a copy of the License with this software.
15 * You can obtain a copy of the License at
16 * http://www.opensolaris.org/os/licensing.
17 * See the License for the specific language governing permissions
18 * and limitations under the License.
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms of the CDDLv1.
27 * Copyright (c) 2001-2010, Intel Corporation
28 * All rights reserved.
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions are met:
33 * 1. Redistributions of source code must retain the above copyright notice,
34 * this list of conditions and the following disclaimer.
36 * 2. Redistributions in binary form must reproduce the above copyright
37 * notice, this list of conditions and the following disclaimer in the
38 * documentation and/or other materials provided with the distribution.
40 * 3. Neither the name of the Intel Corporation nor the names of its
41 * contributors may be used to endorse or promote products derived from
42 * this software without specific prior written permission.
44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
45 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
48 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
54 * POSSIBILITY OF SUCH DAMAGE.
57 #include "e1000_api.h"
59 static u32
e1000_get_phy_addr_for_bm_page(u32 page
, u32 reg
);
60 static s32
e1000_access_phy_wakeup_reg_bm(struct e1000_hw
*hw
, u32 offset
,
61 u16
*data
, bool read
);
63 static u32
e1000_get_phy_addr_for_hv_page(u32 page
);
64 static s32
e1000_access_phy_debug_regs_hv(struct e1000_hw
*hw
, u32 offset
,
65 u16
*data
, bool read
);
67 /* Cable length tables */
68 static const u16 e1000_m88_cable_length_table
[] =
69 {0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
};
71 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
72 (sizeof (e1000_m88_cable_length_table) / \
73 sizeof (e1000_m88_cable_length_table[0]))
75 static const u16 e1000_igp_2_cable_length_table
[] =
76 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
77 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
78 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
79 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
80 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
81 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
82 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
83 104, 109, 114, 118, 121, 124};
85 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
86 (sizeof (e1000_igp_2_cable_length_table) / \
87 sizeof (e1000_igp_2_cable_length_table[0]))
90 * e1000_init_phy_ops_generic - Initialize PHY function pointers
91 * @hw: pointer to the HW structure
93 * Setups up the function pointers to no-op functions
96 e1000_init_phy_ops_generic(struct e1000_hw
*hw
)
98 struct e1000_phy_info
*phy
= &hw
->phy
;
99 DEBUGFUNC("e1000_init_phy_ops_generic");
101 /* Initialize function pointers */
102 phy
->ops
.init_params
= e1000_null_ops_generic
;
103 phy
->ops
.acquire
= e1000_null_ops_generic
;
104 phy
->ops
.check_polarity
= e1000_null_ops_generic
;
105 phy
->ops
.check_reset_block
= e1000_null_ops_generic
;
106 phy
->ops
.commit
= e1000_null_ops_generic
;
107 phy
->ops
.force_speed_duplex
= e1000_null_ops_generic
;
108 phy
->ops
.get_cfg_done
= e1000_null_ops_generic
;
109 phy
->ops
.get_cable_length
= e1000_null_ops_generic
;
110 phy
->ops
.get_info
= e1000_null_ops_generic
;
111 phy
->ops
.read_reg
= e1000_null_read_reg
;
112 phy
->ops
.read_reg_locked
= e1000_null_read_reg
;
113 phy
->ops
.release
= e1000_null_phy_generic
;
114 phy
->ops
.reset
= e1000_null_ops_generic
;
115 phy
->ops
.set_d0_lplu_state
= e1000_null_lplu_state
;
116 phy
->ops
.set_d3_lplu_state
= e1000_null_lplu_state
;
117 phy
->ops
.write_reg
= e1000_null_write_reg
;
118 phy
->ops
.write_reg_locked
= e1000_null_write_reg
;
119 phy
->ops
.power_up
= e1000_null_phy_generic
;
120 phy
->ops
.power_down
= e1000_null_phy_generic
;
121 phy
->ops
.cfg_on_link_up
= e1000_null_ops_generic
;
125 * e1000_null_read_reg - No-op function, return 0
126 * @hw: pointer to the HW structure
129 e1000_null_read_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
131 DEBUGFUNC("e1000_null_read_reg");
132 UNREFERENCED_3PARAMETER(hw
, offset
, data
);
133 return (E1000_SUCCESS
);
137 * e1000_null_phy_generic - No-op function, return void
138 * @hw: pointer to the HW structure
141 e1000_null_phy_generic(struct e1000_hw
*hw
)
143 DEBUGFUNC("e1000_null_phy_generic");
144 UNREFERENCED_1PARAMETER(hw
);
148 * e1000_null_lplu_state - No-op function, return 0
149 * @hw: pointer to the HW structure
152 e1000_null_lplu_state(struct e1000_hw
*hw
, bool active
)
154 DEBUGFUNC("e1000_null_lplu_state");
155 UNREFERENCED_2PARAMETER(hw
, active
);
156 return (E1000_SUCCESS
);
160 * e1000_null_write_reg - No-op function, return 0
161 * @hw: pointer to the HW structure
164 e1000_null_write_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
)
166 DEBUGFUNC("e1000_null_write_reg");
167 UNREFERENCED_3PARAMETER(hw
, offset
, data
);
168 return (E1000_SUCCESS
);
172 * e1000_check_reset_block_generic - Check if PHY reset is blocked
173 * @hw: pointer to the HW structure
175 * Read the PHY management control register and check whether a PHY reset
176 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
177 * return E1000_BLK_PHY_RESET (12).
180 e1000_check_reset_block_generic(struct e1000_hw
*hw
)
184 DEBUGFUNC("e1000_check_reset_block");
186 manc
= E1000_READ_REG(hw
, E1000_MANC
);
188 return ((manc
& E1000_MANC_BLK_PHY_RST_ON_IDE
) ?
189 E1000_BLK_PHY_RESET
: E1000_SUCCESS
);
193 * e1000_get_phy_id - Retrieve the PHY ID and revision
194 * @hw: pointer to the HW structure
196 * Reads the PHY registers and stores the PHY ID and possibly the PHY
197 * revision in the hardware structure.
200 e1000_get_phy_id(struct e1000_hw
*hw
)
202 struct e1000_phy_info
*phy
= &hw
->phy
;
203 s32 ret_val
= E1000_SUCCESS
;
207 DEBUGFUNC("e1000_get_phy_id");
209 if (!(phy
->ops
.read_reg
))
212 while (retry_count
< 2) {
213 ret_val
= phy
->ops
.read_reg(hw
, PHY_ID1
, &phy_id
);
217 phy
->id
= (u32
)(phy_id
<< 16);
219 ret_val
= phy
->ops
.read_reg(hw
, PHY_ID2
, &phy_id
);
223 phy
->id
|= (u32
)(phy_id
& PHY_REVISION_MASK
);
224 phy
->revision
= (u32
)(phy_id
& ~PHY_REVISION_MASK
);
226 if (phy
->id
!= 0 && phy
->id
!= PHY_REVISION_MASK
)
236 * e1000_phy_reset_dsp_generic - Reset PHY DSP
237 * @hw: pointer to the HW structure
239 * Reset the digital signal processor.
242 e1000_phy_reset_dsp_generic(struct e1000_hw
*hw
)
244 s32 ret_val
= E1000_SUCCESS
;
246 DEBUGFUNC("e1000_phy_reset_dsp_generic");
248 if (!(hw
->phy
.ops
.write_reg
))
251 ret_val
= hw
->phy
.ops
.write_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xC1);
255 ret_val
= hw
->phy
.ops
.write_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0);
262 * e1000_read_phy_reg_mdic - Read MDI control register
263 * @hw: pointer to the HW structure
264 * @offset: register offset to be read
265 * @data: pointer to the read data
267 * Reads the MDI control register in the PHY at offset and stores the
268 * information read to data.
271 e1000_read_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
273 struct e1000_phy_info
*phy
= &hw
->phy
;
275 s32 ret_val
= E1000_SUCCESS
;
277 DEBUGFUNC("e1000_read_phy_reg_mdic");
280 * Set up Op-code, Phy Address, and register offset in the MDI Control
281 * register. The MAC will take care of interfacing with the PHY to
282 * retrieve the desired data.
284 mdic
= ((offset
<< E1000_MDIC_REG_SHIFT
) |
285 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
286 (E1000_MDIC_OP_READ
));
288 E1000_WRITE_REG(hw
, E1000_MDIC
, mdic
);
291 * Poll the ready bit to see if the MDI read completed
292 * Increasing the time out as testing showed failures with
295 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
297 mdic
= E1000_READ_REG(hw
, E1000_MDIC
);
298 if (mdic
& E1000_MDIC_READY
)
301 if (!(mdic
& E1000_MDIC_READY
)) {
302 DEBUGOUT("MDI Read did not complete\n");
303 ret_val
= -E1000_ERR_PHY
;
306 if (mdic
& E1000_MDIC_ERROR
) {
307 DEBUGOUT("MDI Error\n");
308 ret_val
= -E1000_ERR_PHY
;
314 * Allow some time after each MDIC transaction to avoid
315 * reading duplicate data in the next MDIC transaction.
317 if (hw
->mac
.type
== e1000_pch2lan
)
325 * e1000_write_phy_reg_mdic - Write MDI control register
326 * @hw: pointer to the HW structure
327 * @offset: register offset to write to
328 * @data: data to write to register at offset
330 * Writes data to MDI control register in the PHY at offset.
333 e1000_write_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16 data
)
335 struct e1000_phy_info
*phy
= &hw
->phy
;
337 s32 ret_val
= E1000_SUCCESS
;
339 DEBUGFUNC("e1000_write_phy_reg_mdic");
342 * Set up Op-code, Phy Address, and register offset in the MDI Control
343 * register. The MAC will take care of interfacing with the PHY to
344 * retrieve the desired data.
346 mdic
= (((u32
)data
) |
347 (offset
<< E1000_MDIC_REG_SHIFT
) |
348 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
349 (E1000_MDIC_OP_WRITE
));
351 E1000_WRITE_REG(hw
, E1000_MDIC
, mdic
);
354 * Poll the ready bit to see if the MDI read completed
355 * Increasing the time out as testing showed failures with
358 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
360 mdic
= E1000_READ_REG(hw
, E1000_MDIC
);
361 if (mdic
& E1000_MDIC_READY
)
364 if (!(mdic
& E1000_MDIC_READY
)) {
365 DEBUGOUT("MDI Write did not complete\n");
366 ret_val
= -E1000_ERR_PHY
;
369 if (mdic
& E1000_MDIC_ERROR
) {
370 DEBUGOUT("MDI Error\n");
371 ret_val
= -E1000_ERR_PHY
;
376 * Allow some time after each MDIC transaction to avoid
377 * reading duplicate data in the next MDIC transaction.
379 if (hw
->mac
.type
== e1000_pch2lan
)
387 * e1000_read_phy_reg_m88 - Read m88 PHY register
388 * @hw: pointer to the HW structure
389 * @offset: register offset to be read
390 * @data: pointer to the read data
392 * Acquires semaphore, if necessary, then reads the PHY register at offset
393 * and storing the retrieved information in data. Release any acquired
394 * semaphores before exiting.
397 e1000_read_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
399 s32 ret_val
= E1000_SUCCESS
;
401 DEBUGFUNC("e1000_read_phy_reg_m88");
403 if (!(hw
->phy
.ops
.acquire
))
406 ret_val
= hw
->phy
.ops
.acquire(hw
);
410 ret_val
= e1000_read_phy_reg_mdic(hw
,
411 MAX_PHY_REG_ADDRESS
& offset
,
414 hw
->phy
.ops
.release(hw
);
421 * e1000_write_phy_reg_m88 - Write m88 PHY register
422 * @hw: pointer to the HW structure
423 * @offset: register offset to write to
424 * @data: data to write at register offset
426 * Acquires semaphore, if necessary, then writes the data to PHY register
427 * at the offset. Release any acquired semaphores before exiting.
430 e1000_write_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16 data
)
432 s32 ret_val
= E1000_SUCCESS
;
434 DEBUGFUNC("e1000_write_phy_reg_m88");
436 if (!(hw
->phy
.ops
.acquire
))
439 ret_val
= hw
->phy
.ops
.acquire(hw
);
443 ret_val
= e1000_write_phy_reg_mdic(hw
,
444 MAX_PHY_REG_ADDRESS
& offset
,
447 hw
->phy
.ops
.release(hw
);
454 * e1000_read_phy_reg_igp - Read igp PHY register
455 * @hw: pointer to the HW structure
456 * @offset: register offset to be read
457 * @data: pointer to the read data
458 * @locked: semaphore has already been acquired or not
460 * Acquires semaphore, if necessary, then reads the PHY register at offset
461 * and stores the retrieved information in data. Release any acquired
462 * semaphores before exiting.
465 __e1000_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
468 s32 ret_val
= E1000_SUCCESS
;
470 DEBUGFUNC("__e1000_read_phy_reg_igp");
473 if (!(hw
->phy
.ops
.acquire
))
476 ret_val
= hw
->phy
.ops
.acquire(hw
);
481 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
482 ret_val
= e1000_write_phy_reg_mdic(hw
,
483 IGP01E1000_PHY_PAGE_SELECT
, (u16
)offset
);
488 ret_val
= e1000_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
493 hw
->phy
.ops
.release(hw
);
499 * e1000_read_phy_reg_igp - Read igp PHY register
500 * @hw: pointer to the HW structure
501 * @offset: register offset to be read
502 * @data: pointer to the read data
504 * Acquires semaphore then reads the PHY register at offset and stores the
505 * retrieved information in data.
506 * Release the acquired semaphore before exiting.
509 e1000_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
511 return (__e1000_read_phy_reg_igp(hw
, offset
, data
, false));
515 * e1000_read_phy_reg_igp_locked - Read igp PHY register
516 * @hw: pointer to the HW structure
517 * @offset: register offset to be read
518 * @data: pointer to the read data
520 * Reads the PHY register at offset and stores the retrieved information
521 * in data. Assumes semaphore already acquired.
524 e1000_read_phy_reg_igp_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
526 return (__e1000_read_phy_reg_igp(hw
, offset
, data
, true));
530 * e1000_write_phy_reg_igp - Write igp PHY register
531 * @hw: pointer to the HW structure
532 * @offset: register offset to write to
533 * @data: data to write at register offset
534 * @locked: semaphore has already been acquired or not
536 * Acquires semaphore, if necessary, then writes the data to PHY register
537 * at the offset. Release any acquired semaphores before exiting.
540 __e1000_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
,
543 s32 ret_val
= E1000_SUCCESS
;
545 DEBUGFUNC("e1000_write_phy_reg_igp");
548 if (!(hw
->phy
.ops
.acquire
))
551 ret_val
= hw
->phy
.ops
.acquire(hw
);
556 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
557 ret_val
= e1000_write_phy_reg_mdic(hw
,
558 IGP01E1000_PHY_PAGE_SELECT
, (u16
)offset
);
563 ret_val
= e1000_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
568 hw
->phy
.ops
.release(hw
);
575 * e1000_write_phy_reg_igp - Write igp PHY register
576 * @hw: pointer to the HW structure
577 * @offset: register offset to write to
578 * @data: data to write at register offset
580 * Acquires semaphore then writes the data to PHY register
581 * at the offset. Release any acquired semaphores before exiting.
584 e1000_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
)
586 return (__e1000_write_phy_reg_igp(hw
, offset
, data
, false));
590 * e1000_write_phy_reg_igp_locked - Write igp PHY register
591 * @hw: pointer to the HW structure
592 * @offset: register offset to write to
593 * @data: data to write at register offset
595 * Writes the data to PHY register at the offset.
596 * Assumes semaphore already acquired.
599 e1000_write_phy_reg_igp_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
601 return (__e1000_write_phy_reg_igp(hw
, offset
, data
, true));
605 * __e1000_read_kmrn_reg - Read kumeran register
606 * @hw: pointer to the HW structure
607 * @offset: register offset to be read
608 * @data: pointer to the read data
609 * @locked: semaphore has already been acquired or not
611 * Acquires semaphore, if necessary. Then reads the PHY register at offset
612 * using the kumeran interface. The information retrieved is stored in data.
613 * Release any acquired semaphores before exiting.
616 __e1000_read_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
, bool locked
)
619 s32 ret_val
= E1000_SUCCESS
;
621 DEBUGFUNC("__e1000_read_kmrn_reg");
624 if (!(hw
->phy
.ops
.acquire
))
627 ret_val
= hw
->phy
.ops
.acquire(hw
);
632 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
633 E1000_KMRNCTRLSTA_OFFSET
) | E1000_KMRNCTRLSTA_REN
;
634 E1000_WRITE_REG(hw
, E1000_KMRNCTRLSTA
, kmrnctrlsta
);
638 kmrnctrlsta
= E1000_READ_REG(hw
, E1000_KMRNCTRLSTA
);
639 *data
= (u16
)kmrnctrlsta
;
642 hw
->phy
.ops
.release(hw
);
649 * e1000_read_kmrn_reg_generic - Read kumeran register
650 * @hw: pointer to the HW structure
651 * @offset: register offset to be read
652 * @data: pointer to the read data
654 * Acquires semaphore then reads the PHY register at offset using the
655 * kumeran interface. The information retrieved is stored in data.
656 * Release the acquired semaphore before exiting.
659 e1000_read_kmrn_reg_generic(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
661 return (__e1000_read_kmrn_reg(hw
, offset
, data
, false));
665 * e1000_read_kmrn_reg_locked - Read kumeran register
666 * @hw: pointer to the HW structure
667 * @offset: register offset to be read
668 * @data: pointer to the read data
670 * Reads the PHY register at offset using the kumeran interface. The
671 * information retrieved is stored in data.
672 * Assumes semaphore already acquired.
675 e1000_read_kmrn_reg_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
677 return (__e1000_read_kmrn_reg(hw
, offset
, data
, true));
681 * __e1000_write_kmrn_reg - Write kumeran register
682 * @hw: pointer to the HW structure
683 * @offset: register offset to write to
684 * @data: data to write at register offset
685 * @locked: semaphore has already been acquired or not
687 * Acquires semaphore, if necessary. Then write the data to PHY register
688 * at the offset using the kumeran interface. Release any acquired semaphores
692 __e1000_write_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
, bool locked
)
695 s32 ret_val
= E1000_SUCCESS
;
697 DEBUGFUNC("e1000_write_kmrn_reg_generic");
700 if (!(hw
->phy
.ops
.acquire
))
703 ret_val
= hw
->phy
.ops
.acquire(hw
);
708 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
709 E1000_KMRNCTRLSTA_OFFSET
) | data
;
710 E1000_WRITE_REG(hw
, E1000_KMRNCTRLSTA
, kmrnctrlsta
);
715 hw
->phy
.ops
.release(hw
);
722 * e1000_write_kmrn_reg_generic - Write kumeran register
723 * @hw: pointer to the HW structure
724 * @offset: register offset to write to
725 * @data: data to write at register offset
727 * Acquires semaphore then writes the data to the PHY register at the offset
728 * using the kumeran interface. Release the acquired semaphore before exiting.
731 e1000_write_kmrn_reg_generic(struct e1000_hw
*hw
, u32 offset
, u16 data
)
733 return (__e1000_write_kmrn_reg(hw
, offset
, data
, false));
737 * e1000_write_kmrn_reg_locked - Write kumeran register
738 * @hw: pointer to the HW structure
739 * @offset: register offset to write to
740 * @data: data to write at register offset
742 * Write the data to PHY register at the offset using the kumeran interface.
743 * Assumes semaphore already acquired.
746 e1000_write_kmrn_reg_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
748 return (__e1000_write_kmrn_reg(hw
, offset
, data
, true));
752 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
753 * @hw: pointer to the HW structure
755 * Sets up Carrier-sense on Transmit and downshift values.
758 e1000_copper_link_setup_82577(struct e1000_hw
*hw
)
760 struct e1000_phy_info
*phy
= &hw
->phy
;
764 DEBUGFUNC("e1000_copper_link_setup_82577");
766 if (phy
->reset_disable
) {
767 ret_val
= E1000_SUCCESS
;
771 /* Enable CRS on TX. This must be set for half-duplex operation. */
772 ret_val
= phy
->ops
.read_reg(hw
, I82577_CFG_REG
, &phy_data
);
776 phy_data
|= I82577_CFG_ASSERT_CRS_ON_TX
;
778 /* Enable downshift */
779 phy_data
|= I82577_CFG_ENABLE_DOWNSHIFT
;
781 ret_val
= phy
->ops
.write_reg(hw
, I82577_CFG_REG
, phy_data
);
785 /* Set number of link attempts before downshift */
786 ret_val
= phy
->ops
.read_reg(hw
, I82577_CTRL_REG
, &phy_data
);
789 phy_data
&= ~I82577_CTRL_DOWNSHIFT_MASK
;
790 ret_val
= phy
->ops
.write_reg(hw
, I82577_CTRL_REG
, phy_data
);
797 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
798 * @hw: pointer to the HW structure
800 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
801 * and downshift values are set also.
804 e1000_copper_link_setup_m88(struct e1000_hw
*hw
)
806 struct e1000_phy_info
*phy
= &hw
->phy
;
810 DEBUGFUNC("e1000_copper_link_setup_m88");
812 if (phy
->reset_disable
) {
813 ret_val
= E1000_SUCCESS
;
817 /* Enable CRS on TX. This must be set for half-duplex operation. */
818 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
822 /* For BM PHY this bit is downshift enable */
823 if (phy
->type
!= e1000_phy_bm
)
824 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
828 * MDI/MDI-X = 0 (default)
829 * 0 - Auto for all speeds
832 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
834 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
838 phy_data
|= M88E1000_PSCR_MDI_MANUAL_MODE
;
841 phy_data
|= M88E1000_PSCR_MDIX_MANUAL_MODE
;
844 phy_data
|= M88E1000_PSCR_AUTO_X_1000T
;
848 phy_data
|= M88E1000_PSCR_AUTO_X_MODE
;
854 * disable_polarity_correction = 0 (default)
855 * Automatic Correction for Reversed Cable Polarity
859 phy_data
&= ~M88E1000_PSCR_POLARITY_REVERSAL
;
860 if (phy
->disable_polarity_correction
== 1)
861 phy_data
|= M88E1000_PSCR_POLARITY_REVERSAL
;
863 /* Enable downshift on BM (disabled by default) */
864 if (phy
->type
== e1000_phy_bm
)
865 phy_data
|= BME1000_PSCR_ENABLE_DOWNSHIFT
;
867 ret_val
= phy
->ops
.write_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
871 if ((phy
->type
== e1000_phy_m88
) &&
872 (phy
->revision
< E1000_REVISION_4
) &&
873 (phy
->id
!= BME1000_E_PHY_ID_R2
)) {
875 * Force TX_CLK in the Extended PHY Specific Control Register
878 ret_val
= phy
->ops
.read_reg(hw
,
879 M88E1000_EXT_PHY_SPEC_CTRL
,
884 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
886 if ((phy
->revision
== E1000_REVISION_2
) &&
887 (phy
->id
== M88E1111_I_PHY_ID
)) {
888 /* 82573L PHY - set the downshift counter to 5x. */
889 phy_data
&= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK
;
890 phy_data
|= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X
;
892 /* Configure Master and Slave downshift values */
893 phy_data
&= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
|
894 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK
);
895 phy_data
|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
|
896 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X
);
898 ret_val
= phy
->ops
.write_reg(hw
,
899 M88E1000_EXT_PHY_SPEC_CTRL
,
905 if ((phy
->type
== e1000_phy_bm
) && (phy
->id
== BME1000_E_PHY_ID_R2
)) {
906 /* Set PHY page 0, register 29 to 0x0003 */
907 ret_val
= phy
->ops
.write_reg(hw
, 29, 0x0003);
911 /* Set PHY page 0, register 30 to 0x0000 */
912 ret_val
= phy
->ops
.write_reg(hw
, 30, 0x0000);
917 /* Commit the changes. */
918 ret_val
= phy
->ops
.commit(hw
);
920 DEBUGOUT("Error committing the PHY changes\n");
924 if (phy
->type
== e1000_phy_82578
) {
925 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
,
930 /* 82578 PHY - set the downshift count to 1x. */
931 phy_data
|= I82578_EPSCR_DOWNSHIFT_ENABLE
;
932 phy_data
&= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK
;
933 ret_val
= phy
->ops
.write_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
,
944 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
945 * @hw: pointer to the HW structure
947 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
951 e1000_copper_link_setup_igp(struct e1000_hw
*hw
)
953 struct e1000_phy_info
*phy
= &hw
->phy
;
957 DEBUGFUNC("e1000_copper_link_setup_igp");
959 if (phy
->reset_disable
) {
960 ret_val
= E1000_SUCCESS
;
964 ret_val
= hw
->phy
.ops
.reset(hw
);
966 DEBUGOUT("Error resetting the PHY.\n");
971 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
972 * timeout issues when LFS is enabled.
977 * The NVM settings will configure LPLU in D3 for non-IGP1 PHYs.
979 if (phy
->type
== e1000_phy_igp
) {
980 /* disable lplu d3 during driver init */
981 ret_val
= hw
->phy
.ops
.set_d3_lplu_state(hw
, false);
983 DEBUGOUT("Error Disabling LPLU D3\n");
988 /* disable lplu d0 during driver init */
989 if (hw
->phy
.ops
.set_d0_lplu_state
) {
990 ret_val
= hw
->phy
.ops
.set_d0_lplu_state(hw
, false);
992 DEBUGOUT("Error Disabling LPLU D0\n");
996 /* Configure mdi-mdix settings */
997 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, &data
);
1001 data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1003 switch (phy
->mdix
) {
1005 data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1008 data
|= IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1012 data
|= IGP01E1000_PSCR_AUTO_MDIX
;
1015 ret_val
= phy
->ops
.write_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, data
);
1019 /* set auto-master slave resolution settings */
1020 if (hw
->mac
.autoneg
) {
1022 * when autonegotiation advertisement is only 1000Mbps then we
1023 * should disable SmartSpeed and enable Auto MasterSlave
1024 * resolution as hardware default.
1026 if (phy
->autoneg_advertised
== ADVERTISE_1000_FULL
) {
1027 /* Disable SmartSpeed */
1028 ret_val
= phy
->ops
.read_reg(hw
,
1029 IGP01E1000_PHY_PORT_CONFIG
,
1034 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1035 ret_val
= phy
->ops
.write_reg(hw
,
1036 IGP01E1000_PHY_PORT_CONFIG
,
1041 /* Set auto Master/Slave resolution process */
1042 ret_val
= phy
->ops
.read_reg(hw
, PHY_1000T_CTRL
, &data
);
1046 data
&= ~CR_1000T_MS_ENABLE
;
1047 ret_val
= phy
->ops
.write_reg(hw
, PHY_1000T_CTRL
, data
);
1052 ret_val
= phy
->ops
.read_reg(hw
, PHY_1000T_CTRL
, &data
);
1056 /* load defaults for future use */
1057 phy
->original_ms_type
= (data
& CR_1000T_MS_ENABLE
) ?
1058 ((data
& CR_1000T_MS_VALUE
) ?
1059 e1000_ms_force_master
:
1060 e1000_ms_force_slave
) :
1063 switch (phy
->ms_type
) {
1064 case e1000_ms_force_master
:
1065 data
|= (CR_1000T_MS_ENABLE
| CR_1000T_MS_VALUE
);
1067 case e1000_ms_force_slave
:
1068 data
|= CR_1000T_MS_ENABLE
;
1069 data
&= ~(CR_1000T_MS_VALUE
);
1072 data
&= ~CR_1000T_MS_ENABLE
;
1076 ret_val
= phy
->ops
.write_reg(hw
, PHY_1000T_CTRL
, data
);
1086 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1087 * @hw: pointer to the HW structure
1089 * Performs initial bounds checking on autoneg advertisement parameter, then
1090 * configure to advertise the full capability. Setup the PHY to autoneg
1091 * and restart the negotiation process between the link partner. If
1092 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1095 e1000_copper_link_autoneg(struct e1000_hw
*hw
)
1097 struct e1000_phy_info
*phy
= &hw
->phy
;
1101 DEBUGFUNC("e1000_copper_link_autoneg");
1104 * Perform some bounds checking on the autoneg advertisement
1107 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
1110 * If autoneg_advertised is zero, we assume it was not defaulted by
1111 * the calling code so we set to advertise full capability.
1113 if (phy
->autoneg_advertised
== 0)
1114 phy
->autoneg_advertised
= phy
->autoneg_mask
;
1116 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1117 ret_val
= e1000_phy_setup_autoneg(hw
);
1119 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1122 DEBUGOUT("Restarting Auto-Neg\n");
1125 * Restart auto-negotiation by setting the Auto Neg Enable bit and the
1126 * Auto Neg Restart bit in the PHY control register.
1128 ret_val
= phy
->ops
.read_reg(hw
, PHY_CONTROL
, &phy_ctrl
);
1132 phy_ctrl
|= (MII_CR_AUTO_NEG_EN
| MII_CR_RESTART_AUTO_NEG
);
1133 ret_val
= phy
->ops
.write_reg(hw
, PHY_CONTROL
, phy_ctrl
);
1138 * Does the user want to wait for Auto-Neg to complete here, or check
1139 * at a later time (for example, callback routine).
1141 if (phy
->autoneg_wait_to_complete
) {
1142 ret_val
= hw
->mac
.ops
.wait_autoneg(hw
);
1144 DEBUGOUT("Error while waiting for "
1145 "autoneg to complete\n");
1150 hw
->mac
.get_link_status
= true;
1157 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1158 * @hw: pointer to the HW structure
1160 * Reads the MII auto-neg advertisement register and/or the 1000T control
1161 * register and if the PHY is already setup for auto-negotiation, then
1162 * return successful. Otherwise, setup advertisement and flow control to
1163 * the appropriate values for the wanted auto-negotiation.
1166 e1000_phy_setup_autoneg(struct e1000_hw
*hw
)
1168 struct e1000_phy_info
*phy
= &hw
->phy
;
1170 u16 mii_autoneg_adv_reg
;
1171 u16 mii_1000t_ctrl_reg
= 0;
1173 DEBUGFUNC("e1000_phy_setup_autoneg");
1175 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
1177 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1178 ret_val
= phy
->ops
.read_reg(hw
, PHY_AUTONEG_ADV
, &mii_autoneg_adv_reg
);
1182 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
1183 /* Read the MII 1000Base-T Control Register (Address 9). */
1184 ret_val
= phy
->ops
.read_reg(hw
,
1186 &mii_1000t_ctrl_reg
);
1192 * Need to parse both autoneg_advertised and fc and set up the
1193 * appropriate PHY registers. First we will parse for
1194 * autoneg_advertised software override. Since we can advertise a
1195 * plethora of combinations, we need to check each bit individually.
1199 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1200 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1201 * the 1000Base-T Control Register (Address 9).
1203 mii_autoneg_adv_reg
&= ~(NWAY_AR_100TX_FD_CAPS
|
1204 NWAY_AR_100TX_HD_CAPS
|
1205 NWAY_AR_10T_FD_CAPS
|
1206 NWAY_AR_10T_HD_CAPS
);
1207 mii_1000t_ctrl_reg
&= ~(CR_1000T_HD_CAPS
| CR_1000T_FD_CAPS
);
1209 DEBUGOUT1("autoneg_advertised %x\n", phy
->autoneg_advertised
);
1211 /* Do we want to advertise 10 Mb Half Duplex? */
1212 if (phy
->autoneg_advertised
& ADVERTISE_10_HALF
) {
1213 DEBUGOUT("Advertise 10mb Half duplex\n");
1214 mii_autoneg_adv_reg
|= NWAY_AR_10T_HD_CAPS
;
1217 /* Do we want to advertise 10 Mb Full Duplex? */
1218 if (phy
->autoneg_advertised
& ADVERTISE_10_FULL
) {
1219 DEBUGOUT("Advertise 10mb Full duplex\n");
1220 mii_autoneg_adv_reg
|= NWAY_AR_10T_FD_CAPS
;
1223 /* Do we want to advertise 100 Mb Half Duplex? */
1224 if (phy
->autoneg_advertised
& ADVERTISE_100_HALF
) {
1225 DEBUGOUT("Advertise 100mb Half duplex\n");
1226 mii_autoneg_adv_reg
|= NWAY_AR_100TX_HD_CAPS
;
1229 /* Do we want to advertise 100 Mb Full Duplex? */
1230 if (phy
->autoneg_advertised
& ADVERTISE_100_FULL
) {
1231 DEBUGOUT("Advertise 100mb Full duplex\n");
1232 mii_autoneg_adv_reg
|= NWAY_AR_100TX_FD_CAPS
;
1235 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1236 if (phy
->autoneg_advertised
& ADVERTISE_1000_HALF
) {
1238 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1241 /* Do we want to advertise 1000 Mb Full Duplex? */
1242 if (phy
->autoneg_advertised
& ADVERTISE_1000_FULL
) {
1243 DEBUGOUT("Advertise 1000mb Full duplex\n");
1244 mii_1000t_ctrl_reg
|= CR_1000T_FD_CAPS
;
1248 * Check for a software override of the flow control settings, and
1249 * setup the PHY advertisement registers accordingly. If
1250 * auto-negotiation is enabled, then software will have to set the
1251 * "PAUSE" bits to the correct value in the Auto-Negotiation
1252 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1255 * The possible values of the "fc" parameter are:
1256 * 0: Flow control is completely disabled
1257 * 1: Rx flow control is enabled (we can receive pause frames
1258 * but not send pause frames).
1259 * 2: Tx flow control is enabled (we can send pause frames
1260 * but we do not support receiving pause frames).
1261 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1262 * other: No software override. The flow control configuration
1263 * in the EEPROM is used.
1265 switch (hw
->fc
.current_mode
) {
1268 * Flow control (Rx & Tx) is completely disabled by a software
1271 mii_autoneg_adv_reg
&= ~(NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1273 case e1000_fc_rx_pause
:
1275 * Rx Flow control is enabled, and Tx Flow control is
1276 * disabled, by a software over-ride.
1278 * Since there really isn't a way to advertise that we are
1279 * capable of Rx Pause ONLY, we will advertise that we support
1280 * both symmetric and asymmetric Rx PAUSE. Later (in
1281 * e1000_config_fc_after_link_up) we will disable the hw's
1282 * ability to send PAUSE frames.
1284 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1286 case e1000_fc_tx_pause
:
1288 * Tx Flow control is enabled, and Rx Flow control is
1289 * disabled, by a software over-ride.
1291 mii_autoneg_adv_reg
|= NWAY_AR_ASM_DIR
;
1292 mii_autoneg_adv_reg
&= ~NWAY_AR_PAUSE
;
1296 * Flow control (both Rx and Tx) is enabled by a software
1299 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1302 DEBUGOUT("Flow control param set incorrectly\n");
1303 ret_val
= -E1000_ERR_CONFIG
;
1307 ret_val
= phy
->ops
.write_reg(hw
, PHY_AUTONEG_ADV
, mii_autoneg_adv_reg
);
1311 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
);
1313 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
1314 ret_val
= phy
->ops
.write_reg(hw
,
1316 mii_1000t_ctrl_reg
);
1326 * e1000_setup_copper_link_generic - Configure copper link settings
1327 * @hw: pointer to the HW structure
1329 * Calls the appropriate function to configure the link for auto-neg or forced
1330 * speed and duplex. Then we check for link, once link is established calls
1331 * to configure collision distance and flow control are called. If link is
1332 * not established, we return -E1000_ERR_PHY (-2).
1335 e1000_setup_copper_link_generic(struct e1000_hw
*hw
)
1340 DEBUGFUNC("e1000_setup_copper_link_generic");
1342 if (hw
->mac
.autoneg
) {
1344 * Setup autoneg and flow control advertisement and perform
1347 ret_val
= e1000_copper_link_autoneg(hw
);
1352 * PHY will be set to 10H, 10F, 100H or 100F depending on user
1355 DEBUGOUT("Forcing Speed and Duplex\n");
1356 ret_val
= hw
->phy
.ops
.force_speed_duplex(hw
);
1358 DEBUGOUT("Error Forcing Speed and Duplex\n");
1364 * Check link status. Wait up to 100 microseconds for link to become
1367 ret_val
= e1000_phy_has_link_generic(hw
,
1368 COPPER_LINK_UP_LIMIT
,
1375 DEBUGOUT("Valid link established!!!\n");
1376 e1000_config_collision_dist_generic(hw
);
1377 ret_val
= e1000_config_fc_after_link_up_generic(hw
);
1380 DEBUGOUT("Unable to establish link!!!\n");
1388 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1389 * @hw: pointer to the HW structure
1391 * Calls the PHY setup function to force speed and duplex. Clears the
1392 * auto-crossover to force MDI manually. Waits for link and returns
1393 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1396 e1000_phy_force_speed_duplex_igp(struct e1000_hw
*hw
)
1398 struct e1000_phy_info
*phy
= &hw
->phy
;
1403 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1405 ret_val
= phy
->ops
.read_reg(hw
, PHY_CONTROL
, &phy_data
);
1409 e1000_phy_force_speed_duplex_setup(hw
, &phy_data
);
1411 ret_val
= phy
->ops
.write_reg(hw
, PHY_CONTROL
, phy_data
);
1416 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1417 * forced whenever speed and duplex are forced.
1419 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1423 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1424 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1426 ret_val
= phy
->ops
.write_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1430 DEBUGOUT1("IGP PSCR: %X\n", phy_data
);
1434 if (phy
->autoneg_wait_to_complete
) {
1435 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1437 ret_val
= e1000_phy_has_link_generic(hw
,
1446 DEBUGOUT("Link taking longer than expected.\n");
1450 ret_val
= e1000_phy_has_link_generic(hw
,
1463 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1464 * @hw: pointer to the HW structure
1466 * Calls the PHY setup function to force speed and duplex. Clears the
1467 * auto-crossover to force MDI manually. Resets the PHY to commit the
1468 * changes. If time expires while waiting for link up, we reset the DSP.
1469 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1470 * successful completion, else return corresponding error code.
1473 e1000_phy_force_speed_duplex_m88(struct e1000_hw
*hw
)
1475 struct e1000_phy_info
*phy
= &hw
->phy
;
1480 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1483 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1484 * forced whenever speed and duplex are forced.
1486 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1490 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1491 ret_val
= phy
->ops
.write_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1495 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data
);
1497 ret_val
= phy
->ops
.read_reg(hw
, PHY_CONTROL
, &phy_data
);
1501 e1000_phy_force_speed_duplex_setup(hw
, &phy_data
);
1503 ret_val
= phy
->ops
.write_reg(hw
, PHY_CONTROL
, phy_data
);
1507 /* Reset the phy to commit changes. */
1508 ret_val
= hw
->phy
.ops
.commit(hw
);
1512 if (phy
->autoneg_wait_to_complete
) {
1513 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1515 ret_val
= e1000_phy_has_link_generic(hw
,
1524 * We didn't get link. Reset the DSP and cross our
1527 ret_val
= phy
->ops
.write_reg(hw
,
1528 M88E1000_PHY_PAGE_SELECT
,
1532 ret_val
= e1000_phy_reset_dsp_generic(hw
);
1537 ret_val
= e1000_phy_has_link_generic(hw
,
1544 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1549 * Resetting the phy means we need to re-force TX_CLK in the Extended
1550 * PHY Specific Control Register to 25MHz clock from the reset value
1553 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1554 ret_val
= phy
->ops
.write_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1559 * In addition, we must re-enable CRS on Tx for both half and full
1562 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1566 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1567 ret_val
= phy
->ops
.write_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1574 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1575 * @hw: pointer to the HW structure
1577 * Forces the speed and duplex settings of the PHY.
1578 * This is a function pointer entry point only called by
1579 * PHY setup routines.
1582 e1000_phy_force_speed_duplex_ife(struct e1000_hw
*hw
)
1584 struct e1000_phy_info
*phy
= &hw
->phy
;
1589 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1591 if (phy
->type
!= e1000_phy_ife
) {
1592 ret_val
= e1000_phy_force_speed_duplex_igp(hw
);
1596 ret_val
= phy
->ops
.read_reg(hw
, PHY_CONTROL
, &data
);
1600 e1000_phy_force_speed_duplex_setup(hw
, &data
);
1602 ret_val
= phy
->ops
.write_reg(hw
, PHY_CONTROL
, data
);
1606 /* Disable MDI-X support for 10/100 */
1607 ret_val
= phy
->ops
.read_reg(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
1611 data
&= ~IFE_PMC_AUTO_MDIX
;
1612 data
&= ~IFE_PMC_FORCE_MDIX
;
1614 ret_val
= phy
->ops
.write_reg(hw
, IFE_PHY_MDIX_CONTROL
, data
);
1618 DEBUGOUT1("IFE PMC: %X\n", data
);
1622 if (phy
->autoneg_wait_to_complete
) {
1623 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1625 ret_val
= e1000_phy_has_link_generic(hw
,
1626 PHY_FORCE_LIMIT
, 100000, &link
);
1632 DEBUGOUT("Link taking longer than expected.\n");
1636 ret_val
= e1000_phy_has_link_generic(hw
,
1637 PHY_FORCE_LIMIT
, 100000, &link
);
1647 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1648 * @hw: pointer to the HW structure
1649 * @phy_ctrl: pointer to current value of PHY_CONTROL
1651 * Forces speed and duplex on the PHY by doing the following: disable flow
1652 * control, force speed/duplex on the MAC, disable auto speed detection,
1653 * disable auto-negotiation, configure duplex, configure speed, configure
1654 * the collision distance, write configuration to CTRL register. The
1655 * caller must write to the PHY_CONTROL register for these settings to
1659 e1000_phy_force_speed_duplex_setup(struct e1000_hw
*hw
, u16
*phy_ctrl
)
1661 struct e1000_mac_info
*mac
= &hw
->mac
;
1664 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1666 /* Turn off flow control when forcing speed/duplex */
1667 hw
->fc
.current_mode
= e1000_fc_none
;
1669 /* Force speed/duplex on the mac */
1670 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
1671 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1672 ctrl
&= ~E1000_CTRL_SPD_SEL
;
1674 /* Disable Auto Speed Detection */
1675 ctrl
&= ~E1000_CTRL_ASDE
;
1677 /* Disable autoneg on the phy */
1678 *phy_ctrl
&= ~MII_CR_AUTO_NEG_EN
;
1680 /* Forcing Full or Half Duplex? */
1681 if (mac
->forced_speed_duplex
& E1000_ALL_HALF_DUPLEX
) {
1682 ctrl
&= ~E1000_CTRL_FD
;
1683 *phy_ctrl
&= ~MII_CR_FULL_DUPLEX
;
1684 DEBUGOUT("Half Duplex\n");
1686 ctrl
|= E1000_CTRL_FD
;
1687 *phy_ctrl
|= MII_CR_FULL_DUPLEX
;
1688 DEBUGOUT("Full Duplex\n");
1691 /* Forcing 10mb or 100mb? */
1692 if (mac
->forced_speed_duplex
& E1000_ALL_100_SPEED
) {
1693 ctrl
|= E1000_CTRL_SPD_100
;
1694 *phy_ctrl
|= MII_CR_SPEED_100
;
1695 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_10
);
1696 DEBUGOUT("Forcing 100mb\n");
1698 ctrl
&= ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1700 *phy_ctrl
|= MII_CR_SPEED_10
;
1701 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_100
);
1702 DEBUGOUT("Forcing 10mb\n");
1705 e1000_config_collision_dist_generic(hw
);
1707 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
);
1711 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1712 * @hw: pointer to the HW structure
1713 * @active: boolean used to enable/disable lplu
1715 * Success returns 0, Failure returns 1
1717 * The low power link up (lplu) state is set to the power management level D3
1718 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1719 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1720 * is used during Dx states where the power conservation is most important.
1721 * During driver activity, SmartSpeed should be enabled so performance is
1725 e1000_set_d3_lplu_state_generic(struct e1000_hw
*hw
, bool active
)
1727 struct e1000_phy_info
*phy
= &hw
->phy
;
1728 s32 ret_val
= E1000_SUCCESS
;
1731 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1733 if (!(hw
->phy
.ops
.read_reg
))
1736 ret_val
= phy
->ops
.read_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
1741 data
&= ~IGP02E1000_PM_D3_LPLU
;
1742 ret_val
= phy
->ops
.write_reg(hw
,
1743 IGP02E1000_PHY_POWER_MGMT
,
1748 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1749 * during Dx states where the power conservation is most
1750 * important. During driver activity we should enable
1751 * SmartSpeed, so performance is maintained.
1753 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1754 ret_val
= phy
->ops
.read_reg(hw
,
1755 IGP01E1000_PHY_PORT_CONFIG
,
1760 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1761 ret_val
= phy
->ops
.write_reg(hw
,
1762 IGP01E1000_PHY_PORT_CONFIG
,
1766 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1767 ret_val
= phy
->ops
.read_reg(hw
,
1768 IGP01E1000_PHY_PORT_CONFIG
,
1773 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1774 ret_val
= phy
->ops
.write_reg(hw
,
1775 IGP01E1000_PHY_PORT_CONFIG
,
1780 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1781 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1782 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1783 data
|= IGP02E1000_PM_D3_LPLU
;
1784 ret_val
= phy
->ops
.write_reg(hw
,
1785 IGP02E1000_PHY_POWER_MGMT
,
1790 /* When LPLU is enabled, we should disable SmartSpeed */
1791 ret_val
= phy
->ops
.read_reg(hw
,
1792 IGP01E1000_PHY_PORT_CONFIG
,
1797 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1798 ret_val
= phy
->ops
.write_reg(hw
,
1799 IGP01E1000_PHY_PORT_CONFIG
,
1808 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
1809 * @hw: pointer to the HW structure
1811 * Success returns 0, Failure returns 1
1813 * A downshift is detected by querying the PHY link health.
1816 e1000_check_downshift_generic(struct e1000_hw
*hw
)
1818 struct e1000_phy_info
*phy
= &hw
->phy
;
1820 u16 phy_data
, offset
, mask
;
1822 DEBUGFUNC("e1000_check_downshift_generic");
1824 switch (phy
->type
) {
1826 case e1000_phy_gg82563
:
1828 case e1000_phy_82578
:
1829 offset
= M88E1000_PHY_SPEC_STATUS
;
1830 mask
= M88E1000_PSSR_DOWNSHIFT
;
1832 case e1000_phy_igp_2
:
1834 case e1000_phy_igp_3
:
1835 offset
= IGP01E1000_PHY_LINK_HEALTH
;
1836 mask
= IGP01E1000_PLHR_SS_DOWNGRADE
;
1839 /* speed downshift not supported */
1840 phy
->speed_downgraded
= false;
1841 ret_val
= E1000_SUCCESS
;
1845 ret_val
= phy
->ops
.read_reg(hw
, offset
, &phy_data
);
1848 phy
->speed_downgraded
= (phy_data
& mask
) ? true : false;
1855 * e1000_check_polarity_m88 - Checks the polarity.
1856 * @hw: pointer to the HW structure
1858 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1860 * Polarity is determined based on the PHY specific status register.
1863 e1000_check_polarity_m88(struct e1000_hw
*hw
)
1865 struct e1000_phy_info
*phy
= &hw
->phy
;
1869 DEBUGFUNC("e1000_check_polarity_m88");
1871 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &data
);
1874 phy
->cable_polarity
= (data
& M88E1000_PSSR_REV_POLARITY
)
1875 ? e1000_rev_polarity_reversed
1876 : e1000_rev_polarity_normal
;
1882 * e1000_check_polarity_igp - Checks the polarity.
1883 * @hw: pointer to the HW structure
1885 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1887 * Polarity is determined based on the PHY port status register, and the
1888 * current speed (since there is no polarity at 100Mbps).
1891 e1000_check_polarity_igp(struct e1000_hw
*hw
)
1893 struct e1000_phy_info
*phy
= &hw
->phy
;
1895 u16 data
, offset
, mask
;
1897 DEBUGFUNC("e1000_check_polarity_igp");
1900 * Polarity is determined based on the speed of our connection.
1902 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
1906 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1907 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1908 offset
= IGP01E1000_PHY_PCS_INIT_REG
;
1909 mask
= IGP01E1000_PHY_POLARITY_MASK
;
1912 * This really only applies to 10Mbps since there is no
1913 * polarity for 100Mbps (always 0).
1915 offset
= IGP01E1000_PHY_PORT_STATUS
;
1916 mask
= IGP01E1000_PSSR_POLARITY_REVERSED
;
1919 ret_val
= phy
->ops
.read_reg(hw
, offset
, &data
);
1922 phy
->cable_polarity
= (data
& mask
)
1923 ? e1000_rev_polarity_reversed
1924 : e1000_rev_polarity_normal
;
1931 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1932 * @hw: pointer to the HW structure
1934 * Polarity is determined on the polarity reversal feature being enabled.
1937 e1000_check_polarity_ife(struct e1000_hw
*hw
)
1939 struct e1000_phy_info
*phy
= &hw
->phy
;
1941 u16 phy_data
, offset
, mask
;
1943 DEBUGFUNC("e1000_check_polarity_ife");
1946 * Polarity is determined based on the reversal feature being enabled.
1948 if (phy
->polarity_correction
) {
1949 offset
= IFE_PHY_EXTENDED_STATUS_CONTROL
;
1950 mask
= IFE_PESC_POLARITY_REVERSED
;
1952 offset
= IFE_PHY_SPECIAL_CONTROL
;
1953 mask
= IFE_PSC_FORCE_POLARITY
;
1956 ret_val
= phy
->ops
.read_reg(hw
, offset
, &phy_data
);
1959 phy
->cable_polarity
= (phy_data
& mask
)
1960 ? e1000_rev_polarity_reversed
: e1000_rev_polarity_normal
;
1966 * e1000_wait_autoneg_generic - Wait for auto-neg completion
1967 * @hw: pointer to the HW structure
1969 * Waits for auto-negotiation to complete or for the auto-negotiation time
1970 * limit to expire, which ever happens first.
1973 e1000_wait_autoneg_generic(struct e1000_hw
*hw
)
1975 s32 ret_val
= E1000_SUCCESS
;
1978 DEBUGFUNC("e1000_wait_autoneg_generic");
1980 if (!(hw
->phy
.ops
.read_reg
))
1981 return (E1000_SUCCESS
);
1983 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1984 for (i
= PHY_AUTO_NEG_LIMIT
; i
> 0; i
--) {
1985 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
, &phy_status
);
1988 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
, &phy_status
);
1991 if (phy_status
& MII_SR_AUTONEG_COMPLETE
)
1997 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation has
2004 * e1000_phy_has_link_generic - Polls PHY for link
2005 * @hw: pointer to the HW structure
2006 * @iterations: number of times to poll for link
2007 * @usec_interval: delay between polling attempts
2008 * @success: pointer to whether polling was successful or not
2010 * Polls the PHY status register for link, 'iterations' number of times.
2013 e1000_phy_has_link_generic(struct e1000_hw
*hw
, u32 iterations
,
2014 u32 usec_interval
, bool *success
)
2016 s32 ret_val
= E1000_SUCCESS
;
2019 DEBUGFUNC("e1000_phy_has_link_generic");
2021 if (!(hw
->phy
.ops
.read_reg
))
2022 return (E1000_SUCCESS
);
2024 for (i
= 0; i
< iterations
; i
++) {
2026 * Some PHYs require the PHY_STATUS register to be read twice
2027 * due to the link bit being sticky. No harm doing it across
2030 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
, &phy_status
);
2033 * If the first read fails, another entity may have
2034 * ownership of the resources, wait and try again to
2035 * see if they have relinquished the resources yet.
2037 usec_delay(usec_interval
);
2039 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
, &phy_status
);
2042 if (phy_status
& MII_SR_LINK_STATUS
)
2044 if (usec_interval
>= 1000)
2045 msec_delay_irq(usec_interval
/ 1000);
2047 usec_delay(usec_interval
);
2050 *success
= (i
< iterations
) ? true : false;
2056 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2057 * @hw: pointer to the HW structure
2059 * Reads the PHY specific status register to retrieve the cable length
2060 * information. The cable length is determined by averaging the minimum and
2061 * maximum values to get the "average" cable length. The m88 PHY has four
2062 * possible cable length values, which are:
2063 * Register Value Cable Length
2067 * 3 110 - 140 meters
2071 e1000_get_cable_length_m88(struct e1000_hw
*hw
)
2073 struct e1000_phy_info
*phy
= &hw
->phy
;
2075 u16 phy_data
, index
;
2077 DEBUGFUNC("e1000_get_cable_length_m88");
2079 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
2083 index
= (phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
2084 M88E1000_PSSR_CABLE_LENGTH_SHIFT
;
2086 if (index
>= M88E1000_CABLE_LENGTH_TABLE_SIZE
- 1) {
2087 ret_val
= E1000_ERR_PHY
;
2090 phy
->min_cable_length
= e1000_m88_cable_length_table
[index
];
2091 phy
->max_cable_length
= e1000_m88_cable_length_table
[index
+ 1];
2093 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
2100 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2101 * @hw: pointer to the HW structure
2103 * The automatic gain control (agc) normalizes the amplitude of the
2104 * received signal, adjusting for the attenuation produced by the
2105 * cable. By reading the AGC registers, which represent the
2106 * combination of coarse and fine gain value, the value can be put
2107 * into a lookup table to obtain the approximate cable length
2111 e1000_get_cable_length_igp_2(struct e1000_hw
*hw
)
2113 struct e1000_phy_info
*phy
= &hw
->phy
;
2114 s32 ret_val
= E1000_SUCCESS
;
2115 u16 phy_data
, i
, agc_value
= 0;
2116 u16 cur_agc_index
, max_agc_index
= 0;
2117 u16 min_agc_index
= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
- 1;
2118 u16 agc_reg_array
[IGP02E1000_PHY_CHANNEL_NUM
] =
2119 {IGP02E1000_PHY_AGC_A
,
2120 IGP02E1000_PHY_AGC_B
,
2121 IGP02E1000_PHY_AGC_C
,
2122 IGP02E1000_PHY_AGC_D
};
2124 DEBUGFUNC("e1000_get_cable_length_igp_2");
2126 /* Read the AGC registers for all channels */
2127 for (i
= 0; i
< IGP02E1000_PHY_CHANNEL_NUM
; i
++) {
2128 ret_val
= phy
->ops
.read_reg(hw
, agc_reg_array
[i
], &phy_data
);
2133 * Getting bits 15:9, which represent the combination of
2134 * coarse and fine gain values. The result is a number that
2135 * can be put into the lookup table to obtain the approximate
2138 cur_agc_index
= (phy_data
>> IGP02E1000_AGC_LENGTH_SHIFT
) &
2139 IGP02E1000_AGC_LENGTH_MASK
;
2141 /* Array index bound check. */
2142 if ((cur_agc_index
>= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
) ||
2143 (cur_agc_index
== 0)) {
2144 ret_val
= -E1000_ERR_PHY
;
2148 /* Remove min & max AGC values from calculation. */
2149 if (e1000_igp_2_cable_length_table
[min_agc_index
] >
2150 e1000_igp_2_cable_length_table
[cur_agc_index
])
2151 min_agc_index
= cur_agc_index
;
2152 if (e1000_igp_2_cable_length_table
[max_agc_index
] <
2153 e1000_igp_2_cable_length_table
[cur_agc_index
])
2154 max_agc_index
= cur_agc_index
;
2156 agc_value
+= e1000_igp_2_cable_length_table
[cur_agc_index
];
2159 agc_value
-= (e1000_igp_2_cable_length_table
[min_agc_index
] +
2160 e1000_igp_2_cable_length_table
[max_agc_index
]);
2161 agc_value
/= (IGP02E1000_PHY_CHANNEL_NUM
- 2);
2163 /* Calculate cable length with the error range of +/- 10 meters. */
2164 phy
->min_cable_length
= ((agc_value
- IGP02E1000_AGC_RANGE
) > 0) ?
2165 (agc_value
- IGP02E1000_AGC_RANGE
) : 0;
2166 phy
->max_cable_length
= agc_value
+ IGP02E1000_AGC_RANGE
;
2168 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
2175 * e1000_get_phy_info_m88 - Retrieve PHY information
2176 * @hw: pointer to the HW structure
2178 * Valid for only copper links. Read the PHY status register (sticky read)
2179 * to verify that link is up. Read the PHY special control register to
2180 * determine the polarity and 10base-T extended distance. Read the PHY
2181 * special status register to determine MDI/MDIx and current speed. If
2182 * speed is 1000, then determine cable length, local and remote receiver.
2185 e1000_get_phy_info_m88(struct e1000_hw
*hw
)
2187 struct e1000_phy_info
*phy
= &hw
->phy
;
2192 DEBUGFUNC("e1000_get_phy_info_m88");
2194 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
2195 DEBUGOUT("Phy info is only valid for copper media\n");
2196 ret_val
= -E1000_ERR_CONFIG
;
2200 ret_val
= e1000_phy_has_link_generic(hw
, 1, 0, &link
);
2205 DEBUGOUT("Phy info is only valid if link is up\n");
2206 ret_val
= -E1000_ERR_CONFIG
;
2210 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
2214 phy
->polarity_correction
= (phy_data
& M88E1000_PSCR_POLARITY_REVERSAL
)
2218 ret_val
= e1000_check_polarity_m88(hw
);
2222 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
2226 phy
->is_mdix
= (phy_data
& M88E1000_PSSR_MDIX
) ? true : false;
2228 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
) {
2229 ret_val
= hw
->phy
.ops
.get_cable_length(hw
);
2233 ret_val
= phy
->ops
.read_reg(hw
, PHY_1000T_STATUS
, &phy_data
);
2237 phy
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
)
2238 ? e1000_1000t_rx_status_ok
2239 : e1000_1000t_rx_status_not_ok
;
2241 phy
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
)
2242 ? e1000_1000t_rx_status_ok
2243 : e1000_1000t_rx_status_not_ok
;
2245 /* Set values to "undefined" */
2246 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
2247 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
2248 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
2256 * e1000_get_phy_info_igp - Retrieve igp PHY information
2257 * @hw: pointer to the HW structure
2259 * Read PHY status to determine if link is up. If link is up, then
2260 * set/determine 10base-T extended distance and polarity correction. Read
2261 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2262 * determine on the cable length, local and remote receiver.
2265 e1000_get_phy_info_igp(struct e1000_hw
*hw
)
2267 struct e1000_phy_info
*phy
= &hw
->phy
;
2272 DEBUGFUNC("e1000_get_phy_info_igp");
2274 ret_val
= e1000_phy_has_link_generic(hw
, 1, 0, &link
);
2279 DEBUGOUT("Phy info is only valid if link is up\n");
2280 ret_val
= -E1000_ERR_CONFIG
;
2284 phy
->polarity_correction
= true;
2286 ret_val
= e1000_check_polarity_igp(hw
);
2290 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
2294 phy
->is_mdix
= (data
& IGP01E1000_PSSR_MDIX
) ? true : false;
2296 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
2297 IGP01E1000_PSSR_SPEED_1000MBPS
) {
2298 ret_val
= hw
->phy
.ops
.get_cable_length(hw
);
2302 ret_val
= phy
->ops
.read_reg(hw
, PHY_1000T_STATUS
, &data
);
2306 phy
->local_rx
= (data
& SR_1000T_LOCAL_RX_STATUS
)
2307 ? e1000_1000t_rx_status_ok
2308 : e1000_1000t_rx_status_not_ok
;
2310 phy
->remote_rx
= (data
& SR_1000T_REMOTE_RX_STATUS
)
2311 ? e1000_1000t_rx_status_ok
2312 : e1000_1000t_rx_status_not_ok
;
2314 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
2315 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
2316 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
2324 * e1000_phy_sw_reset_generic - PHY software reset
2325 * @hw: pointer to the HW structure
2327 * Does a software reset of the PHY by reading the PHY control register and
2328 * setting/write the control register reset bit to the PHY.
2331 e1000_phy_sw_reset_generic(struct e1000_hw
*hw
)
2333 s32 ret_val
= E1000_SUCCESS
;
2336 DEBUGFUNC("e1000_phy_sw_reset_generic");
2338 if (!(hw
->phy
.ops
.read_reg
))
2341 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_CONTROL
, &phy_ctrl
);
2345 phy_ctrl
|= MII_CR_RESET
;
2346 ret_val
= hw
->phy
.ops
.write_reg(hw
, PHY_CONTROL
, phy_ctrl
);
2357 * e1000_phy_hw_reset_generic - PHY hardware reset
2358 * @hw: pointer to the HW structure
2360 * Verify the reset block is not blocking us from resetting. Acquire
2361 * semaphore (if necessary) and read/set/write the device control reset
2362 * bit in the PHY. Wait the appropriate delay time for the device to
2363 * reset and release the semaphore (if necessary).
2366 e1000_phy_hw_reset_generic(struct e1000_hw
*hw
)
2368 struct e1000_phy_info
*phy
= &hw
->phy
;
2369 s32 ret_val
= E1000_SUCCESS
;
2372 DEBUGFUNC("e1000_phy_hw_reset_generic");
2374 ret_val
= phy
->ops
.check_reset_block(hw
);
2376 ret_val
= E1000_SUCCESS
;
2380 ret_val
= phy
->ops
.acquire(hw
);
2384 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
2385 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
| E1000_CTRL_PHY_RST
);
2386 E1000_WRITE_FLUSH(hw
);
2388 usec_delay(phy
->reset_delay_us
);
2390 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
);
2391 E1000_WRITE_FLUSH(hw
);
2395 phy
->ops
.release(hw
);
2397 ret_val
= phy
->ops
.get_cfg_done(hw
);
2404 * e1000_get_cfg_done_generic - Generic configuration done
2405 * @hw: pointer to the HW structure
2407 * Generic function to wait 10 milli-seconds for configuration to complete
2408 * and return success.
2411 e1000_get_cfg_done_generic(struct e1000_hw
*hw
)
2413 DEBUGFUNC("e1000_get_cfg_done_generic");
2414 UNREFERENCED_1PARAMETER(hw
);
2418 return (E1000_SUCCESS
);
2422 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2423 * @hw: pointer to the HW structure
2425 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2428 e1000_phy_init_script_igp3(struct e1000_hw
*hw
)
2430 DEBUGOUT("Running IGP 3 PHY init script\n");
2432 /* PHY init IGP 3 */
2433 /* Enable rise/fall, 10-mode work in class-A */
2434 hw
->phy
.ops
.write_reg(hw
, 0x2F5B, 0x9018);
2435 /* Remove all caps from Replica path filter */
2436 hw
->phy
.ops
.write_reg(hw
, 0x2F52, 0x0000);
2437 /* Bias trimming for ADC, AFE and Driver (Default) */
2438 hw
->phy
.ops
.write_reg(hw
, 0x2FB1, 0x8B24);
2439 /* Increase Hybrid poly bias */
2440 hw
->phy
.ops
.write_reg(hw
, 0x2FB2, 0xF8F0);
2441 /* Add 4% to TX amplitude in Giga mode */
2442 hw
->phy
.ops
.write_reg(hw
, 0x2010, 0x10B0);
2443 /* Disable trimming (TTT) */
2444 hw
->phy
.ops
.write_reg(hw
, 0x2011, 0x0000);
2445 /* Poly DC correction to 94.6% + 2% for all channels */
2446 hw
->phy
.ops
.write_reg(hw
, 0x20DD, 0x249A);
2447 /* ABS DC correction to 95.9% */
2448 hw
->phy
.ops
.write_reg(hw
, 0x20DE, 0x00D3);
2449 /* BG temp curve trim */
2450 hw
->phy
.ops
.write_reg(hw
, 0x28B4, 0x04CE);
2451 /* Increasing ADC OPAMP stage 1 currents to max */
2452 hw
->phy
.ops
.write_reg(hw
, 0x2F70, 0x29E4);
2453 /* Force 1000 ( required for enabling PHY regs configuration) */
2454 hw
->phy
.ops
.write_reg(hw
, 0x0000, 0x0140);
2455 /* Set upd_freq to 6 */
2456 hw
->phy
.ops
.write_reg(hw
, 0x1F30, 0x1606);
2458 hw
->phy
.ops
.write_reg(hw
, 0x1F31, 0xB814);
2459 /* Disable adaptive fixed FFE (Default) */
2460 hw
->phy
.ops
.write_reg(hw
, 0x1F35, 0x002A);
2461 /* Enable FFE hysteresis */
2462 hw
->phy
.ops
.write_reg(hw
, 0x1F3E, 0x0067);
2463 /* Fixed FFE for short cable lengths */
2464 hw
->phy
.ops
.write_reg(hw
, 0x1F54, 0x0065);
2465 /* Fixed FFE for medium cable lengths */
2466 hw
->phy
.ops
.write_reg(hw
, 0x1F55, 0x002A);
2467 /* Fixed FFE for long cable lengths */
2468 hw
->phy
.ops
.write_reg(hw
, 0x1F56, 0x002A);
2469 /* Enable Adaptive Clip Threshold */
2470 hw
->phy
.ops
.write_reg(hw
, 0x1F72, 0x3FB0);
2471 /* AHT reset limit to 1 */
2472 hw
->phy
.ops
.write_reg(hw
, 0x1F76, 0xC0FF);
2473 /* Set AHT master delay to 127 msec */
2474 hw
->phy
.ops
.write_reg(hw
, 0x1F77, 0x1DEC);
2475 /* Set scan bits for AHT */
2476 hw
->phy
.ops
.write_reg(hw
, 0x1F78, 0xF9EF);
2477 /* Set AHT Preset bits */
2478 hw
->phy
.ops
.write_reg(hw
, 0x1F79, 0x0210);
2479 /* Change integ_factor of channel A to 3 */
2480 hw
->phy
.ops
.write_reg(hw
, 0x1895, 0x0003);
2481 /* Change prop_factor of channels BCD to 8 */
2482 hw
->phy
.ops
.write_reg(hw
, 0x1796, 0x0008);
2483 /* Change cg_icount + enable integbp for channels BCD */
2484 hw
->phy
.ops
.write_reg(hw
, 0x1798, 0xD008);
2486 * Change cg_icount + enable integbp + change prop_factor_master to 8
2489 hw
->phy
.ops
.write_reg(hw
, 0x1898, 0xD918);
2490 /* Disable AHT in Slave mode on channel A */
2491 hw
->phy
.ops
.write_reg(hw
, 0x187A, 0x0800);
2493 * Enable LPLU and disable AN to 1000 in non-D0a states, Enable
2496 hw
->phy
.ops
.write_reg(hw
, 0x0019, 0x008D);
2497 /* Enable restart AN on an1000_dis change */
2498 hw
->phy
.ops
.write_reg(hw
, 0x001B, 0x2080);
2499 /* Enable wh_fifo read clock in 10/100 modes */
2500 hw
->phy
.ops
.write_reg(hw
, 0x0014, 0x0045);
2501 /* Restart AN, Speed selection is 1000 */
2502 hw
->phy
.ops
.write_reg(hw
, 0x0000, 0x1340);
2504 return (E1000_SUCCESS
);
2508 * e1000_get_phy_type_from_id - Get PHY type from id
2509 * @phy_id: phy_id read from the phy
2511 * Returns the phy type from the id.
2514 e1000_get_phy_type_from_id(u32 phy_id
)
2516 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
2519 case M88E1000_I_PHY_ID
:
2520 case M88E1000_E_PHY_ID
:
2521 case M88E1111_I_PHY_ID
:
2522 case M88E1011_I_PHY_ID
:
2523 phy_type
= e1000_phy_m88
;
2525 case IGP01E1000_I_PHY_ID
: /* IGP 1 & 2 share this */
2526 phy_type
= e1000_phy_igp_2
;
2528 case GG82563_E_PHY_ID
:
2529 phy_type
= e1000_phy_gg82563
;
2531 case IGP03E1000_E_PHY_ID
:
2532 phy_type
= e1000_phy_igp_3
;
2535 case IFE_PLUS_E_PHY_ID
:
2536 case IFE_C_E_PHY_ID
:
2537 phy_type
= e1000_phy_ife
;
2539 case BME1000_E_PHY_ID
:
2540 case BME1000_E_PHY_ID_R2
:
2541 phy_type
= e1000_phy_bm
;
2543 case I82578_E_PHY_ID
:
2544 phy_type
= e1000_phy_82578
;
2546 case I82577_E_PHY_ID
:
2547 phy_type
= e1000_phy_82577
;
2549 case I82579_E_PHY_ID
:
2550 phy_type
= e1000_phy_82579
;
2553 phy_type
= e1000_phy_unknown
;
2560 * e1000_determine_phy_address - Determines PHY address.
2561 * @hw: pointer to the HW structure
2563 * This uses a trial and error method to loop through possible PHY
2564 * addresses. It tests each by reading the PHY ID registers and
2565 * checking for a match.
2568 e1000_determine_phy_address(struct e1000_hw
*hw
)
2570 s32 ret_val
= -E1000_ERR_PHY_TYPE
;
2573 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
2575 hw
->phy
.id
= phy_type
;
2577 for (phy_addr
= 0; phy_addr
< E1000_MAX_PHY_ADDR
; phy_addr
++) {
2578 hw
->phy
.addr
= phy_addr
;
2582 (void) e1000_get_phy_id(hw
);
2583 phy_type
= e1000_get_phy_type_from_id(hw
->phy
.id
);
2586 * If phy_type is valid, break - we found our
2589 if (phy_type
!= e1000_phy_unknown
) {
2590 ret_val
= E1000_SUCCESS
;
2603 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2604 * @page: page to access
2606 * Returns the phy address for the page requested.
2609 e1000_get_phy_addr_for_bm_page(u32 page
, u32 reg
)
2613 if ((page
>= 768) || (page
== 0 && reg
== 25) || (reg
== 31))
2620 * e1000_write_phy_reg_bm - Write BM PHY register
2621 * @hw: pointer to the HW structure
2622 * @offset: register offset to write to
2623 * @data: data to write at register offset
2625 * Acquires semaphore, if necessary, then writes the data to PHY register
2626 * at the offset. Release any acquired semaphores before exiting.
2629 e1000_write_phy_reg_bm(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2632 u32 page_select
= 0;
2633 u32 page
= offset
>> IGP_PAGE_SHIFT
;
2636 DEBUGFUNC("e1000_write_phy_reg_bm");
2638 ret_val
= hw
->phy
.ops
.acquire(hw
);
2642 /* Page 800 works differently than the rest so it has its own func */
2643 if (page
== BM_WUC_PAGE
) {
2644 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
,
2645 offset
, &data
, false);
2649 hw
->phy
.addr
= e1000_get_phy_addr_for_bm_page(page
, offset
);
2651 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2653 * Page select is register 31 for phy address 1 and 22 for phy
2654 * address 2 and 3. Page select is shifted only for phy
2657 if (hw
->phy
.addr
== 1) {
2658 page_shift
= IGP_PAGE_SHIFT
;
2659 page_select
= IGP01E1000_PHY_PAGE_SELECT
;
2662 page_select
= BM_PHY_PAGE_SELECT
;
2665 /* Page is shifted left, PHY expects (page x 32) */
2666 ret_val
= e1000_write_phy_reg_mdic(hw
, page_select
,
2667 (page
<< page_shift
));
2672 ret_val
= e1000_write_phy_reg_mdic(hw
,
2673 MAX_PHY_REG_ADDRESS
& offset
,
2677 hw
->phy
.ops
.release(hw
);
2682 * e1000_read_phy_reg_bm - Read BM PHY register
2683 * @hw: pointer to the HW structure
2684 * @offset: register offset to be read
2685 * @data: pointer to the read data
2687 * Acquires semaphore, if necessary, then reads the PHY register at offset
2688 * and storing the retrieved information in data. Release any acquired
2689 * semaphores before exiting.
2692 e1000_read_phy_reg_bm(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2695 u32 page_select
= 0;
2696 u32 page
= offset
>> IGP_PAGE_SHIFT
;
2699 DEBUGFUNC("e1000_read_phy_reg_bm");
2701 ret_val
= hw
->phy
.ops
.acquire(hw
);
2705 /* Page 800 works differently than the rest so it has its own func */
2706 if (page
== BM_WUC_PAGE
) {
2707 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
,
2708 offset
, data
, true);
2712 hw
->phy
.addr
= e1000_get_phy_addr_for_bm_page(page
, offset
);
2714 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2716 * Page select is register 31 for phy address 1 and 22 for phy
2717 * address 2 and 3. Page select is shifted only for phy
2720 if (hw
->phy
.addr
== 1) {
2721 page_shift
= IGP_PAGE_SHIFT
;
2722 page_select
= IGP01E1000_PHY_PAGE_SELECT
;
2725 page_select
= BM_PHY_PAGE_SELECT
;
2728 /* Page is shifted left, PHY expects (page x 32) */
2729 ret_val
= e1000_write_phy_reg_mdic(hw
, page_select
,
2730 (page
<< page_shift
));
2735 ret_val
= e1000_read_phy_reg_mdic(hw
,
2736 MAX_PHY_REG_ADDRESS
& offset
,
2740 hw
->phy
.ops
.release(hw
);
2745 * e1000_read_phy_reg_bm2 - Read BM PHY register
2746 * @hw: pointer to the HW structure
2747 * @offset: register offset to be read
2748 * @data: pointer to the read data
2750 * Acquires semaphore, if necessary, then reads the PHY register at offset
2751 * and storing the retrieved information in data. Release any acquired
2752 * semaphores before exiting.
2755 e1000_read_phy_reg_bm2(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2758 u16 page
= (u16
)(offset
>> IGP_PAGE_SHIFT
);
2760 DEBUGFUNC("e1000_write_phy_reg_bm2");
2762 ret_val
= hw
->phy
.ops
.acquire(hw
);
2766 /* Page 800 works differently than the rest so it has its own func */
2767 if (page
== BM_WUC_PAGE
) {
2768 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, data
,
2775 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2777 /* Page is shifted left, PHY expects (page x 32) */
2778 ret_val
= e1000_write_phy_reg_mdic(hw
, BM_PHY_PAGE_SELECT
,
2785 ret_val
= e1000_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2789 hw
->phy
.ops
.release(hw
);
2794 * e1000_write_phy_reg_bm2 - Write BM PHY register
2795 * @hw: pointer to the HW structure
2796 * @offset: register offset to write to
2797 * @data: data to write at register offset
2799 * Acquires semaphore, if necessary, then writes the data to PHY register
2800 * at the offset. Release any acquired semaphores before exiting.
2803 e1000_write_phy_reg_bm2(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2806 u16 page
= (u16
)(offset
>> IGP_PAGE_SHIFT
);
2808 DEBUGFUNC("e1000_write_phy_reg_bm2");
2810 ret_val
= hw
->phy
.ops
.acquire(hw
);
2814 /* Page 800 works differently than the rest so it has its own func */
2815 if (page
== BM_WUC_PAGE
) {
2816 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, &data
,
2823 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2824 /* Page is shifted left, PHY expects (page x 32) */
2825 ret_val
= e1000_write_phy_reg_mdic(hw
, BM_PHY_PAGE_SELECT
,
2832 ret_val
= e1000_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2836 hw
->phy
.ops
.release(hw
);
2841 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
2842 * @hw: pointer to the HW structure
2843 * @offset: register offset to be read or written
2844 * @data: pointer to the data to read or write
2845 * @read: determines if operation is read or write
2847 * Acquires semaphore, if necessary, then reads the PHY register at offset
2848 * and storing the retrieved information in data. Release any acquired
2849 * semaphores before exiting. Note that procedure to read the wakeup
2850 * registers are different. It works as such:
2851 * 1) Set page 769, register 17, bit 2 = 1
2852 * 2) Set page to 800 for host (801 if we were manageability)
2853 * 3) Write the address using the address opcode (0x11)
2854 * 4) Read or write the data using the data opcode (0x12)
2855 * 5) Restore 769_17.2 to its original value
2857 * Assumes semaphore already acquired.
2860 e1000_access_phy_wakeup_reg_bm(struct e1000_hw
*hw
,
2861 u32 offset
, u16
*data
, bool read
)
2864 u16 reg
= BM_PHY_REG_NUM(offset
);
2867 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
2869 /* Gig must be disabled for MDIO accesses to page 800 */
2870 if ((hw
->mac
.type
== e1000_pchlan
) &&
2871 (!(E1000_READ_REG(hw
, E1000_PHY_CTRL
) &
2872 E1000_PHY_CTRL_GBE_DISABLE
))) {
2874 DEBUGOUT("Attempting to access page 800 while gig enabled.\n");
2877 /* All operations in this function are phy address 1 */
2881 (void) e1000_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2882 (BM_WUC_ENABLE_PAGE
<< IGP_PAGE_SHIFT
));
2884 ret_val
= e1000_read_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, &phy_reg
);
2886 DEBUGOUT("Could not read PHY page 769\n");
2890 /* First clear bit 4 to avoid a power state change */
2891 phy_reg
&= ~(BM_WUC_HOST_WU_BIT
);
2892 ret_val
= e1000_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, phy_reg
);
2894 DEBUGOUT("Could not clear PHY page 769 bit 4\n");
2898 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2899 ret_val
= e1000_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
,
2900 phy_reg
| BM_WUC_ENABLE_BIT
);
2902 DEBUGOUT("Could not write PHY page 769 bit 2\n");
2906 /* Select page 800 */
2907 ret_val
= e1000_write_phy_reg_mdic(hw
,
2908 IGP01E1000_PHY_PAGE_SELECT
,
2909 (BM_WUC_PAGE
<< IGP_PAGE_SHIFT
));
2911 /* Write the page 800 offset value using opcode 0x11 */
2912 ret_val
= e1000_write_phy_reg_mdic(hw
, BM_WUC_ADDRESS_OPCODE
, reg
);
2914 DEBUGOUT("Could not write address opcode to page 800\n");
2919 /* Read the page 800 value using opcode 0x12 */
2920 ret_val
= e1000_read_phy_reg_mdic(hw
, BM_WUC_DATA_OPCODE
,
2923 /* Write the page 800 value using opcode 0x12 */
2924 ret_val
= e1000_write_phy_reg_mdic(hw
, BM_WUC_DATA_OPCODE
,
2929 DEBUGOUT("Could not access data value from page 800\n");
2934 * Restore 769_17.2 to its original value Set page 769
2936 (void) e1000_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2937 (BM_WUC_ENABLE_PAGE
<< IGP_PAGE_SHIFT
));
2939 /* Clear 769_17.2 */
2940 ret_val
= e1000_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, phy_reg
);
2942 DEBUGOUT("Could not clear PHY page 769 bit 2\n");
2951 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2952 * @hw: pointer to the HW structure
2954 * In the case of a PHY power down to save power, or to turn off link during a
2955 * driver unload, or wake on lan is not enabled, restore the link to previous
2959 e1000_power_up_phy_copper(struct e1000_hw
*hw
)
2963 /* The PHY will retain its settings across a power down/up cycle */
2964 hw
->phy
.ops
.read_reg(hw
, PHY_CONTROL
, &mii_reg
);
2965 mii_reg
&= ~MII_CR_POWER_DOWN
;
2966 hw
->phy
.ops
.write_reg(hw
, PHY_CONTROL
, mii_reg
);
2970 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2971 * @hw: pointer to the HW structure
2973 * In the case of a PHY power down to save power, or to turn off link during a
2974 * driver unload, or wake on lan is not enabled, restore the link to previous
2978 e1000_power_down_phy_copper(struct e1000_hw
*hw
)
2982 /* The PHY will retain its settings across a power down/up cycle */
2983 hw
->phy
.ops
.read_reg(hw
, PHY_CONTROL
, &mii_reg
);
2984 mii_reg
|= MII_CR_POWER_DOWN
;
2985 hw
->phy
.ops
.write_reg(hw
, PHY_CONTROL
, mii_reg
);
2990 * __e1000_read_phy_reg_hv - Read HV PHY register
2991 * @hw: pointer to the HW structure
2992 * @offset: register offset to be read
2993 * @data: pointer to the read data
2994 * @locked: semaphore has already been acquired or not
2996 * Acquires semaphore, if necessary, then reads the PHY register at offset
2997 * and stores the retrieved information in data. Release any acquired
2998 * semaphore before exiting.
3001 __e1000_read_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
3005 u16 page
= BM_PHY_REG_PAGE(offset
);
3006 u16 reg
= BM_PHY_REG_NUM(offset
);
3008 DEBUGFUNC("__e1000_read_phy_reg_hv");
3011 ret_val
= hw
->phy
.ops
.acquire(hw
);
3016 /* Page 800 works differently than the rest so it has its own func */
3017 if (page
== BM_WUC_PAGE
) {
3018 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
,
3023 if (page
> 0 && page
< HV_INTC_FC_PAGE_START
) {
3024 ret_val
= e1000_access_phy_debug_regs_hv(hw
, offset
,
3029 hw
->phy
.addr
= e1000_get_phy_addr_for_hv_page(page
);
3031 if (page
== HV_INTC_FC_PAGE_START
)
3034 if (reg
> MAX_PHY_MULTI_PAGE_REG
) {
3035 u32 phy_addr
= hw
->phy
.addr
;
3039 /* Page is shifted left, PHY expects (page x 32) */
3040 ret_val
= e1000_write_phy_reg_mdic(hw
,
3041 IGP01E1000_PHY_PAGE_SELECT
, (page
<< IGP_PAGE_SHIFT
));
3042 hw
->phy
.addr
= phy_addr
;
3048 ret_val
= e1000_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& reg
, data
);
3051 hw
->phy
.ops
.release(hw
);
3057 * e1000_read_phy_reg_hv - Read HV PHY register
3058 * @hw: pointer to the HW structure
3059 * @offset: register offset to be read
3060 * @data: pointer to the read data
3062 * Acquires semaphore then reads the PHY register at offset and stores
3063 * the retrieved information in data. Release the acquired semaphore
3067 e1000_read_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
3069 return (__e1000_read_phy_reg_hv(hw
, offset
, data
, false));
3073 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3074 * @hw: pointer to the HW structure
3075 * @offset: register offset to be read
3076 * @data: pointer to the read data
3078 * Reads the PHY register at offset and stores the retrieved information
3079 * in data. Assumes semaphore already acquired.
3082 e1000_read_phy_reg_hv_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
3084 return (__e1000_read_phy_reg_hv(hw
, offset
, data
, true));
3088 * __e1000_write_phy_reg_hv - Write HV PHY register
3089 * @hw: pointer to the HW structure
3090 * @offset: register offset to write to
3091 * @data: data to write at register offset
3092 * @locked: semaphore has already been acquired or not
3094 * Acquires semaphore, if necessary, then writes the data to PHY register
3095 * at the offset. Release any acquired semaphores before exiting.
3098 __e1000_write_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16 data
,
3102 u16 page
= BM_PHY_REG_PAGE(offset
);
3103 u16 reg
= BM_PHY_REG_NUM(offset
);
3105 DEBUGFUNC("__e1000_write_phy_reg_hv");
3108 ret_val
= hw
->phy
.ops
.acquire(hw
);
3113 /* Page 800 works differently than the rest so it has its own func */
3114 if (page
== BM_WUC_PAGE
) {
3115 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
,
3120 if (page
> 0 && page
< HV_INTC_FC_PAGE_START
) {
3121 ret_val
= e1000_access_phy_debug_regs_hv(hw
, offset
,
3126 hw
->phy
.addr
= e1000_get_phy_addr_for_hv_page(page
);
3128 if (page
== HV_INTC_FC_PAGE_START
)
3132 * Workaround MDIO accesses being disabled after entering IEEE Power
3133 * Down (whenever bit 11 of the PHY Control register is set)
3135 if ((hw
->phy
.type
== e1000_phy_82578
) &&
3136 (hw
->phy
.revision
>= 1) &&
3137 (hw
->phy
.addr
== 2) &&
3138 ((MAX_PHY_REG_ADDRESS
& reg
) == 0) &&
3139 (data
& (1 << 11))) {
3141 ret_val
= e1000_access_phy_debug_regs_hv(hw
, (1 << 6) | 0x3,
3147 if (reg
> MAX_PHY_MULTI_PAGE_REG
) {
3148 u32 phy_addr
= hw
->phy
.addr
;
3152 /* Page is shifted left, PHY expects (page x 32) */
3153 ret_val
= e1000_write_phy_reg_mdic(hw
,
3154 IGP01E1000_PHY_PAGE_SELECT
, (page
<< IGP_PAGE_SHIFT
));
3155 hw
->phy
.addr
= phy_addr
;
3161 ret_val
= e1000_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& reg
,
3166 hw
->phy
.ops
.release(hw
);
3172 * e1000_write_phy_reg_hv - Write HV PHY register
3173 * @hw: pointer to the HW structure
3174 * @offset: register offset to write to
3175 * @data: data to write at register offset
3177 * Acquires semaphore then writes the data to PHY register at the offset.
3178 * Release the acquired semaphores before exiting.
3181 e1000_write_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16 data
)
3183 return (__e1000_write_phy_reg_hv(hw
, offset
, data
, false));
3187 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3188 * @hw: pointer to the HW structure
3189 * @offset: register offset to write to
3190 * @data: data to write at register offset
3192 * Writes the data to PHY register at the offset. Assumes semaphore
3196 e1000_write_phy_reg_hv_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
3198 return (__e1000_write_phy_reg_hv(hw
, offset
, data
, true));
3202 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3203 * @page: page to be accessed
3206 e1000_get_phy_addr_for_hv_page(u32 page
)
3210 if (page
>= HV_INTC_FC_PAGE_START
)
3217 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3218 * @hw: pointer to the HW structure
3219 * @offset: register offset to be read or written
3220 * @data: pointer to the data to be read or written
3221 * @read: determines if operation is read or written
3223 * Reads the PHY register at offset and stores the retreived information
3224 * in data. Assumes semaphore already acquired. Note that the procedure
3225 * to read these regs uses the address port and data port to read/write.
3228 e1000_access_phy_debug_regs_hv(struct e1000_hw
*hw
, u32 offset
,
3229 u16
*data
, bool read
)
3235 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3237 /* This takes care of the difference with desktop vs mobile phy */
3238 addr_reg
= (hw
->phy
.type
== e1000_phy_82578
) ?
3239 I82578_ADDR_REG
: I82577_ADDR_REG
;
3240 data_reg
= addr_reg
+ 1;
3242 /* All operations in this function are phy address 2 */
3245 /* masking with 0x3F to remove the page from offset */
3246 ret_val
= e1000_write_phy_reg_mdic(hw
, addr_reg
, (u16
)offset
& 0x3F);
3248 DEBUGOUT("Could not write PHY the HV address register\n");
3252 /* Read or write the data value next */
3254 ret_val
= e1000_read_phy_reg_mdic(hw
, data_reg
, data
);
3256 ret_val
= e1000_write_phy_reg_mdic(hw
, data_reg
, *data
);
3259 DEBUGOUT("Could not read data value from HV data register\n");
3268 * e1000_link_stall_workaround_hv - Si workaround
3269 * @hw: pointer to the HW structure
3271 * This function works around a Si bug where the link partner can get
3272 * a link up indication before the PHY does. If small packets are sent
3273 * by the link partner they can be placed in the packet buffer without
3274 * being properly accounted for by the PHY and will stall preventing
3275 * further packets from being received. The workaround is to clear the
3276 * packet buffer after the PHY detects link up.
3279 e1000_link_stall_workaround_hv(struct e1000_hw
*hw
)
3281 s32 ret_val
= E1000_SUCCESS
;
3284 DEBUGFUNC("e1000_link_stall_workaround_hv");
3286 if (hw
->phy
.type
!= e1000_phy_82578
)
3289 /* Do not apply workaround if in PHY loopback bit 14 set */
3290 hw
->phy
.ops
.read_reg(hw
, PHY_CONTROL
, &data
);
3291 if (data
& PHY_CONTROL_LB
)
3294 /* check if link is up and at 1Gbps */
3295 ret_val
= hw
->phy
.ops
.read_reg(hw
, BM_CS_STATUS
, &data
);
3299 data
&= BM_CS_STATUS_LINK_UP
|
3300 BM_CS_STATUS_RESOLVED
|
3301 BM_CS_STATUS_SPEED_MASK
;
3303 if (data
!= (BM_CS_STATUS_LINK_UP
|
3304 BM_CS_STATUS_RESOLVED
|
3305 BM_CS_STATUS_SPEED_1000
))
3310 /* flush the packets in the fifo buffer */
3311 ret_val
= hw
->phy
.ops
.write_reg(hw
, HV_MUX_DATA_CTRL
,
3312 HV_MUX_DATA_CTRL_GEN_TO_MAC
| HV_MUX_DATA_CTRL_FORCE_SPEED
);
3316 ret_val
= hw
->phy
.ops
.write_reg(hw
, HV_MUX_DATA_CTRL
,
3317 HV_MUX_DATA_CTRL_GEN_TO_MAC
);
3324 * e1000_check_polarity_82577 - Checks the polarity.
3325 * @hw: pointer to the HW structure
3327 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3329 * Polarity is determined based on the PHY specific status register.
3332 e1000_check_polarity_82577(struct e1000_hw
*hw
)
3334 struct e1000_phy_info
*phy
= &hw
->phy
;
3338 DEBUGFUNC("e1000_check_polarity_82577");
3340 ret_val
= phy
->ops
.read_reg(hw
, I82577_PHY_STATUS_2
, &data
);
3343 phy
->cable_polarity
= (data
& I82577_PHY_STATUS2_REV_POLARITY
)
3344 ? e1000_rev_polarity_reversed
3345 : e1000_rev_polarity_normal
;
3351 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3352 * @hw: pointer to the HW structure
3354 * Calls the PHY setup function to force speed and duplex. Clears the
3355 * auto-crossover to force MDI manually. Waits for link and returns
3356 * successful if link up is successful, else -E1000_ERR_PHY (-2).
3359 e1000_phy_force_speed_duplex_82577(struct e1000_hw
*hw
)
3361 struct e1000_phy_info
*phy
= &hw
->phy
;
3366 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3368 ret_val
= phy
->ops
.read_reg(hw
, PHY_CONTROL
, &phy_data
);
3372 e1000_phy_force_speed_duplex_setup(hw
, &phy_data
);
3374 ret_val
= phy
->ops
.write_reg(hw
, PHY_CONTROL
, phy_data
);
3379 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI
3380 * forced whenever speed and duplex are forced.
3382 ret_val
= phy
->ops
.read_reg(hw
, I82577_PHY_CTRL_2
, &phy_data
);
3386 phy_data
&= ~I82577_PHY_CTRL2_AUTO_MDIX
;
3387 phy_data
&= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX
;
3389 ret_val
= phy
->ops
.write_reg(hw
, I82577_PHY_CTRL_2
, phy_data
);
3393 DEBUGOUT1("I82577_PHY_CTRL_2: %X\n", phy_data
);
3397 if (phy
->autoneg_wait_to_complete
) {
3398 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3400 ret_val
= e1000_phy_has_link_generic(hw
,
3401 PHY_FORCE_LIMIT
, 100000, &link
);
3407 DEBUGOUT("Link taking longer than expected.\n");
3411 ret_val
= e1000_phy_has_link_generic(hw
,
3412 PHY_FORCE_LIMIT
, 100000, &link
);
3422 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3423 * @hw: pointer to the HW structure
3425 * Read PHY status to determine if link is up. If link is up, then
3426 * set/determine 10base-T extended distance and polarity correction. Read
3427 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3428 * determine on the cable length, local and remote receiver.
3431 e1000_get_phy_info_82577(struct e1000_hw
*hw
)
3433 struct e1000_phy_info
*phy
= &hw
->phy
;
3438 DEBUGFUNC("e1000_get_phy_info_82577");
3440 ret_val
= e1000_phy_has_link_generic(hw
, 1, 0, &link
);
3445 DEBUGOUT("Phy info is only valid if link is up\n");
3446 ret_val
= -E1000_ERR_CONFIG
;
3450 phy
->polarity_correction
= true;
3452 ret_val
= e1000_check_polarity_82577(hw
);
3456 ret_val
= phy
->ops
.read_reg(hw
, I82577_PHY_STATUS_2
, &data
);
3460 phy
->is_mdix
= (data
& I82577_PHY_STATUS2_MDIX
) ? true : false;
3462 if ((data
& I82577_PHY_STATUS2_SPEED_MASK
) ==
3463 I82577_PHY_STATUS2_SPEED_1000MBPS
) {
3464 ret_val
= hw
->phy
.ops
.get_cable_length(hw
);
3468 ret_val
= phy
->ops
.read_reg(hw
, PHY_1000T_STATUS
, &data
);
3472 phy
->local_rx
= (data
& SR_1000T_LOCAL_RX_STATUS
)
3473 ? e1000_1000t_rx_status_ok
: e1000_1000t_rx_status_not_ok
;
3475 phy
->remote_rx
= (data
& SR_1000T_REMOTE_RX_STATUS
)
3476 ? e1000_1000t_rx_status_ok
: e1000_1000t_rx_status_not_ok
;
3478 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
3479 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
3480 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
3488 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3489 * @hw: pointer to the HW structure
3491 * Reads the diagnostic status register and verifies result is valid before
3492 * placing it in the phy_cable_length field.
3495 e1000_get_cable_length_82577(struct e1000_hw
*hw
)
3497 struct e1000_phy_info
*phy
= &hw
->phy
;
3499 u16 phy_data
, length
;
3501 DEBUGFUNC("e1000_get_cable_length_82577");
3503 ret_val
= phy
->ops
.read_reg(hw
, I82577_PHY_DIAG_STATUS
, &phy_data
);
3507 length
= (phy_data
& I82577_DSTATUS_CABLE_LENGTH
) >>
3508 I82577_DSTATUS_CABLE_LENGTH_SHIFT
;
3510 if (length
== E1000_CABLE_LENGTH_UNDEFINED
)
3511 ret_val
= E1000_ERR_PHY
;
3513 phy
->cable_length
= length
;