usr/src/uts/i86pc/io/speedstep.c

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  */
  25
  26 #pragma ident   "%Z%%M% %I%     %E% SMI"
  27
  28 #include <sys/x86_archext.h>
  29 #include <sys/machsystm.h>
  30 #include <sys/x_call.h>
  31 #include <sys/acpi/acpi.h>
  32 #include <sys/acpica.h>
  33 #include <sys/speedstep.h>
  34 #include <sys/cpu_acpi.h>
  35 #include <sys/cpupm.h>
  36 #include <sys/dtrace.h>
  37 #include <sys/sdt.h>
  38
  39 /*
  40  * Error returns
  41  */
  42 #define ESS_RET_SUCCESS         0x00
  43 #define ESS_RET_NO_PM           0x01
  44 #define ESS_RET_UNSUP_STATE     0x02
  45
  46 /*
  47  * Intel docs indicate that maximum latency of P-state changes should
  48  * be on the order of 10mS. When waiting, wait in 100uS increments.
  49  */
  50 #define ESS_MAX_LATENCY_MICROSECS       10000
  51 #define ESS_LATENCY_WAIT                100
  52
  53 /*
  54  * The SpeedStep related Processor Driver Capabilities (_PDC).
  55  * See Intel Processor Vendor-Specific ACPI Interface Specification
  56  * for details.
  57  */
  58 #define ESS_PDC_REVISION                0x1
  59 #define ESS_PDC_PS_MSR                  (1<<0)
  60 #define ESS_PDC_IO_BEFORE_HALT          (1<<1)
  61 #define ESS_PDC_MP                      (1<<3)
  62 #define ESS_PDC_PSD                     (1<<5)
  63
  64 /*
  65  * MSR registers for changing and reading processor power state.
  66  */
  67 #define IA32_PERF_STAT_MSR              0x198
  68 #define IA32_PERF_CTL_MSR               0x199
  69
  70 #define IA32_CPUID_TSC_CONSTANT         0xF30
  71 #define IA32_MISC_ENABLE_MSR            0x1A0
  72 #define IA32_MISC_ENABLE_EST            (1<<16)
  73 #define IA32_MISC_ENABLE_CXE            (1<<25)
  74 /*
  75  * Debugging support
  76  */
  77 #ifdef  DEBUG
  78 volatile int ess_debug = 0;
  79 #define ESSDEBUG(arglist) if (ess_debug) printf arglist;
  80 #else
  81 #define ESSDEBUG(arglist)
  82 #endif
  83
  84 typedef struct speedstep_state {
  85         uint32_t ss_state;
  86 } speedstep_state_t;
  87
  88 /*
  89  * Note that SpeedStep support requires the following _PDC bits be
  90  * enabled so that ACPI returns the proper objects. The requirement
  91  * that ESS_PDC_IO_BEFORE_HALT be enabled probably seems strange.
  92  * Unfortunately, the _PDC bit for this feature has been historically
  93  * misassociated with SpeedStep support and some BIOS implementations
  94  * erroneously check this bit when evaluating _PSS methods. Enabling
  95  * this bit is our only option as the likelihood of a BIOS fix on all
  96  * affected platforms is not very good.
  97  */
  98 uint32_t ess_pdccap = ESS_PDC_PS_MSR | ESS_PDC_IO_BEFORE_HALT |
  99     ESS_PDC_MP | ESS_PDC_PSD;
 100
 101 /*
 102  * Read the status register. How it is read, depends upon the _PCT
 103  * APCI object value.
 104  */
 105 static int
 106 read_status(cpu_acpi_handle_t handle, uint32_t *stat)
 107 {
 108         cpu_acpi_pct_t *pct_stat;
 109         uint64_t reg;
 110         int ret = 0;
 111
 112         pct_stat = CPU_ACPI_PCT_STATUS(handle);
 113
 114         switch (pct_stat->pc_addrspace_id) {
 115         case ACPI_ADR_SPACE_FIXED_HARDWARE:
 116                 reg = rdmsr(IA32_PERF_STAT_MSR);
 117                 *stat = reg & 0xFFFF;
 118                 ret = 0;
 119                 break;
 120
 121         case ACPI_ADR_SPACE_SYSTEM_IO:
 122                 ret = cpu_acpi_read_port(pct_stat->pc_address, stat,
 123                     pct_stat->pc_width);
 124                 break;
 125
 126         default:
 127                 DTRACE_PROBE1(ess_status_unsupported_type, uint8_t,
 128                     pct_stat->pc_addrspace_id);
 129                 return (-1);
 130         }
 131
 132         DTRACE_PROBE1(ess_status_read, uint32_t, *stat);
 133         DTRACE_PROBE1(ess_status_read_err, int, ret);
 134
 135         return (ret);
 136 }
 137
 138 /*
 139  * Write the ctrl register. How it is written, depends upon the _PCT
 140  * APCI object value.
 141  */
 142 static int
 143 write_ctrl(cpu_acpi_handle_t handle, uint32_t ctrl)
 144 {
 145         cpu_acpi_pct_t *pct_ctrl;
 146         uint64_t reg;
 147         int ret = 0;
 148
 149         pct_ctrl = CPU_ACPI_PCT_CTRL(handle);
 150
 151         switch (pct_ctrl->pc_addrspace_id) {
 152         case ACPI_ADR_SPACE_FIXED_HARDWARE:
 153                 /*
 154                  * Read current power state because reserved bits must be
 155                  * preserved, compose new value, and write it.
 156                  */
 157                 reg = rdmsr(IA32_PERF_CTL_MSR);
 158                 reg &= ~((uint64_t)0xFFFF);
 159                 reg |= ctrl;
 160                 wrmsr(IA32_PERF_CTL_MSR, reg);
 161                 ret = 0;
 162                 break;
 163
 164         case ACPI_ADR_SPACE_SYSTEM_IO:
 165                 ret = cpu_acpi_write_port(pct_ctrl->pc_address, ctrl,
 166                     pct_ctrl->pc_width);
 167                 break;
 168
 169         default:
 170                 DTRACE_PROBE1(ess_ctrl_unsupported_type, uint8_t,
 171                     pct_ctrl->pc_addrspace_id);
 172                 return (-1);
 173         }
 174
 175         DTRACE_PROBE1(ess_ctrl_write, uint32_t, ctrl);
 176         DTRACE_PROBE1(ess_ctrl_write_err, int, ret);
 177
 178         return (ret);
 179 }
 180
 181 /*
 182  * Transition the current processor to the requested state.
 183  */
 184 void
 185 speedstep_pstate_transition(int *ret, cpudrv_devstate_t *cpudsp,
 186     uint32_t req_state)
 187 {
 188         speedstep_state_t *speedstep_state = cpudsp->module_state;
 189         cpu_acpi_handle_t handle = cpudsp->acpi_handle;
 190         cpu_acpi_pstate_t *req_pstate;
 191         uint32_t ctrl;
 192         uint32_t stat;
 193         int i;
 194
 195         req_pstate = CPU_ACPI_PSTATE(handle, req_state);
 196         DTRACE_PROBE1(ess_transition, uint32_t, CPU_ACPI_FREQ(req_pstate));
 197
 198         /*
 199          * Initiate the processor p-state change.
 200          */
 201         ctrl = CPU_ACPI_CTRL(req_pstate);
 202         if (write_ctrl(handle, ctrl) != 0) {
 203                 *ret = ESS_RET_UNSUP_STATE;
 204                 return;
 205         }
 206
 207         /* Wait until switch is complete, but bound the loop just in case. */
 208         for (i = 0; i < ESS_MAX_LATENCY_MICROSECS; i += ESS_LATENCY_WAIT) {
 209                 if (read_status(handle, &stat) == 0 &&
 210                     CPU_ACPI_STAT(req_pstate) == stat)
 211                         break;
 212                 drv_usecwait(ESS_LATENCY_WAIT);
 213         }
 214         if (i >= ESS_MAX_LATENCY_MICROSECS) {
 215                 DTRACE_PROBE(ess_transition_incomplete);
 216         }
 217
 218         speedstep_state->ss_state = req_state;
 219         CPU->cpu_curr_clock =
 220             (((uint64_t)CPU_ACPI_FREQ(req_pstate) * 1000000));
 221         *ret = ESS_RET_SUCCESS;
 222 }
 223
 224 int
 225 speedstep_power(cpudrv_devstate_t *cpudsp, uint32_t req_state)
 226 {
 227         cpuset_t cpus;
 228         int ret;
 229
 230         CPUSET_ONLY(cpus, cpudsp->cpu_id);
 231
 232         kpreempt_disable();
 233         xc_call((xc_arg_t)&ret, (xc_arg_t)cpudsp, (xc_arg_t)req_state,
 234             X_CALL_HIPRI, cpus, (xc_func_t)speedstep_pstate_transition);
 235         kpreempt_enable();
 236
 237         return (ret);
 238 }
 239
 240 /*
 241  * Validate that this processor supports Speedstep and if so,
 242  * get the P-state data from ACPI and cache it.
 243  */
 244 int
 245 speedstep_init(cpudrv_devstate_t *cpudsp)
 246 {
 247         speedstep_state_t *speedstep_state;
 248         cpu_acpi_handle_t handle;
 249         cpu_acpi_pct_t *pct_stat;
 250         uint64_t reg;
 251         uint_t family;
 252         uint_t model;
 253         struct cpuid_regs cpu_regs;
 254         cpu_t *cp;
 255         int dependency;
 256
 257         ESSDEBUG(("speedstep_init: instance %d\n",
 258             ddi_get_instance(cpudsp->dip)));
 259
 260         /* Intel w/ CPUID support and rdmsr/wrmsr? */
 261         if (x86_vendor != X86_VENDOR_Intel ||
 262             !(x86_feature & X86_CPUID) ||
 263             !(x86_feature & X86_MSR)) {
 264                 ESSDEBUG(("Either not Intel or feature not supported.\n"));
 265                 return (ESS_RET_NO_PM);
 266         }
 267
 268         /*
 269          * Enhanced Speedstep supported?
 270          */
 271         cpu_regs.cp_eax = 0x1;
 272         (void) __cpuid_insn(&cpu_regs);
 273         if (!(cpu_regs.cp_ecx & CPUID_INTC_ECX_EST)) {
 274                 ESSDEBUG(("Enhanced Speedstep not supported.\n"));
 275                 return (ESS_RET_NO_PM);
 276         }
 277
 278         family = cpuid_getfamily(CPU);
 279         model = cpuid_getmodel(CPU);
 280         if (!((family == 0xf && model >= 0x3) ||
 281             (family == 0x6 && model >= 0xe))) {
 282                 ESSDEBUG(("Variant TSC not supported.\n"));
 283                 return (ESS_RET_NO_PM);
 284         }
 285
 286         /*
 287          * If Enhanced Speedstep has not been enabled on the system,
 288          * then we probably should not override the BIOS setting.
 289          */
 290         reg = rdmsr(IA32_MISC_ENABLE_MSR);
 291         if (! (reg & IA32_MISC_ENABLE_EST)) {
 292                 cmn_err(CE_NOTE, "!Enhanced Intel SpeedStep not enabled.");
 293                 cmn_err(CE_NOTE, "!CPU power management will not function.");
 294                 return (ESS_RET_NO_PM);
 295         }
 296
 297         /*
 298          * Enhanced Speedstep requires ACPI support. Get a handle
 299          * to the correct processor object for this dip.
 300          */
 301         handle = cpudsp->acpi_handle = cpu_acpi_init(cpudsp->dip);
 302         if (handle == NULL) {
 303                 cmn_err(CE_WARN, "!speedstep_init: instance %d: "
 304                     "unable to get ACPI handle",
 305                     ddi_get_instance(cpudsp->dip));
 306
 307                 cmn_err(CE_NOTE, "!CPU power management will not function.");
 308                 return (ESS_RET_NO_PM);
 309         }
 310
 311         /*
 312          * _PDC support is optional and the driver should
 313          * function even if the _PDC write fails.
 314          */
 315         if (cpu_acpi_write_pdc(handle, ESS_PDC_REVISION, 1,
 316             &ess_pdccap) != 0)
 317                 ESSDEBUG(("Failed to write PDC\n"));
 318
 319         if (cpu_acpi_cache_data(handle) != 0) {
 320                 ESSDEBUG(("Failed to cache ACPI data\n"));
 321                 cpu_acpi_fini(handle);
 322                 return (ESS_RET_NO_PM);
 323         }
 324
 325         pct_stat = CPU_ACPI_PCT_STATUS(handle);
 326         switch (pct_stat->pc_addrspace_id) {
 327         case ACPI_ADR_SPACE_FIXED_HARDWARE:
 328                 ESSDEBUG(("Transitions will use fixed hardware\n"));
 329                 break;
 330         case ACPI_ADR_SPACE_SYSTEM_IO:
 331                 ESSDEBUG(("Transitions will use system IO\n"));
 332                 break;
 333         default:
 334                 cmn_err(CE_WARN, "!_PCT conifgured for unsupported "
 335                     "addrspace = %d.", pct_stat->pc_addrspace_id);
 336                 cmn_err(CE_NOTE, "!CPU power management will not function.");
 337                 cpu_acpi_fini(handle);
 338                 return (ESS_RET_NO_PM);
 339         }
 340
 341         if (CPU_ACPI_IS_OBJ_CACHED(handle, CPU_ACPI_PSD_CACHED))
 342                 dependency = CPU_ACPI_PSD(handle).pd_domain;
 343         else {
 344                 mutex_enter(&cpu_lock);
 345                 cp = cpu[CPU->cpu_id];
 346                 dependency = cpuid_get_chipid(cp);
 347                 mutex_exit(&cpu_lock);
 348         }
 349         cpupm_add_cpu2dependency(cpudsp->dip, dependency);
 350
 351         speedstep_state = kmem_zalloc(sizeof (speedstep_state_t), KM_SLEEP);
 352         speedstep_state->ss_state = NULL;
 353         cpudsp->module_state = speedstep_state;
 354
 355         ESSDEBUG(("Instance %d succeeded.\n", ddi_get_instance(cpudsp->dip)));
 356         return (ESS_RET_SUCCESS);
 357 }
 358
 359 /*
 360  * Free resources allocated by speedstep_init().
 361  */
 362 void
 363 speedstep_fini(cpudrv_devstate_t *cpudsp)
 364 {
 365         cpu_acpi_fini(cpudsp->acpi_handle);
 366         kmem_free(cpudsp->module_state, sizeof (speedstep_state_t));
 367 }