usr/src/cmd/fps/fptest/cheetah_sdc.s

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21
  22 /*
  23  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26
  27 #pragma ident   "%Z%%M% %I%     %E% SMI"
  28
  29 #include <sys/asm_linkage.h>
  30 #include "cheetah_sdc.h"
  31
  32 /*
  33  * TARGET_REG and TEMP_REG are macros defined in cheetah_sdc.h
  34  * They are set based on some compile time values
  35  * for eg.
  36  * as -xarch=v8 -P -D_ASM -DLOCALS -DL0 cheetah_sdc.s -o ch_sdc_l0.o
  37  * ch_sdc_l0.o will contain code to test %l0 register
  38  * The functions are named after the register it is testing (l1(), l2() etc)
  39  *
  40  * Algorithm
  41  * Use TARGET_REGISTER
  42  * Do some random stuff on TEMP_REGISTER
  43  * Do some operations on TARGET_REGISTER
  44  * Test
  45  *
  46  * TARGET_REG(unsigned long, unsigned long*, unsigned long*)
  47  * Registers :
  48  * i0 = contains the pattern
  49  * i1 = location for the observed value
  50  * i2 = location for the expected value
  51  */
  52
  53 #ifdef __lint
  54
  55 /*ARGSUSED*/
  56 int
  57 g1(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
  58 {
  59         return (0);
  60 }
  61
  62 /*ARGSUSED*/
  63 int
  64 g2(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
  65 {
  66         return (0);
  67 }
  68
  69 /*ARGSUSED*/
  70 int
  71 g3(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
  72 {
  73         return (0);
  74 }
  75
  76 /*ARGSUSED*/
  77 int
  78 g4(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
  79 {
  80         return (0);
  81 }
  82
  83 /*ARGSUSED*/
  84 int
  85 l0(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
  86 {
  87         return (0);
  88 }
  89
  90 /*ARGSUSED*/
  91 int
  92 l1(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
  93 {
  94         return (0);
  95 }
  96
  97 /*ARGSUSED*/
  98 int
  99 l2(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
 100 {
 101         return (0);
 102 }
 103
 104 /*ARGSUSED*/
 105 int
 106 l3(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
 107 {
 108         return (0);
 109 }
 110
 111 /*ARGSUSED*/
 112 int
 113 l4(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
 114 {
 115         return (0);
 116 }
 117
 118 /*ARGSUSED*/
 119 int
 120 l5(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
 121 {
 122         return (0);
 123 }
 124
 125 /*ARGSUSED*/
 126 int
 127 l6(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
 128 {
 129         return (0);
 130 }
 131
 132 /*ARGSUSED*/
 133 int
 134 l7(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
 135 {
 136         return (0);
 137 }
 138
 139 /*ARGSUSED*/
 140 int
 141 o0(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
 142 {
 143         return (0);
 144 }
 145
 146 /*ARGSUSED*/
 147 int
 148 o1(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
 149 {
 150         return (0);
 151 }
 152
 153 /*ARGSUSED*/
 154 int
 155 o2(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
 156 {
 157         return (0);
 158 }
 159
 160 /*ARGSUSED*/
 161 int
 162 o3(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
 163 {
 164         return (0);
 165 }
 166
 167 /*ARGSUSED*/
 168 int
 169 o4(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
 170 {
 171         return (0);
 172 }
 173
 174 /*ARGSUSED*/
 175 int
 176 o5(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
 177 {
 178         return (0);
 179 }
 180
 181 /*ARGSUSED*/
 182 int
 183 o7(unsigned long arg1, unsigned long *arg2, unsigned long *arg3)
 184 {
 185         return (0);
 186 }
 187
 188 #else /* LINT */
 189
 190         .align 64
 191 ENTRY(TARGET_REG)
 192
 193         save    %sp, -SA(MINFRAME), %sp
 194
 195         setn    0x12345678, %g1, %TARGET_REG    ! initialize the TARGET_REG
 196                                                 ! with a known value
 197
 198 #ifdef  _sparc64
 199         stx     %i0, [%i1]      ! store the pattern to the first location
 200 #else
 201         st      %i0, [%i1]
 202 #endif
 203
 204         nop
 205         nop
 206         nop
 207         nop
 208
 209         nop
 210         nop
 211         nop
 212         nop
 213 #ifdef  _sparc64
 214         stx     %g0, [%i2]
 215         stx     %g0, [%i2]
 216 #else
 217         st      %g0, [%i2]
 218         st      %g0, [%i2]
 219 #endif
 220
 221
 222 !!
 223         clr     %TEMP_REG
 224         clr     %TEMP_REG
 225
 226 #ifdef  _sparc64
 227         st      %g0, [%i2]
 228 #else
 229         st      %g0, [%i2]
 230 #endif
 231         inc     %g0
 232         inc     %g0
 233         or      %TEMP_REG, %g0, %TEMP_REG
 234         or      %TEMP_REG, %g0, %TEMP_REG
 235
 236
 237 !!
 238 #ifdef  _sparc64
 239         ldx     [%i1], %TARGET_REG
 240 #else
 241         ld      [%i1], %TARGET_REG
 242 #endif
 243         mov     %TARGET_REG, %CHECK_REG1        ! CHECK_REG1 should contain the
 244                                                 ! most recent value of TARGET_REG.
 245
 246         mov     %TARGET_REG, %CHECK_REG2        ! CHECK_REG2 should have the same
 247                                                 ! value as CHECK_REG1
 248 ! ==
 249         cmp     %CHECK_REG1, %CHECK_REG2        ! comparison should pass in non-faulty
 250                                                 ! hardware
 251
 252         be      Done
 253         mov     0, %i0
 254
 255 #ifdef  _sparc64
 256         stx     %CHECK_REG1, [%i1]
 257         stx     %CHECK_REG2, [%i2]
 258 #else
 259         st      %CHECK_REG1, [%i1]
 260         st      %CHECK_REG2, [%i2]
 261 #endif
 262
 263         mov     1, %i0
 264
 265 Done :
 266
 267         ret
 268         restore
 269 SET_SIZE(TARGET_REG)
 270
 271 #endif /* LINT */