usr/src/uts/common/sys/pcic_var.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21
  22 /*
  23  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26
  27 /*
  28  * PCIC driver specific data structures
  29  */
  30
  31 #ifndef _PCIC_VAR_H
  32 #define _PCIC_VAR_H
  33
  34 #pragma ident   "%Z%%M% %I%     %E% SMI"
  35
  36 #ifdef  __cplusplus
  37 extern "C" {
  38 #endif
  39
  40 /*
  41  * defines and default values for power management simulation
  42  */
  43 #define PCIC_PM_TIME            3       /* PM timer timeout time in secs */
  44 #define PCIC_PM_DETWIN          6       /* detection window in secs */
  45 #define PCIC_PM_METHOD_TIME     0x0001  /* use time check */
  46 #define PCIC_PM_METHOD_REG      0x0002  /* use reg check */
  47 #define PCIC_PM_DEF_METHOD      0       /* use no methods as default */
  48
  49 #define PCIC_PM_INIT    0x0001  /* init PM handler */
  50 #define PCIC_PM_RUN     0x0002  /* normal PM handler operation */
  51
  52 typedef struct pcic_pm_t {
  53         int             state;  /* state */
  54         uint32_t        ptime;  /* previous time check */
  55         dev_info_t      *dip;   /* dip to pass */
  56 } pcic_pm_t;
  57
  58 /*
  59  * Card insertion/removal processing debounce parameters
  60  */
  61 #define PCIC_REM_DEBOUNCE_CNT   40
  62 #define PCIC_REM_DEBOUNCE_TIME  0x1000  /* in uS */
  63 #define PCIC_DEBOUNCE_OK_CNT    10
  64
  65 /*
  66  * Loop control in pcic_ready_wait
  67  *
  68  * Multiplying PCIC_READY_WAIT_LOOPS * PCIC_READY_WAIT_TIME gives
  69  *      total loop time in mS
  70  */
  71 #define PCIC_READY_WAIT_LOOPS   205     /* count */
  72 #define PCIC_READY_WAIT_TIME    20      /* mS */
  73
  74 typedef struct pcs_memwin {
  75         int                     pcw_status;
  76         uint32_t                pcw_base;
  77         int                     pcw_len;
  78         uint32_t                pcw_speed;
  79         volatile caddr_t        pcw_hostmem;
  80         off_t                   pcw_offset;
  81         ddi_acc_handle_t        pcw_handle;
  82         dev_info_t              *res_dip; /* dip from which mem is allocated */
  83 } pcs_memwin_t;
  84
  85 typedef struct pci_iowin {
  86         int                     pcw_status;
  87         uint32_t                pcw_base;
  88         int                     pcw_len;
  89         uint32_t                pcw_speed;
  90         volatile caddr_t        pcw_hostmem;
  91                                 /* Cirrus Logic specific offset info */
  92         int                     pcw_offset;
  93         ddi_acc_handle_t        pcw_handle;
  94         dev_info_t              *res_dip; /* dip from which io is allocated */
  95 } pcs_iowin_t;
  96
  97 #define PCW_MAPPED      0x0001  /* window is mapped */
  98 #define PCW_ENABLED     0x0002  /* window is enabled */
  99 #define PCW_ATTRIBUTE   0x0004  /* window is in attribute memory */
 100 #define PCW_WP          0x0008  /* window is write protected */
 101 #define PCW_OFFSET      0x0010  /* window uses CL style offset */
 102
 103 typedef
 104 struct pcic_socket {
 105         int     pcs_flags;
 106         uchar_t *pcs_io;        /* I/O address of PCIC controller */
 107         int     pcs_socket;     /* socket to determine register set */
 108         char    pcs_cd_softint_flg;
 109         timeout_id_t pcs_debounce_id;   /* timeout for CD debounce */
 110         ddi_softint_handle_t pcs_cd_softint_hdl; /* Debounce softint id */
 111         struct pcicdev_t *pcs_pcic;
 112         caddr_t pcs_phys;
 113         int     pcs_iobase;
 114         int     pcs_iolen;
 115         caddr_t pcs_confbase;
 116         int     pcs_conflen;
 117         int     pcs_conf_index; /* used to select which cftable entry to use */
 118         int     pcs_irq;
 119         int     pcs_smi;
 120         int     pcs_state;
 121         int     pcs_status;
 122         int     pcs_intmask;
 123         uint32_t pcs_vcc;
 124         uint32_t pcs_vpp1;
 125         uint32_t pcs_vpp2;
 126         union pcic_window {
 127                 pcs_memwin_t mem;
 128                 pcs_iowin_t  io;
 129         }       pcs_windows[PCIC_IOWINDOWS + PCIC_MEMWINDOWS];
 130 } pcic_socket_t;
 131
 132 #define PCS_CARD_PRESENT        0x0001  /* card inserted in socket */
 133 #define PCS_CARD_IDENTIFIED     0x0002  /* card has been identified */
 134 #define PCS_CARD_ENABLED        0x0004  /* card and socket enabled */
 135 #define PCS_CARD_WPS            0x0008  /* write protect ignored */
 136 #define PCS_IRQ_ENABLED         0x0010  /* irq is a mask of values */
 137 #define PCS_CARD_RAM            0x0020  /* ram needs to be mapped */
 138 #define PCS_CARD_IO             0x0040  /* card is I/O type */
 139 #define PCS_CARD_16BIT          0x0080  /* set in 16-bit mode */
 140 #define PCS_SOCKET_IO           0x0100  /* socket is I/O type */
 141 #define PCS_READY               0x0200  /* socket just came ready */
 142 #define PCS_WAITING             0x0400  /* Doing a wait on this socket */
 143 #define PCS_STARTING            0x0800  /* Starting up flag */
 144 #define PCS_CARD_ISCARDBUS      0x1000  /* NJH - 32 bit (CARDBUS) card */
 145 #define PCS_CARD_IS16BIT        0x2000  /* So we can tell if it's OK */
 146 #define PCS_CARD_REMOVED        0x4000  /* Removed but still work to do */
 147 #define PCS_CARD_CBREM          0x8000  /* Cardbus specific work to do */
 148 #define PCS_DEBOUNCING          0x10000  /* Socket in debouncing state */
 149
 150 #define PCIC_MAX_SOCKETS 4      /* 2 per chip up to 2 chips per IO addr */
 151
 152 typedef struct pcic_debounce_state {
 153         int insert_cnt;
 154         int remove_cnt;
 155         int uncertain_cnt;
 156         int prev_status;
 157         int debounce_cnt;
 158         timeout_id_t timeout_id;
 159 } pcic_debounce_state_t;
 160
 161 typedef struct pcicdev_t {
 162         uint32_t                pc_flags;
 163         uint32_t                pc_type;
 164         char                    *pc_chipname;
 165         uint32_t                pc_irqs;        /* the possible IRQ levels */
 166         uint32_t                pc_smi;         /* SMI IRQ */
 167         uint32_t                pc_irq;         /* IO IRQ */
 168         int                     pc_io_type;
 169         int                     pc_intr_mode;   /* which interrupt method */
 170         dev_info_t              *dip;
 171         ddi_idevice_cookie_t    pc_dcookie;     /* Stay compatible w/ PCMCIA */
 172         inthandler_t            *sirq[14];      /* List for each level */
 173         uint16_t                si_actflg;      /* Bit for each active level */
 174         inthandler_t            *irq_top;
 175         inthandler_t            *irq_current;
 176         ddi_intr_handle_t       *pc_pci_intr_hdlp; /* For PCI based adapters */
 177         ddi_iblock_cookie_t     pc_pri;         /* Priority saved for mutexes */
 178         ddi_intr_handle_t       *pc_intr_htblp; /* ISA: interrupt handles */
 179         ddi_softint_handle_t    pc_softint_hdl; /* Softinterrupt handle */
 180         kmutex_t                pc_lock;        /* general register lock */
 181         kmutex_t                intr_lock;      /* protects fields modified */
 182                                                 /* in pcic_intr() */
 183         int                     pc_numsockets;
 184                                 /* used to inform nexus of events */
 185         int                     (*pc_callback)();
 186         int                     pc_cb_arg;
 187         int                     (*pc_ss_bios)();
 188         struct pcic_socket      pc_sockets[PCIC_MAX_SOCKETS];
 189         int                     pc_numpower;
 190         struct power_entry      *pc_power;
 191         timeout_id_t            pc_pmtimer;     /* timeout for simulating PM */
 192         pcic_pm_t               pmt;            /* PM handler structure */
 193         kcondvar_t              pm_cv;          /* CV for suspend/resume sync */
 194         ddi_acc_handle_t        handle;         /* PCIC register handle */
 195         ddi_acc_handle_t        cfg_handle;     /* PCIC config space handle */
 196         uchar_t                 *cfgaddr;       /* config address */
 197         uchar_t                 *ioaddr;        /* PCIC register IO base */
 198         int                     mem_reg_num;    /* memory space reg number */
 199         offset_t                mem_reg_offset;
 200         int                     io_reg_num;     /* IO space reg number */
 201         offset_t                io_reg_offset;
 202         int                     bus_speed;      /* parent bus speed */
 203         uint32_t                pc_timestamp;   /* last time touched */
 204         inthandler_t            *pc_handlers;
 205         int                     pc_lastreg;
 206         uint32_t                pc_base;        /* first possible mem-addr */
 207         uint32_t                pc_bound;       /* bound length */
 208         uint32_t                pc_iobase;      /* first io addr */
 209         uint32_t                pc_iobound;
 210         pcic_debounce_state_t   deb_state[PCIC_MAX_SOCKETS];
 211         int                     pc_softintr_req[PCIC_MAX_SOCKETS];
 212         struct pcic_cd_change_param {
 213                 struct pcicdev_t        *pcic;
 214                 pcic_socket_t           *sockp;
 215                 int                     sn;
 216         }  pcic_cd_change_param[PCIC_MAX_SOCKETS];
 217 } pcicdev_t;
 218
 219
 220
 221 #define PCF_ATTACHED    0x00000001
 222 #define PCF_CALLBACK    0x00000002      /* callback handler registered */
 223 #define PCF_GPI_EJECT   0x00000004      /* GPI signal is eject/insert */
 224 #define PCF_INTRENAB    0x00000008
 225 #define PCF_USE_SMI     0x00000010      /* use the SMI enable */
 226 #define PCF_AUDIO       0x00000020      /* use audio if available */
 227 #define PCF_SUSPENDED   0x00000040      /* driver attached but suspended */
 228 #define PCF_EXTEND_INTR 0x00000080      /* Use Vadem interrupt sharing */
 229 #define PCF_1SOCKET     0x00000100      /* Chip only has one socket  */
 230 #define PCF_33VCAP      0x00000200      /* 3.3 Volt capable and coded */
 231 #define PCF_CBPWRCTL    0x00000400      /* Use cardbus regs for power ctl */
 232 #define PCF_DEBOUNCE    0x00002000      /* Chip has hardware debounce enabled */
 233 #define PCF_VPPX        0x00004000      /* Vpp1 and Vpp2 tied together */
 234 #define PCF_EXTBUFF     0x00008000      /* Chip strapped for external buffers */
 235 #define PCF_PCIBUS      0x00010000      /* this instance on a PCI bus */
 236 #define PCF_NOIO_OFF    0x00020000      /* 0 offset for IO mapping */
 237 #define PCF_MULT_IRQ    0x00040000
 238 #define PCF_IO_REMAP    0x00080000      /* adapter can remap I/O */
 239 #define PCF_CARDBUS     0x00100000      /* Yenta CardBus */
 240 #define PCF_MEM_PAGE    0x00200000      /* all windows same 16M page */
 241
 242 /* newer features */
 243 #define PCF_DMA         0x00400000      /* supports DMA */
 244 #define PCF_ZV          0x00800000      /* supports Zoom Video */
 245
 246 #define PCF_ISA6729     0x01000000      /* 6729 */
 247
 248 /*
 249  * misc flags
 250  */
 251 #define PCIC_FOUND_ADAPTER      0x00000001
 252 #define PCIC_ENABLE_IO          0x00000002
 253 #define PCIC_ENABLE_MEM         0x00000004
 254
 255 #define PCIC_SOFTINT_PRI_VAL    0x04    /* value used while adding softint */
 256
 257 /*
 258  * interrupt modes
 259  * the pcic variants provide a number of interrupt modes.
 260  * e.g. on PCI, we can either use PCI interrupts or ISA interrupts
 261  * but the SPARC version must use PCI interrupts and x86 "depends"
 262  */
 263
 264 #define PCIC_INTR_MODE_ISA      00 /* default- use ISA mode */
 265 #define PCIC_INTR_MODE_PCI      01 /* use pure PCI */
 266 #define PCIC_INTR_MODE_PCI_1    02 /* use pure PCI but share */
 267 #define PCIC_INTR_MODE_PCI_S    03 /* serial PCI interrupts */
 268
 269 #define PCIC_INTR_DEF_PRI       11 /* default IPL level */
 270
 271 /*
 272  * I/O access types
 273  */
 274 #define PCIC_IO_TYPE_82365SL    0 /* uses index/data reg model */
 275 #define PCIC_IO_TYPE_YENTA      1 /* uses the Yenta spec memory model */
 276
 277 /*
 278  * On some PCI busses, the IO and memory resources available to us are
 279  *      available via the last two tuples in the reg property. The
 280  *      following defines are the reg numbers from the end of the reg
 281  *      property, and NOT the reg number itself.
 282  */
 283 #define PCIC_PCI_MEM_REG_OFFSET 2
 284 #define PCIC_PCI_IO_REG_OFFSET  3
 285
 286 /* I/O type 82365SL is default, Yenta is alternative */
 287 #define PCIC_IOTYPE_82365SL     0
 288 #define PCIC_IOTYPE_YENTA       1 /* CardBus memory mode */
 289
 290 /*
 291  * On Yenta cards, the PCI configuration space bridge control register
 292  * must match the interrupt * type we have selected.
 293  */
 294
 295 #define PCIC_CB_BRIDGE_CTL      0x3E
 296 #define PCIC_BCTL_IREQ_ISA      0x80
 297
 298 /*
 299  * On all PCI busses, we get at least two tuples in the reg property. One
 300  *      of the tuples is the config space tuple and the other is the PCIC
 301  *      IO control register space tuple.
 302  */
 303
 304 #define PCIC_PCI_CONFIG_REG_NUM 0
 305 #define PCIC_PCI_CONFIG_REG_OFFSET      0
 306 #define PCIC_PCI_CONFIG_REG_LENGTH      0x100
 307
 308 #define PCIC_PCI_CONTROL_REG_NUM        1
 309 #define PCIC_PCI_CONTROL_REG_OFFSET     0
 310 #define PCIC_PCI_CONTROL_REG_LENGTH     4
 311 #define PCIC_CB_CONTROL_REG_LENGTH      4096 /* CardBus is 4K mem page */
 312
 313 /*
 314  * On ISA/EISA/MCA our reg property must look like this:
 315  *
 316  *      IOreg,0x0,0x8, 0x0,0x0,0x100000, 0x1,0x0,0x1000
 317  *      ^^^^^^^^^^^^^  ^^^^^^^^^^^^^^^^  ^^^^^^^^^^^^^^
 318  *      adapter regs    general memory     general IO
 319  *
 320  * where IOreg specifies the adapter's control registers in
 321  *      IO space.
 322  * The value of PCIC_ISA_IO_REG_OFFSET must be the first
 323  *      component of the third (general IO) register spec.
 324  */
 325 #define PCIC_ISA_IO_REG_OFFSET          1
 326 #define PCIC_ISA_CONTROL_REG_NUM        0
 327 #define PCIC_ISA_CONTROL_REG_OFFSET     0       /* XXX MUST be 0! */
 328 #define PCIC_ISA_CONTROL_REG_LENGTH     2
 329
 330 #define PCIC_ISA_MEM_REG_NUM            1
 331 #define PCIC_ISA_IO_REG_NUM             2
 332
 333 /*
 334  * there are several variants of the 82365 chip from different "clone"
 335  * vendors.  Each has a few differences which may or may not have to be
 336  * handled.  The following defines are used to identify the chip being
 337  * used.  If it can't be determined, then 82365SL is assumed.
 338  *
 339  * The following are ISA/EISA/MCA-R2 adapters
 340  */
 341 #define PCIC_I82365SL           0x00 /* Intel 82365SL */
 342 #define PCIC_TYPE_I82365SL      "i82365SL"
 343 #define PCIC_CL_PD6710          0x01 /* Cirrus Logic CL-PD6710/6720 */
 344 #define PCIC_CL_PD6722          0x05 /* Cirrus Logic CL-PD6722 */
 345 #define PCIC_TYPE_PD6710        "PD6710"
 346 #define PCIC_TYPE_PD6720        "PD6720"
 347 #define PCIC_TYPE_PD6722        "PD6722"
 348 #define PCIC_VADEM              0x02 /* Vadem VG465/365 */
 349 #define PCIC_VADEM_VG469        0x03 /* Vadem VG469 - P&P, etc. */
 350 #define PCIC_VG_465             "VG465"
 351 #define PCIC_VG_365             "VG365"
 352 #define PCIC_VG_468             "VG468"
 353 #define PCIC_VG_469             "VG469"
 354 #define PCIC_RICOH              0x04
 355 #define PCIC_TYPE_RF5C296       "RF5C296"
 356 #define PCIC_TYPE_RF5C396       "RF5C396"
 357
 358 /* PCI adapters are known by 32-bit value of vendor+device id */
 359 #define PCI_ID(vend, dev)       ((uint32_t)(((uint32_t)(vend) << 16) | (dev)))
 360
 361 /*
 362  * The following are PCI-R2 adapters
 363  * The Cirrus Logic PCI adapters typically have their IRQ3 line
 364  *      routed to the PCI INT A# line.
 365  */
 366 #define PCIC_CL_VENDORID        0x1013
 367 #define PCIC_PD6729_DEVID       0x1100
 368 #define PCIC_TYPE_PD6729        "PD6729"
 369 #define PCIC_CL_PD6729          PCI_ID(PCIC_CL_VENDORID, PCIC_PD6729_DEVID)
 370 #define PCIC_PD6729_INTA_ROUTE  0x03
 371
 372 #define PCIC_TYPE_PD6730        "PD6730"
 373 #define PCIC_PD6730_DEVID       0x1101
 374 #define PCIC_CL_PD6730          PCI_ID(PCIC_CL_VENDORID, PCIC_PD6730_DEVID)
 375 #define PCIC_PD6730_INTA_ROUTE  0x09
 376
 377 #define PCIC_TYPE_PD6832        "PD6832"
 378 #define PCIC_PD6832_DEVID       0x1110
 379 #define PCIC_CL_PD6832          PCI_ID(PCIC_CL_VENDORID, PCIC_PD6832_DEVID)
 380
 381 /* Intel i82092AA controller */
 382
 383 #define PCIC_INTEL_VENDORID     0x8086
 384 #define PCIC_TYPE_i82092        "i82092"
 385 #define PCIC_i82092_DEVID       0x1221
 386 #define PCIC_INTEL_i82092       PCI_ID(PCIC_INTEL_VENDORID, \
 387                                         PCIC_i82092_DEVID)
 388 #define PCIC_i82092_INTA_ROUTE  0x0     /* XXX ? what is it really ? XXX */
 389
 390 /* Texas Instruments */
 391
 392 #define PCIC_TI_VENDORID        0x104C
 393 #define PCIC_PCI1050_DEVID      0xAC10
 394 #define PCIC_PCI1130_DEVID      0xAC12
 395 #define PCIC_PCI1031_DEVID      0xAC13 /* R2 only with Yenta IF */
 396 #define PCIC_PCI1131_DEVID      0xAC15
 397 #define PCIC_PCI1250_DEVID      0xAC16
 398 #define PCIC_PCI1221_DEVID      0xAC19
 399 #define PCIC_PCI1225_DEVID      0xAC1C
 400 #define PCIC_PCI1220_DEVID      0xAC17
 401 #define PCIC_PCI1260_DEVID      0xAC18
 402 #define PCIC_PCI1210_DEVID      0xAC1A
 403 #define PCIC_PCI1450_DEVID      0xAC1B
 404 #define PCIC_PCI1251_DEVID      0xAC1D
 405 #define PCIC_PCI1211_DEVID      0xAC1E
 406 #define PCIC_PCI1251B_DEVID     0xAC1F
 407 #define PCIC_PCI1260B_DEVID     0xAC30
 408 #define PCIC_PCI4450_DEVID      0xAC40
 409 #define PCIC_PCI4410_DEVID      0xAC41
 410 #define PCIC_PCI4451_DEVID      0xAC42
 411 #define PCIC_PCI4510_DEVID      0xAC44
 412 #define PCIC_PCI1410_DEVID      0xAC50
 413 #define PCIC_PCI1420_DEVID      0xAC51
 414 #define PCIC_PCI1451_DEVID      0xAC52
 415 #define PCIC_PCI1421_DEVID      0xAC53
 416 #define PCIC_PCI1520_DEVID      0xAC55
 417 #define PCIC_PCI1510_DEVID      0xAC56
 418
 419 #define PCIC_TI_PCI1130         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1130_DEVID)
 420 #define PCIC_TYPE_PCI1130       "PCI1130"
 421 #define PCIC_TI_PCI1031         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1031_DEVID)
 422 #define PCIC_TYPE_PCI1031       "PCI1031"
 423 #define PCIC_TI_PCI1131         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1131_DEVID)
 424 #define PCIC_TYPE_PCI1131       "PCI1131"
 425 #define PCIC_TI_PCI1250         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1250_DEVID)
 426 #define PCIC_TYPE_PCI1250       "PCI1250"
 427 #define PCIC_TI_PCI1050         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1050_DEVID)
 428 #define PCIC_TYPE_PCI1050       "PCI1050"
 429 #define PCIC_TI_PCI1221         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1221_DEVID)
 430 #define PCIC_TYPE_PCI1221       "PCI1221"
 431 #define PCIC_TI_PCI1225         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1225_DEVID)
 432 #define PCIC_TYPE_PCI1225       "PCI1225"
 433 #define PCIC_TI_PCI1220         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1220_DEVID)
 434 #define PCIC_TYPE_PCI1220       "PCI1220"
 435 #define PCIC_TI_PCI1260         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1260_DEVID)
 436 #define PCIC_TYPE_PCI1260       "PCI1260"
 437 #define PCIC_TI_PCI1210         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1210_DEVID)
 438 #define PCIC_TYPE_PCI1210       "PCI1210"
 439 #define PCIC_TI_PCI1450         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1450_DEVID)
 440 #define PCIC_TYPE_PCI1450       "PCI1450"
 441 #define PCIC_TI_PCI1251         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1251_DEVID)
 442 #define PCIC_TYPE_PCI1251       "PCI1251"
 443 #define PCIC_TI_PCI1211         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1211_DEVID)
 444 #define PCIC_TYPE_PCI1211       "PCI1211"
 445 #define PCIC_TI_PCI1251B        PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1251B_DEVID)
 446 #define PCIC_TYPE_PCI1251B      "PCI1251B"
 447 #define PCIC_TI_PCI1260B        PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1260B_DEVID)
 448 #define PCIC_TYPE_PCI1260B      "PCI1260B"
 449 #define PCIC_TI_PCI4450         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI4450_DEVID)
 450 #define PCIC_TYPE_PCI4450       "PCI4450"
 451 #define PCIC_TI_PCI4410         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI4410_DEVID)
 452 #define PCIC_TYPE_PCI4410       "PCI4410"
 453 #define PCIC_TI_PCI4451         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI4451_DEVID)
 454 #define PCIC_TYPE_PCI4451       "PCI4451"
 455 #define PCIC_TI_PCI4510         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI4510_DEVID)
 456 #define PCIC_TYPE_PCI4510       "PCI4510"
 457 #define PCIC_TI_PCI1410         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1410_DEVID)
 458 #define PCIC_TYPE_PCI1410       "PCI1410"
 459 #define PCIC_TI_PCI1420         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1420_DEVID)
 460 #define PCIC_TYPE_PCI1420       "PCI1420"
 461 #define PCIC_TI_PCI1451         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1451_DEVID)
 462 #define PCIC_TYPE_PCI1451       "PCI1451"
 463 #define PCIC_TI_PCI1421         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1421_DEVID)
 464 #define PCIC_TYPE_PCI1421       "PCI1421"
 465 #define PCIC_TI_PCI1510         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1510_DEVID)
 466 #define PCIC_TYPE_PCI1510       "PCI1510"
 467 #define PCIC_TI_PCI1520         PCI_ID(PCIC_TI_VENDORID, PCIC_PCI1520_DEVID)
 468 #define PCIC_TYPE_PCI1520       "PCI1520"
 469 #define PCIC_TI_VENDOR          PCI_ID(PCIC_TI_VENDORID, 0x0000)
 470 #define PCIC_TYPE_TI            "PCIC_TI"
 471
 472 /* O2 Micro */
 473 #define PCIC_O2_VENDORID        0x1217
 474 #define PCIC_OZ6912_DEVID       0x6972
 475 #define PCIC_O2_OZ6912          PCI_ID(PCIC_O2_VENDORID, PCIC_OZ6912_DEVID)
 476 #define PCIC_TYPE_OZ6912        "OZ6912"
 477 #define PCIC_O2MICRO_VENDOR     PCI_ID(PCIC_O2_VENDORID, 0x0000)
 478 #define PCIC_TYPE_O2MICRO       "O2Micro"
 479
 480 /* ENE */
 481 #define PCIC_ENE_VENDORID       0x1524
 482 #define PCIC_ENE1410_DEVID      0x1410
 483 #define PCIC_ENE_1410           PCI_ID(PCIC_ENE_VENDORID, PCIC_ENE1410_DEVID)
 484 #define PCIC_TYPE_1410          "ENE1410"
 485 #define PCIC_ENE1420_DEVID      0x1420
 486 #define PCIC_ENE_1420           PCI_ID(PCIC_ENE_VENDORID, PCIC_ENE1420_DEVID)
 487 #define PCIC_TYPE_1420          "ENE1420"
 488
 489 /* SMC 34C90 */
 490 #define PCIC_SMC_VENDORID       0x10B3
 491 #define PCIC_SMC34C90_DEVID     0xB106
 492 #define PCIC_SMC_34C90          PCI_ID(PCIC_SMC_VENDORID, PCIC_SMC34C90_DEVID)
 493 #define PCIC_TYPE_34C90         "SMC34c90"
 494
 495 /* Ricoh RL5CXXX */
 496 #define PCIC_RICOH_VENDORID     0x1180
 497 #define PCIC_RL5C466_DEVID      0x0466
 498 #define PCIC_RL5C475_DEVID      0x0475
 499 #define PCIC_RL5C476_DEVID      0x0476
 500 #define PCIC_RL5C477_DEVID      0x0477
 501 #define PCIC_RL5C478_DEVID      0x0478
 502 #define PCIC_RICOH_RL5C466      PCI_ID(PCIC_RICOH_VENDORID, PCIC_RL5C466_DEVID)
 503 #define PCIC_RICOH_RL5C475      PCI_ID(PCIC_RICOH_VENDORID, PCIC_RL5C475_DEVID)
 504 #define PCIC_RICOH_RL5C476      PCI_ID(PCIC_RICOH_VENDORID, PCIC_RL5C476_DEVID)
 505 #define PCIC_RICOH_RL5C477      PCI_ID(PCIC_RICOH_VENDORID, PCIC_RL5C477_DEVID)
 506 #define PCIC_RICOH_RL5C478      PCI_ID(PCIC_RICOH_VENDORID, PCIC_RL5C478_DEVID)
 507 #define PCIC_TYPE_RL5C466               "RL5C466"
 508 #define PCIC_TYPE_RL5C475               "RL5C475"
 509 #define PCIC_TYPE_RL5C476               "RL5C476"
 510 #define PCIC_TYPE_RL5C477               "RL5C477"
 511 #define PCIC_TYPE_RL5C478               "RL5C478"
 512 #define PCIC_RICOH_VENDOR       PCI_ID(PCIC_RICOH_VENDORID, 0x0000)
 513 #define PCIC_TYPE_RICOH         "Ricoh"
 514
 515 /* Toshiba */
 516 #define PCIC_TOSHIBA_VENDORID   0x1179
 517 #define PCIC_TOPIC95_DEVID      0x0603
 518 #define PCIC_TOSHIBA_TOPIC95    PCI_ID(PCIC_TOSHIBA_VENDORID, \
 519                                         PCIC_TOPIC95_DEVID)
 520 #define PCIC_TYPE_TOPIC95       "ToPIC95"
 521 #define PCIC_TOPIC100_DEVID     0x0617
 522 #define PCIC_TOSHIBA_TOPIC100   PCI_ID(PCIC_TOSHIBA_VENDORID, \
 523                                         PCIC_TOPIC100_DEVID)
 524 #define PCIC_TYPE_TOPIC100      "ToPIC100"
 525 #define PCIC_TOSHIBA_VENDOR     PCI_ID(PCIC_TOSHIBA_VENDORID, 0x0000)
 526 #define PCIC_TYPE_TOSHIBA       "Toshiba"
 527
 528 /* Generic Yenta compliant chip */
 529 #define PCIC_TYPE_YENTA         "Yenta"
 530
 531 /* Yenta-compliant vcc register, bits */
 532 #define PCIC_PRESENT_STATE_REG  0x8
 533 #define PCIC_VCC_MASK           0xc00
 534 #define PCIC_VCC_3VCARD         0x800
 535 #define PCIC_VCC_5VCARD         0x400
 536
 537 #define PCIC_16BIT_CARD         0x010           /* 16 bit card */
 538 #define PCIC_CB_CARD            0x020           /* cardbus card */
 539 #define PCIC_CINT_IREQ          0x040           /* Interrupt present */
 540 #define PCIC_NOT_A_CARD         0x080           /* Not a card */
 541 #define PCIC_DATA_LOST          0x100           /* Data lost */
 542 #define PCIC_BAD_VCC_REQ        0x200           /* Bad Vcc request */
 543
 544
 545 /* TI Multi Function Terminal selection (MFUNC0 selected as INTA) */
 546 #define PCIC_TI_MFUNC_SEL       0x22
 547
 548 #define PCICPROP_CTL            "controller"
 549
 550 #define PCIC_REV_LEVEL_LOW      0x02
 551 #define PCIC_REV_LEVEL_HI       0x04
 552 #define PCIC_REV_C              0x04
 553 #define PCIC_REV_MASK           0x0f
 554
 555 #define PCIC_ID_NAME            "pcic"
 556 #define PCIC_DEV_NAME           "pcic"
 557
 558 #ifndef DEVI_PCI_NEXNAME
 559 #define DEVI_PCI_NEXNAME        "pci"
 560 #endif
 561
 562 #ifndef DEVI_PCIEX_NEXNAME
 563 #define DEVI_PCIEX_NEXNAME      "pciex"
 564 #endif
 565
 566 /* PCI Class Code stuff */
 567 #define PCIC_PCI_CLASS(cls, subclass)   (((cls) << 16) | ((subclass) << 8))
 568 #define PCIC_PCI_PCMCIA PCIC_PCI_CLASS(PCI_CLASS_BRIDGE, PCI_BRIDGE_PCMCIA)
 569 #define PCIC_PCI_CARDBUS PCIC_PCI_CLASS(PCI_CLASS_BRIDGE, PCI_BRIDGE_CARDBUS)
 570
 571 #define PCIC_MEM_AM     0       /* Attribute Memory */
 572 #define PCIC_MEM_CM     1       /* Common Memory */
 573
 574 #define PCS_SUBTYPE_UNKNOWN     0x00 /* haven't processed this yet */
 575 #define PCS_SUBTYPE_MEMORY      0x01 /* normal memory access */
 576 #define PCS_SUBTYPE_FAT         0x02 /* DOS floppy (FAT) file system */
 577
 578 /*
 579  * For speed calculation, assume a SYSCLK rate of 8.33MHz
 580  *      unless our parent tells us otherwise. 8.33MHz is a
 581  *      reasonable default for an ISA bus.
 582  */
 583 #define PCIC_ISA_DEF_SYSCLK     8       /* MHZ */
 584 #define PCIC_PCI_DEF_SYSCLK     33      /* MHZ */
 585 #define PCIC_PCI_25MHZ          25
 586 #define mhztons(c)              (1000000 / (uint32_t)((c) * 1000))
 587 #define PCIC_SYSCLK_25MHZ       25 * 1000 * 1000
 588 #define PCIC_SYSCLK_33MHZ       33 * 1000 * 1000
 589
 590 /* simplify the callback so it looks like straight function call */
 591 #define PC_CALLBACK     (*pcic->pc_callback)
 592
 593 /* hardware event capabilities -- needs sservice.h */
 594 #define PCIC_DEFAULT_INT_CAPS   (SBM_BVD1|SBM_BVD2|SBM_RDYBSY|SBM_CD)
 595 #define PCIC_DEFAULT_RPT_CAPS   (PCIC_DEFAULT_INT_CAPS|SBM_WP)
 596 /* note that we don't support indicators via the PCIC */
 597 #define PCIC_DEFAULT_CTL_CAPS   (0)
 598
 599 /* format of pcic "ranges" property */
 600 typedef struct pcic_ranges {
 601         uint32_t pcic_range_caddrhi;
 602         uint32_t pcic_range_caddrlo;
 603         uint32_t pcic_range_paddrhi;
 604         uint32_t pcic_range_paddrmid;
 605         uint32_t pcic_range_paddrlo;
 606         uint32_t pcic_range_size;
 607 } pcic_ranges_t;
 608
 609 /* debug stuff */
 610 #if defined(DEBUG)
 611 #define PCIC_DEBUG
 612 #endif
 613
 614 #ifdef  __cplusplus
 615 }
 616 #endif
 617
 618 #endif  /* _PCIC_VAR_H */