usr/src/uts/common/sys/miiregs.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  */
  25
  26 /*
  27  * Definitions for MII registers from 802.3u and vendor documentation
  28  */
  29
  30 #ifndef _SYS_MIIREGS_H
  31 #define _SYS_MIIREGS_H
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 /* Register addresses: Section 22.2.4 */
  38 #define MII_CONTROL             0
  39 #define MII_STATUS              1
  40 #define MII_PHYIDH              2
  41 #define MII_PHYIDL              3
  42 #define MII_AN_ADVERT           4       /* Auto negotiation advertisement. */
  43 #define MII_AN_LPABLE           5       /* Auto neg. Link Partner Ability  */
  44 #define MII_AN_EXPANSION        6       /* Auto neg. Expansion.            */
  45 #define MII_AN_NXTPGXMIT        7       /* Auto neg. Next Page Transmit    */
  46 #define MII_AN_NXTPGLP          8       /* Link Part. Augo neg. Next Page  */
  47 #define MII_MSCONTROL           9       /* 100Base-T2 and 1000 BaseT Ctrl. */
  48 #define MII_MSSTATUS            10      /* 100Base-T2 and 1000 BaseT Stat. */
  49 #define MII_EXTSTATUS           15      /* Extended status registers       */
  50 #define MII_VENDOR(x)           (16+(x)) /* Vendor specific                */
  51
  52 /* Control register: 22.2.4.1, 28.2.4.1.1 */
  53 #define MII_CONTROL_RESET       (1<<15)
  54 #define MII_CONTROL_LOOPBACK    (1<<14)
  55 #define MII_CONTROL_100MB       (1<<13)
  56 #define MII_CONTROL_ANE         (1<<12)
  57 #define MII_CONTROL_PWRDN       (1<<11)
  58 #define MII_CONTROL_ISOLATE     (1<<10)
  59 #define MII_CONTROL_RSAN        (1<<9)
  60 #define MII_CONTROL_FDUPLEX     (1<<8)
  61 #define MII_CONTROL_COLTST      (1<<7)
  62 #define MII_CONTROL_1GB         (1<<6)
  63 #define MII_CONTROL_UNIDIR      (1<<5)
  64
  65 /* Status register: 22.2.4.2, 28.2.4.1.2 */
  66 #define MII_STATUS_100_BASE_T4  (1<<15)
  67 #define MII_STATUS_100_BASEX_FD (1<<14)
  68 #define MII_STATUS_100_BASEX    (1<<13)
  69 #define MII_STATUS_10_FD        (1<<12)
  70 #define MII_STATUS_10           (1<<11)
  71 #define MII_STATUS_100T2_FD     (1<<10)
  72 #define MII_STATUS_100T2        (1<<9)
  73 #define MII_STATUS_EXTSTAT      (1<<8)
  74 #define MII_STATUS_UNIDIR       (1<<7)
  75 #define MII_STATUS_MFPRMBLSUPR  (1<<6)
  76 #define MII_STATUS_ANDONE       (1<<5)
  77 #define MII_STATUS_REMFAULT     (1<<4)
  78 #define MII_STATUS_CANAUTONEG   (1<<3)
  79 #define MII_STATUS_LINKUP       (1<<2)
  80 #define MII_STATUS_JABBERING    (1<<1)
  81 #define MII_STATUS_EXTENDED     (1<<0)
  82
  83 /* Advertisement/Partner ability registers: 28.2.4.1.3/4 */
  84 #define MII_AN_ADVERT_NP        (1<<15)
  85 #define MII_AN_ADVERT_ACK       (1<<14)
  86 #define MII_AN_ADVERT_REMFAULT  (1<<13)
  87 #define MII_AN_ADVERT_EXTNP     (1<<12)
  88 #define MII_AN_ADVERT_TECHABLE  (0x7f<<5)
  89 #define MII_AN_ADVERT_SELECTOR  (0x1f)
  90 #define MII_AN_SELECTOR_8023    0x0001
  91
  92 /* Technology field bits (above). From Annex 28B */
  93 #define MII_ABILITY_10BASE_T    (1<<5)
  94 #define MII_ABILITY_10BASE_T_FD (1<<6)
  95 #define MII_ABILITY_100BASE_TX  (1<<7)
  96 #define MII_ABILITY_100BASE_TX_FD (1<<8)
  97 #define MII_ABILITY_100BASE_T4  (1<<9)
  98 #define MII_ABILITY_PAUSE       (1<<10)
  99 #define MII_ABILITY_ASMPAUSE    (1<<11)
 100 /* Override fields for 1000 Base-X: 37.2.5.1.3 */
 101 #define MII_ABILITY_X_FD        (1<<5)
 102 #define MII_ABILITY_X_HD        (1<<6)
 103 #define MII_ABILITY_X_PAUSE     (1<<7)
 104 #define MII_ABILITY_X_ASMPAUSE  (1<<8)
 105 /* Override fields for 100 Base T2: 32.5.4.2 */
 106 #define MII_ABILITY_T2_FD       (1<<11)
 107 #define MII_ABILITY_T2_HD       (1<<10)
 108
 109 /* Expansion register 28.2.4.1.5 */
 110 #define MII_AN_EXP_PARFAULT     (1<<4)  /* fault detected                 */
 111 #define MII_AN_EXP_LPCANNXTP    (1<<3)  /* Link partner is Next Page able */
 112 #define MII_AN_EXP_CANNXTPP     (1<<2)  /* Local is next page able        */
 113 #define MII_AN_EXP_PAGERCVD     (1<<1)  /* A new page has been recvd.     */
 114 #define MII_AN_EXP_LPCANAN      (1<<0)  /* LP can auto-negotiate          */
 115
 116 /* Master/Slave control: 40.5.1.1 */
 117 #define MII_MSCONTROL_TEST_MASK (3<<13)
 118 #define MII_MSCONTROL_MANUAL    (1<<12) /* manual master/slave control */
 119 #define MII_MSCONTROL_MASTER    (1<<11)
 120 #define MII_MSCONTROL_MULTIPORT (1<<10) /* DCE, default 0 for NICs */
 121 #define MII_MSCONTROL_1000T_FD  (1<<9)
 122 #define MII_MSCONTROL_1000T     (1<<8)
 123
 124 /* Master/Slave status: 40.5.1.1 */
 125 #define MII_MSSTATUS_FAULT      (1<<15) /* Master/slave config fault */
 126 #define MII_MSSTATUS_MASTER     (1<<14) /* Master/slave config result */
 127 #define MII_MSSTATUS_RXSTAT     (1<<13)
 128 #define MII_MSSTATUS_REMRXSTAT  (1<<12)
 129 #define MII_MSSTATUS_LP1000T_FD (1<<11)
 130 #define MII_MSSTATUS_LP1000T    (1<<10)
 131 #define MII_MSSTATUS_IDLE_ERR   (0xff)
 132
 133 /* Extended status: 22.2.4.4 */
 134 #define MII_EXTSTATUS_1000X_FD  (1<<15)
 135 #define MII_EXTSTATUS_1000X     (1<<14)
 136 #define MII_EXTSTATUS_1000T_FD  (1<<13)
 137 #define MII_EXTSTATUS_1000T     (1<<12)
 138
 139 /*
 140  * Truncated OUIs as found in the PHY Identifier ( 22.2.4.3.1 ),
 141  * and known models (and their registers) from those manufacturers
 142  */
 143
 144 #define MII_PHY_MFG(x)          (((x) >> 10) & 0x3fffff) /* 22 bits, 10-31 */
 145 #define MII_PHY_MODEL(x)        (((x) >> 4) & 0x3f)      /* 6 bits,4-9     */
 146 #define MII_PHY_REV(x)          ((x) & 0xf)              /* 4 bits, 0-3    */
 147
 148 /*
 149  * PHY manufacturer OUIs
 150  */
 151 #define MII_OUI_ALTIMA                  0x000895
 152 #define MII_OUI_AMD                     0x00001a
 153 #define MII_OUI_AMD_2                   0x000058
 154 #define MII_OUI_ATTANSIC                0x001374
 155 #define MII_OUI_BROADCOM                0x001018
 156 #define MII_OUI_BROADCOM_2              0x000818
 157 #define MII_OUI_CICADA                  0x0003f1
 158 #define MII_OUI_CICADA_2                0x00c08f
 159 #define MII_OUI_DAVICOM                 0x00606e
 160 #define MII_OUI_DAVICOM_2               0x000676
 161 #define MII_OUI_ICS                     0x00057d
 162 #define MII_OUI_ICPLUS                  0x0090c3
 163 #define MII_OUI_INTEL                   0x00aa00
 164 #define MII_OUI_INTEL_2                 0x001f00
 165 #define MII_OUI_LUCENT                  0x00601d
 166 #define MII_OUI_MARVELL                 0x005043
 167 #define MII_OUI_NATIONAL_SEMI           0x080017
 168 #define MII_OUI_NATIONAL_SEMI_2         0x1000e8
 169 #define MII_OUI_QUALITY_SEMI            0x006051
 170 #define MII_OUI_QUALITY_SEMI_2          0x00608a
 171
 172 /*
 173  * PHY models
 174  */
 175 #define MII_MODEL_ALTIMA_AC101                  0x21    /* also Am79C874 */
 176 #define MII_MODEL_ALTIMA_AC101L                 0x12
 177 #define MII_MODEL_ALTIMA_AM79C875               0x14
 178
 179 #define MII_MODEL_AMD_AM79C901                  0x37
 180 #define MII_MODEL_AMD_AM79C972                  0x01
 181 #define MII_MODEL_AMD_AM79C973                  0x36
 182
 183 #define MII_MODEL_CICADA_CS8201                 0x01
 184 #define MII_MODEL_CICADA_CS8201A                0x20
 185 #define MII_MODEL_CICADA_CS8201B                0x21
 186
 187 #define MII_MODEL_DAVICOM_DM9101                0x00
 188 #define MII_MODEL_DAVICOM_DM9102                0x04
 189 #define MII_MODEL_DAVICOM_DM9161                0x08
 190
 191 #define MII_MODEL_ICPLUS_IP101                  0x05
 192
 193 #define MII_MODEL_ICS_ICS1889                   0x01
 194 #define MII_MODEL_ICS_ICS1890                   0x02
 195 #define MII_MODEL_ICS_ICS1892                   0x03
 196 #define MII_MODEL_ICS_ICS1893                   0x04
 197
 198 #define MII_MODEL_INTEL_82553_CSTEP             0x35
 199 #define MII_MODEL_INTEL_82555                   0x15
 200 #define MII_MODEL_INTEL_82562_EH                0x33
 201 #define MII_MODEL_INTEL_82562_EM                0x31
 202 #define MII_MODEL_INTEL_82562_ET                0x32
 203
 204 #define MII_MODEL_LUCENT_LU6612                 0x0c
 205
 206 #define MII_MODEL_MARVELL_88E1000               0x00
 207 #define MII_MODEL_MARVELL_88E1011               0x02
 208 #define MII_MODEL_MARVELL_88E1000_2             0x03
 209 #define MII_MODEL_MARVELL_88E1000S              0x04
 210 #define MII_MODEL_MARVELL_88E1000_3             0x05
 211 #define MII_MODEL_MARVELL_88E3082               0x08    /* 10/100 */
 212 #define MII_MODEL_MARVELL_88E1112               0x09
 213 #define MII_MODEL_MARVELL_88E1149               0x0b
 214 #define MII_MODEL_MARVELL_88E1111               0x0c
 215 #define MII_MODEL_MARVELL_88E1116               0x21
 216 #define MII_MODEL_MARVELL_88E1118               0x22
 217 #define MII_MODEL_MARVELL_88E1116R              0x24
 218 #define MII_MODEL_MARVELL_88E3016               0x26    /* 10/100 */
 219
 220 #define MII_MODEL_NATIONAL_SEMI_DP83840         0x00
 221 #define MII_MODEL_NATIONAL_SEMI_DP83843         0x01
 222 #define MII_MODEL_NATIONAL_SEMI_DP83815         0x02
 223 #define MII_MODEL_NATIONAL_SEMI_DP83847         0x03
 224 #define MII_MODEL_NATIONAL_SEMI_DP83891         0x05
 225 #define MII_MODEL_NATIONAL_SEMI_DP83861         0x06
 226
 227 #define MII_MODEL_QUALITY_SEMI_QS6612           0x00
 228
 229 #ifdef __cplusplus
 230 }
 231 #endif
 232
 233 #endif /* _SYS_MIIREGS_H */