usr/src/uts/sparc/sys/cmpregs.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  */
  25
  26 #ifndef _CMPREGS_H
  27 #define _CMPREGS_H
  28
  29 #pragma ident   "%Z%%M% %I%     %E% SMI"
  30
  31 #ifdef  __cplusplus
  32 extern "C" {
  33 #endif
  34
  35 #define ASI_CMP_SHARED          0x41    /* shared CMP registers */
  36 #define ASI_CMP_PER_CORE        0x63    /* core-local CMP registers */
  37
  38 /*
  39  * Core ID Register
  40  *
  41  *   |-----------------------|
  42  *   |MAX_CORE_ID|---|CORE_ID|
  43  *   |-----------------------|
  44  *    21       16     5     0
  45  */
  46 #define ASI_CORE_ID             0x10    /* ASI 0x63, VA 0x10 */
  47 #define COREID_MASK             0x3f
  48
  49
  50 /*
  51  * Error Steering Register
  52  *
  53  *   |-------|
  54  *   |CORE_ID|
  55  *   |-------|
  56  *    5     0
  57  */
  58 #define ASI_CMP_ERROR_STEERING  0x40    /* ASI 0x41, VA 0x40 */
  59
  60 /*
  61  * Core Running
  62  *
  63  *   |------------------------------|
  64  *   |       |core running (status) |
  65  *   |------------------------------|
  66  *            1                    0
  67  */
  68 #define ASI_CORE_RUNNING_RW     0x50    /* ASI 0x41, VA 0x50 */
  69 #define ASI_CORE_RUNNING_STATUS 0x58    /* ASI 0x41, VA 0x58 */
  70 #define ASI_CORE_RUNNING_W1S    0x60    /* ASI 0x41, VA 0x60 */
  71 #define ASI_CORE_RUNNING_W1C    0x68    /* ASI 0x41, VA 0x68 */
  72
  73 #ifdef  __cplusplus
  74 }
  75 #endif
  76
  77 #endif /* _CMPREGS_H */