usr/src/uts/common/sys/vgareg.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License, Version 1.0 only
   6  * (the "License").  You may not use this file except in compliance
   7  * with the License.
   8  *
   9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  10  * or http://www.opensolaris.org/os/licensing.
  11  * See the License for the specific language governing permissions
  12  * and limitations under the License.
  13  *
  14  * When distributing Covered Code, include this CDDL HEADER in each
  15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  16  * If applicable, add the following below this CDDL HEADER, with the
  17  * fields enclosed by brackets "[]" replaced with your own identifying
  18  * information: Portions Copyright [yyyy] [name of copyright owner]
  19  *
  20  * CDDL HEADER END
  21  */
  22 /*
  23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26
  27 #ifndef _SYS_VGAREG_H
  28 #define _SYS_VGAREG_H
  29
  30 #ifdef  __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 #define VGA_REG_ADDR    0x3c0
  35 #define VGA_REG_SIZE    0x20
  36
  37 #define VGA_MEM_ADDR    0xa0000
  38 #define VGA_MEM_SIZE    0x20000
  39
  40 #define VGA_TEXT_COLS   80
  41 #define VGA_TEXT_ROWS   25
  42
  43 /*
  44  * VGA frame buffer hardware definitions.
  45  */
  46
  47 #define VGA8_DEPTH              8
  48 #define VGA8_CMAP_ENTRIES       256
  49 #define VGA_TEXT_CMAP_ENTRIES   64
  50
  51 /*
  52  * General VGA registers
  53  * These are relative to their register set, which
  54  * the 3c0-3df set.
  55  */
  56 #define VGA_ATR_AD      0x00
  57 #define VGA_ATR_DATA    0x01
  58 #define VGA_MISC_W      0x02
  59 #define VGA_SEQ_ADR     0x04
  60 #define VGA_SEQ_DATA    0x05
  61 #define VGA_DAC_BASE    0x06
  62 #define VGA_DAC_AD_MK   0x06
  63 #define VGA_DAC_RD_AD   0x07
  64 #define VGA_DAC_STS     0x07
  65 #define VGA_DAC_WR_AD   0x08
  66 #define VGA_DAC_DATA    0x09
  67 #define VGA_MISC_R      0x0c
  68 #define VGA_GRC_ADR     0x0e
  69 #define VGA_GRC_DATA    0x0f
  70 #define VGA_CRTC_ADR    0x14
  71 #define VGA_CRTC_DATA   0x15
  72 #define CGA_STAT        0x1a
  73
  74 /*
  75  * Attribute controller index bits
  76  */
  77 #define VGA_ATR_ENB_PLT 0x20
  78
  79 /*
  80  * Miscellaneous output bits
  81  */
  82 #define VGA_MISC_IOA_SEL        0x01
  83 #define VGA_MISC_ENB_RAM        0x02
  84 #define VGA_MISC_VCLK           0x0c
  85 #define         VGA_MISC_VCLK0          0x00
  86 #define         VGA_MISC_VCLK1          0x04
  87 #define         VGA_MISC_VCLK2          0x08
  88 #define         VGA_MISC_VCLK3          0x0c
  89 #define VGA_MISC_PGSL           0x20
  90 #define VGA_MISC_HSP            0x40
  91 #define VGA_MISC_VSP            0x80
  92 #define VGA_MISC_IS1_VR         0x08    /* Vertical Retrace */
  93 #define VGA_MISC_IS1_DD         0x01    /* Display Disabled */
  94
  95 /*
  96  * CRT Controller registers
  97  */
  98 #define VGA_CRTC_H_TOTAL        0x00
  99 #define VGA_CRTC_H_D_END        0x01
 100 #define VGA_CRTC_S_H_BLNK       0x02
 101 #define VGA_CRTC_E_H_BLNK       0x03
 102 #define         VGA_CRTC_E_H_BLNK_PUT_EHB(n) \
 103                         ((n)&0x1f)
 104 #define VGA_CRTC_S_H_SY_P       0x04
 105 #define VGA_CRTC_E_H_SY_P       0x05
 106 #define         VGA_CRTC_E_H_SY_P_HOR_SKW_SHIFT 5
 107 #define         VGA_CRTC_E_H_SY_P_HOR_SKW       0x60
 108 #define         VGA_CRTC_E_H_SY_P_EHB5          7
 109 #define         VGA_CRTC_E_H_SY_P_PUT_HOR_SKW(skew) \
 110                         ((skew)<<VGA_CRTC_E_H_SY_P_HOR_SKW_SHIFT)
 111 #define         VGA_CRTC_E_H_SY_P_PUT_EHB(n) \
 112                         ((((n)>>5)&1)<<VGA_CRTC_E_H_SY_P_EHB5)
 113 #define         VGA_CRTC_E_H_SY_P_PUT_EHS(n) \
 114                         ((n)&0x1f)
 115 #define VGA_CRTC_V_TOTAL        0x06
 116 #define VGA_CRTC_OVFL_REG       0x07
 117 #define         VGA_CRTC_OVFL_REG_VT8   0
 118 #define         VGA_CRTC_OVFL_REG_VDE8  1
 119 #define         VGA_CRTC_OVFL_REG_VRS8  2
 120 #define         VGA_CRTC_OVFL_REG_SVB8  3
 121 #define         VGA_CRTC_OVFL_REG_LCM8  4
 122 #define         VGA_CRTC_OVFL_REG_VT9   5
 123 #define         VGA_CRTC_OVFL_REG_VDE9  6
 124 #define         VGA_CRTC_OVFL_REG_VRS9  7
 125 #define         VGA_CRTC_OVFL_REG_PUT_VT(n)     \
 126                         ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_VT8) \
 127                         | ((((n)>>9)&1)<<VGA_CRTC_OVFL_REG_VT9)
 128 #define         VGA_CRTC_OVFL_REG_PUT_VDE(n)    \
 129                         ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_VDE8) \
 130                         | ((((n)>>9)&1)<<VGA_CRTC_OVFL_REG_VDE9)
 131 #define         VGA_CRTC_OVFL_REG_PUT_VRS(n)    \
 132                         ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_VRS8) \
 133                         | ((((n)>>9)&1)<<VGA_CRTC_OVFL_REG_VRS9)
 134 #define         VGA_CRTC_OVFL_REG_PUT_LCM(n)    \
 135                         ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_LCM8)
 136 #define         VGA_CRTC_OVFL_REG_PUT_SVB(n)    \
 137                         ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_SVB8)
 138 #define VGA_CRTC_P_R_SCAN       0x08
 139 #define VGA_CRTC_MAX_S_LN       0x09
 140 #define         VGA_CRTC_MAX_S_LN_SVB9  5
 141 #define         VGA_CRTC_MAX_S_LN_LCM9  6
 142 #define         VGA_CRTC_MAX_S_LN_PUT_SVB(n)    \
 143                         ((((n)>>9)&1)<<VGA_CRTC_MAX_S_LN_SVB9)
 144 #define         VGA_CRTC_MAX_S_LN_PUT_LCM(n)    \
 145                         ((((n)>>9)&1)<<VGA_CRTC_MAX_S_LN_LCM9)
 146 #define VGA_CRTC_CSSL           0x0a
 147 #define VGA_CRTC_CESL           0x0b
 148 #define VGA_CRTC_STAH           0x0c
 149 #define VGA_CRTC_STAL           0x0d
 150 #define VGA_CRTC_CLAH           0x0e
 151 #define VGA_CRTC_CLAL           0x0f
 152 #define VGA_CRTC_VRS            0x10
 153 #define VGA_CRTC_VRE            0x11
 154 #define         VGA_CRTC_VRE_LOCK       0x80
 155 #define         VGA_CRTC_VRE_DIS_VINT   0x20
 156 #define         VGA_CRTC_VRE_PUT_VRE(n) \
 157                         ((n)&0x0f)
 158 #define VGA_CRTC_VDE            0x12
 159 #define VGA_CRTC_SCREEN_OFFSET  0x13
 160 #define VGA_CRTC_ULL            0x14
 161 #define VGA_CRTC_SVB            0x15
 162 #define VGA_CRTC_EVB            0x16
 163 #define VGA_CRTC_CRT_MD         0x17
 164 #define         VGA_CRTC_CRT_MD_2BK_CGA         0x01
 165 #define         VGA_CRTC_CRT_MD_4BK_HGC         0x02
 166 #define         VGA_CRTC_CRT_MD_VT_X2           0x04
 167 #define         VGA_CRTC_CRT_MD_WRD_MODE        0x08
 168 #define         VGA_CRTC_CRT_MD_ADW_16K         0x20
 169 #define         VGA_CRTC_CRT_MD_BYTE_MODE       0x40
 170 #define         VGA_CRTC_CRT_MD_NO_RESET        0x80
 171 #define VGA_CRTC_LCM            0x18
 172
 173 /*
 174  * Sequencer registers
 175  */
 176 #define VGA_SEQ_RST_SYN         0x00
 177 #define         VGA_SEQ_RST_SYN_ASYNC_RESET     0x00
 178 #define         VGA_SEQ_RST_SYN_NO_ASYNC_RESET  0x01
 179 #define         VGA_SEQ_RST_SYN_SYNC_RESET      0x00
 180 #define         VGA_SEQ_RST_SYN_NO_SYNC_RESET   0x02
 181 #define VGA_SEQ_CLK_MODE        0x01
 182 #define         VGA_SEQ_CLK_MODE_8DC            0x01
 183 #define VGA_SEQ_EN_WT_PL        0x02
 184 #define         VGA_SEQ_EN_WT_PL_ALL            0x0f
 185 #define VGA_SEQ_CMS             0x03            /* Char Map Select */
 186 #define         VGA_SEQ_CMS_SAH                 0x20    /* Char. A (bit 2) */
 187 #define         VGA_SEQ_CMS_SBH                 0x10    /* Char. B (bit 2) */
 188 #define         VGA_SEQ_CMS_SA                  0x0C    /* Char. A (bit 0+1) */
 189 #define         VGA_SEQ_CMS_SB                  0x03    /* Char. B (bit 0+1) */
 190 #define VGA_SEQ_MEM_MODE        0x04
 191 #define         VGA_SEQ_MEM_MODE_EXT_MEM        0x02
 192 #define         VGA_SEQ_MEM_MODE_SEQ_MODE       0x04
 193 #define         VGA_SEQ_MEM_MODE_CHN_4M         0x08
 194
 195 /*
 196  * Graphics Controller
 197  */
 198 #define VGA_GRC_SET_RST_DT      0x00
 199 #define VGA_GRC_EN_S_R_DT       0x01
 200 #define VGA_GRC_COLOR_CMP       0x02
 201 #define VGA_GRC_WT_ROP_RTC      0x03
 202 #define VGA_GRC_RD_PL_SL        0x04
 203 #define VGA_GRC_GRP_MODE        0x05
 204 #define         VGA_GRC_GRP_MODE_SHF_MODE_256   0x40
 205 #define VGA_GRC_MISC_GM         0x06
 206 #define         VGA_GRC_MISC_GM_GRAPH           0x01
 207 #define         VGA_GRC_MISC_GM_MEM_MAP_1       0x04
 208 #define VGA_GRC_CMP_DNTC        0x07
 209 #define         VGA_GRC_CMP_DNTC_ALL            0x0f
 210 #define VGA_GRC_BIT_MASK        0x08
 211
 212 /*
 213  * Attribute controller registers
 214  */
 215 #define VGA_ATR_PAS             0x20    /* Palette Address Source */
 216 #define VGA_ATR_PLT_REG         0x00    /* Palette Register */
 217 #define VGA_ATR_NUM_PLT         0x10    /* Palette Register count */
 218 #define VGA_ATR_MODE            0x10    /* Attribute mode control */
 219 #define         VGA_ATR_MODE_GRAPH      0x01    /* Graphics enable */
 220 #define         VGA_ATR_MODE_MONO       0x02    /* Monochrome emulation */
 221 #define         VGA_ATR_MODE_9WIDE      0x04    /* Line Graphics enable */
 222 #define         VGA_ATR_MODE_BLINK      0x08    /* Blink enable */
 223 #define         VGA_ATR_MODE_PPM        0x20    /* Pixel panning mode */
 224 #define         VGA_ATR_MODE_256CLR     0x40    /* 8-bit color enable */
 225 #define         VGA_ATR_MODE_P54S       0x80    /* Palette bits 4-5 select */
 226 #define VGA_ATR_BDR_CLR         0x11
 227 #define VGA_ATR_DISP_PLN        0x12
 228 #define         VGA_ATR_DISP_PLN_ALL    0x0f
 229 #define VGA_ATR_H_PX_PAN        0x13
 230 #define VGA_ATR_PX_PADD         0x14
 231
 232 /*
 233  * Low-memory frame buffer definitions.  These are relative to the
 234  * A0000 register set.
 235  */
 236 #define VGA_MONO_BASE           0x10000 /* Base of monochrome text */
 237 #define VGA_COLOR_BASE          0x18000 /* Base of color text */
 238 #define VGA_TEXT_SIZE           0x8000  /* Size of text frame buffer */
 239
 240 #ifdef  __cplusplus
 241 }
 242 #endif
 243
 244 #endif /* _SYS_VGAREG_H */