usr/src/uts/common/sys/asy.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*      Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
  22 /*      Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T   */
  23 /*        All Rights Reserved   */
  24
  25 /*
  26  * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
  27  * Copyright 2023 Oxide Computer Company
  28  * Copyright 2024 Hans Rosenfeld
  29  */
  30
  31 #ifndef _SYS_ASY_H
  32 #define _SYS_ASY_H
  33
  34 #ifdef __cplusplus
  35 extern "C" {
  36 #endif
  37
  38 #include <sys/tty.h>
  39 #include <sys/ksynch.h>
  40 #include <sys/dditypes.h>
  41
  42 /*
  43  * internal bus type naming
  44  */
  45 #define ASY_BUS_PCI     (0)
  46 #define ASY_BUS_ISA     (1)
  47 #define ASY_BUS_UNKNOWN (-1)
  48
  49 #define ASY_MINOR_LEN   (40)
  50
  51 #define COM1_IOADDR     0x3f8
  52 #define COM2_IOADDR     0x2f8
  53 #define COM3_IOADDR     0x3e8
  54 #define COM4_IOADDR     0x2e8
  55
  56 /*
  57  * asy_hwtype definitions
  58  *
  59  * W.r.t the supported device registers, the 16650 actually a superset of the
  60  * 16750, hence the ordering.
  61  */
  62 #define ASY_8250A       0x00008250      /* 8250A or 16450 */
  63 #define ASY_16550       0x10016550      /* broken FIFO which must not be used */
  64 #define ASY_16550A      0x20016551      /* usable FIFO */
  65 #define ASY_16750       0x30016750      /* 64 byte FIFO, auto flow control */
  66 #define ASY_16650       0x40016650      /* 32 byte FIFO, auto flow control */
  67 #define ASY_16950       0x50016950      /* 128 byte FIFO, auto flow control */
  68 #define ASY_MAXCHIP     ASY_16950
  69
  70 /*
  71  * Definitions for INS8250 / 16550  chips
  72  */
  73 typedef enum {
  74         ASY_ILLEGAL = 0,
  75         /* 8250 / 16450 / 16550 registers */
  76         ASY_THR,                /* Transmitter Holding Register (W) */
  77         ASY_RHR,                /* Receiver Holding Register    (R) */
  78         ASY_IER,                /* Interrupt Enable Register    (R/W) */
  79         ASY_FCR,                /* FIFO Control Register        (W) */
  80         ASY_ISR,                /* Interrupt Status Register    (R) */
  81         ASY_LCR,                /* Line Control Register        (R/W) */
  82         ASY_MCR,                /* Modem Control Register       (R/W) */
  83         ASY_LSR,                /* Line Status Register         (R) */
  84         ASY_MSR,                /* Modem Status Register        (R) */
  85         ASY_SPR,                /* Scratch Pad Register         (R/W) */
  86         ASY_DLL,                /* Divisor Latch Low            (R/W) */
  87         ASY_DLH,                /* Divisor Latch High           (R/W) */
  88
  89         /* 16750 extended register */
  90         ASY_EFR,                /* Extended Feature Register    (R/W) */
  91
  92         /* 16650 extended registers */
  93         ASY_XON1,               /* XON Character 1              (R/W) */
  94         ASY_XON2,               /* XON Character 2              (R/W) */
  95         ASY_XOFF1,              /* XOFF Character 1             (R/W) */
  96         ASY_XOFF2,              /* XOFF Character 2             (R/W) */
  97
  98         /* 16950 additional registers */
  99         ASY_ASR,                /* Additional Status Register   (R/W) */
 100         ASY_RFL,                /* Receiver FIFO Length         (R/W) */
 101         ASY_TFL,                /* Transmitter FIFO Length      (R/W) */
 102         ASY_ICR,                /* Indexed Control Register     (R/W) */
 103
 104         /* 16950 indexed registers */
 105         ASY_ACR,                /* Additional Control Register  (R/W) */
 106         ASY_CPR,                /* Clock Prescaler Register     (R/W) */
 107         ASY_TCR,                /* Times Clock Register         (R/W) */
 108         ASY_CKS,                /* Clock Select Register        (R/W) */
 109         ASY_TTL,                /* Transmitter Trigger Level    (R/W) */
 110         ASY_RTL,                /* Receiver Trigger Level       (R/W) */
 111         ASY_FCL,                /* Flow Control Low-Level       (R/W) */
 112         ASY_FCH,                /* Flow Control High-Level      (R/W) */
 113         ASY_ID1,                /* Device Identification 1      (R) */
 114         ASY_ID2,                /* Device Identification 2      (R) */
 115         ASY_ID3,                /* Device Identification 3      (R) */
 116         ASY_REV,                /* Device Revision              (R) */
 117         ASY_CSR,                /* Channel Software Reset       (W) */
 118         ASY_NMR,                /* Nine-Bit Mode Register       (R/W) */
 119
 120         ASY_NREG,
 121 } asy_reg_t;
 122
 123 /*
 124  * INTEL 8210-A/B & 16450/16550 Registers Structure.
 125  */
 126
 127 /* Interrupt Enable Register */
 128 #define ASY_IER_RIEN    0x01    /* Received Data Ready */
 129 #define ASY_IER_TIEN    0x02    /* Tx Hold Register Empty */
 130 #define ASY_IER_SIEN    0x04    /* Receiver Line Status */
 131 #define ASY_IER_MIEN    0x08    /* Modem Status */
 132 #define ASY_IER_ALL     \
 133         (ASY_IER_RIEN | ASY_IER_TIEN | ASY_IER_SIEN | ASY_IER_MIEN)
 134
 135 /* FIFO Control register */
 136 #define ASY_FCR_FIFO_EN 0x01    /* FIFOs enabled */
 137 #define ASY_FCR_RHR_FL  0x02    /* flush receiver FIFO */
 138 #define ASY_FCR_THR_FL  0x04    /* flush transmitter FIFO */
 139 #define ASY_FCR_DMA     0x08    /* DMA mode 1 */
 140 #define ASY_FCR_THR_TR0 0x10    /* transmitter trigger level bit 0 (16650) */
 141 #define ASY_FCR_THR_TR1 0x20    /* transmitter trigger level bit 1 (16650) */
 142 #define ASY_FCR_FIFO64  0x20    /* 64 byte FIFO enable (16750) */
 143 #define ASY_FCR_RHR_TR0 0x40    /* receiver trigger level bit 0 */
 144 #define ASY_FCR_RHR_TR1 0x80    /* receiver trigger level bit 1 */
 145
 146 /* 16550 receiver trigger levels */
 147 #define ASY_FCR_RHR_TRIG_1      0               /*  1 byte RX trigger level */
 148 #define ASY_FCR_RHR_TRIG_4      ASY_FCR_RHR_TR0 /*  4 byte RX trigger level */
 149 #define ASY_FCR_RHR_TRIG_8      ASY_FCR_RHR_TR1 /*  8 byte RX trigger level */
 150 #define ASY_FCR_RHR_TRIG_14     \
 151         (ASY_FCR_THR_TR0 | ASY_FCR_THR_TR1)     /* 14 byte RX trigger level */
 152
 153 /* 16650 transmitter trigger levels */
 154 #define ASY_FCR_THR_TRIG_16     0               /* 16 byte TX trigger level */
 155 #define ASY_FCR_THR_TRIG_8      ASY_FCR_THR_TR0 /*  8 byte TX trigger level */
 156 #define ASY_FCR_THR_TRIG_24     ASY_FCR_THR_TR1 /* 24 byte TX trigger level */
 157 #define ASY_FCR_THR_TRIG_30     \
 158         (ASY_FCR_THR_TR0 | ASY_FCR_THR_TR1)     /* 30 byte TX trigger level */
 159
 160 #define ASY_FCR_FIFO_OFF 0      /* FIFOs disabled */
 161
 162 /* Interrupt Status Register */
 163 #define ASY_ISR_NOINTR  0x01    /* no interrupt pending */
 164 #define ASY_ISR_MASK    0x0e    /* interrupt identification mask */
 165 #define ASY_ISR_EMASK   0x3e    /* interrupt id mask when EFR[4] = 1 (16650) */
 166
 167 #define ASY_ISR_FIFO64  0x20    /* 64 byte FIFOs enabled (16750) */
 168 #define ASY_ISR_FIFOEN  0xc0    /* FIFOs enabled (16550A and up) */
 169
 170 #define ASY_ISR_ID_RLST 0x06    /* Receiver Line Status */
 171 #define ASY_ISR_ID_RDA  0x04    /* Receiver Data Available */
 172 #define ASY_ISR_ID_TMO  0x0c    /* Character timeout (16550A and up) */
 173 #define ASY_ISR_ID_THRE 0x02    /* Transmitter Holding Register Empty */
 174 #define ASY_ISR_ID_MST  0x00    /* Modem Status changed */
 175 #define ASY_ISR_ID_XOFF 0x10    /* Received XOFF / special character (16650) */
 176 #define ASY_ISR_ID_RCTS 0x20    /* RTS/CTS changed (16650) */
 177
 178 /* Line Control Register */
 179 #define ASY_LCR_WLS0    0x01    /* word length select bit 0 */
 180 #define ASY_LCR_WLS1    0x02    /* word length select bit 2 */
 181 #define ASY_LCR_STB     0x04    /* number of stop bits */
 182 #define ASY_LCR_PEN     0x08    /* parity enable */
 183 #define ASY_LCR_EPS     0x10    /* even parity select */
 184 #define ASY_LCR_SPS     0x20    /* stick parity select */
 185 #define ASY_LCR_SETBRK  0x40    /* break key */
 186 #define ASY_LCR_DLAB    0x80    /* divisor latch access bit */
 187
 188 #define ASY_LCR_STOP1   0x00
 189 #define ASY_LCR_STOP2   ASY_LCR_STB
 190
 191 #define ASY_LCR_EFRACCESS       0xBF    /* magic value for 16650 EFR access */
 192
 193 #define ASY_LCR_BITS5   0x00                            /* 5 bits per char */
 194 #define ASY_LCR_BITS6   ASY_LCR_WLS0                    /* 6 bits per char */
 195 #define ASY_LCR_BITS7   ASY_LCR_WLS1                    /* 7 bits per char */
 196 #define ASY_LCR_BITS8   (ASY_LCR_WLS0 | ASY_LCR_WLS1)   /* 8 bits per char */
 197
 198 /* Modem Control Register */
 199 #define ASY_MCR_DTR     0x01    /* Data Terminal Ready */
 200 #define ASY_MCR_RTS     0x02    /* Request To Send */
 201 #define ASY_MCR_OUT1    0x04    /* Aux output - not used */
 202 #define ASY_MCR_OUT2    0x08    /* turns intr to 386 on/off */
 203 #define ASY_MCR_LOOP    0x10    /* loopback for diagnostics */
 204
 205 #define ASY_MCR_LOOPBACK        \
 206         (ASY_MCR_DTR | ASY_MCR_RTS | ASY_MCR_OUT1 | ASY_MCR_OUT2 | ASY_MCR_LOOP)
 207
 208 /* Line Status Register */
 209 #define ASY_LSR_DR      0x01    /* data ready */
 210 #define ASY_LSR_OE      0x02    /* overrun error */
 211 #define ASY_LSR_PE      0x04    /* parity error */
 212 #define ASY_LSR_FE      0x08    /* framing error */
 213 #define ASY_LSR_BI      0x10    /* break interrupt */
 214 #define ASY_LSR_THRE    0x20    /* transmitter holding register empty */
 215 #define ASY_LSR_TEMT    0x40    /* transmitter empty (THR + TSR empty) */
 216 #define ASY_LSR_DE      0x80    /* Receiver FIFO data error */
 217
 218 #define ASY_LSR_ERRORS  \
 219         (ASY_LSR_OE | ASY_LSR_PE | ASY_LSR_FE | ASY_LSR_BI)
 220
 221 /* Modem Status Register */
 222 #define ASY_MSR_DCTS    0x01    /* Delta Clear To Send */
 223 #define ASY_MSR_DDSR    0x02    /* Delta Data Set Ready */
 224 #define ASY_MSR_TERI    0x04    /* Trailing Edge Ring Indicator */
 225 #define ASY_MSR_DDCD    0x08    /* Delta Data Carrier Detect */
 226 #define ASY_MSR_CTS     0x10    /* Clear To Send */
 227 #define ASY_MSR_DSR     0x20    /* Data Set Ready */
 228 #define ASY_MSR_RI      0x40    /* Ring Indicator */
 229 #define ASY_MSR_DCD     0x80    /* Data Carrier Detect */
 230
 231 #define ASY_MSR_DELTAS(x)       \
 232         ((x) & (ASY_MSR_DCTS | ASY_MSR_DDSR | ASY_MSR_TERI | ASY_MSR_DDCD))
 233 #define ASY_MSR_STATES(x)       \
 234         ((x) & (ASY_MSR_CTS | ASY_MSR_DSR | ASY_MSR_RI | ASY_MSR_DCD))
 235
 236 /* Scratch Pad Register */
 237 #define ASY_SPR_TEST    0x5a    /* arbritrary value for testing SPR */
 238
 239 /* Extended Feature Register (16650) */
 240 #define ASY_EFR_ENH_EN  0x10    /* IER[4:7], ISR[4,5], FCR[4,5], MCR[5:7] */
 241
 242 /* Additional Status Register (16950) */
 243 #define ASY_ASR_TD      0x01    /* Transmitter Disabled */
 244 #define ASY_ASR_RTD     0x02    /* Remote Transmitter Disabled */
 245 #define ASY_ASR_RTS     0x04    /* RTS status */
 246 #define ASY_ASR_DTR     0x08    /* DTR status */
 247 #define ASY_ASR_SCD     0x10    /* Special Character detected */
 248 #define ASY_ASR_FIFOSEL 0x20    /* FIFOSEL pin status */
 249 #define ASY_ASR_FIFOSZ  0x40    /* FIFO size */
 250 #define ASY_ASR_TI      0x80    /* Transmitter Idle */
 251
 252 /* Additional Control Register (16950) */
 253 #define ASY_ACR_RD      0x01    /* Receiver Disable */
 254 #define ASY_ACR_TD      0x02    /* Transmitter Disable */
 255 #define ASY_ACR_DSR     0x04    /* Automatic DSR flow control */
 256 #define ASY_ACR_DTR     0x18    /* DTR line configuration */
 257 #define ASY_ACR_TRIG    0x20    /* 950 mode trigger levels enable */
 258 #define ASY_ACR_ICR     0x40    /* ICR read enable */
 259 #define ASY_ACR_ASR     0x80    /* Additional Status Enable */
 260
 261 #define ASY_ACR_DTR_NORM        0x00    /* DTR normal (compatible) */
 262 #define ASY_ACR_DTR_FLOW        0x08    /* DTR used for flow-control */
 263 #define ASY_ACR_DTR_RS485_LOW   0x10    /* DTR drives ext. RS485 buffer low */
 264 #define ASY_ACR_DTR_RS485_HIGH  0x18    /* DTR drives ext. RS485 buffer high */
 265
 266 /* Clock Select Register (16950) */
 267 #define ASY_CKS_RCLK    0x00    /* RCLK pin drives receiver clock */
 268 #define ASY_CKS_RDSR    0x01    /* DSR pin drives receiver clock */
 269 #define ASY_CKS_RBDOUT  0x02    /* BDOUT pint drives receiver clock */
 270 #define ASY_CKS_RTCLK   0x03    /* transmitter clock drives receiver clock */
 271
 272 #define ASY_CKS_BDO_DIS 0x04    /* Disable BDOUT pin */
 273 #define ASY_CKS_RCLK_1X 0x08    /* Receiver clock in isochronous 1x mode */
 274
 275 #define ASY_CKS_DTR_NO  0x00    /* DTR pin defined by ACR[ASY_ACR_DTR] */
 276 #define ASY_CKS_DTR_T1X 0x10    /* Transmitter 1x clock on DTR pin */
 277 #define ASY_CKS_DTR_BDO 0x20    /* Baud rate generator output on DTR pin */
 278
 279 #define ASY_CKS_TCLK_RI 0x40    /* External transmitter clock on RI pin */
 280 #define ASY_CKS_TCLK_1X 0x80    /* Transmitter clock in isochronous 1x mode */
 281
 282 /* Serial in/out requests */
 283
 284 #define OVERRUN         040000
 285 #define FRERROR         020000
 286 #define PERROR          010000
 287 #define S_ERRORS        (PERROR|OVERRUN|FRERROR)
 288
 289 /*
 290  * Ring buffer and async line management definitions.
 291  */
 292 #define RINGBITS        16              /* # of bits in ring ptrs */
 293 #define RINGSIZE        (1<<RINGBITS)   /* size of ring */
 294 #define RINGMASK        (RINGSIZE-1)
 295 #define RINGFRAC        12              /* fraction of ring to force flush */
 296
 297 #define RING_INIT(ap)  ((ap)->async_rput = (ap)->async_rget = 0)
 298 #define RING_CNT(ap)   (((ap)->async_rput >= (ap)->async_rget) ? \
 299         ((ap)->async_rput - (ap)->async_rget):\
 300         ((0x10000 - (ap)->async_rget) + (ap)->async_rput))
 301 #define RING_FRAC(ap)  ((int)RING_CNT(ap) >= (int)(RINGSIZE/RINGFRAC))
 302 #define RING_POK(ap, n) ((int)RING_CNT(ap) < (int)(RINGSIZE-(n)))
 303 #define RING_PUT(ap, c) \
 304         ((ap)->async_ring[(ap)->async_rput++ & RINGMASK] =  (uchar_t)(c))
 305 #define RING_UNPUT(ap) ((ap)->async_rput--)
 306 #define RING_GOK(ap, n) ((int)RING_CNT(ap) >= (int)(n))
 307 #define RING_GET(ap)   ((ap)->async_ring[(ap)->async_rget++ & RINGMASK])
 308 #define RING_EAT(ap, n) ((ap)->async_rget += (n))
 309 #define RING_MARK(ap, c, s) \
 310         ((ap)->async_ring[(ap)->async_rput++ & RINGMASK] = ((uchar_t)(c)|(s)))
 311 #define RING_UNMARK(ap) \
 312         ((ap)->async_ring[((ap)->async_rget) & RINGMASK] &= ~S_ERRORS)
 313 #define RING_ERR(ap, c) \
 314         ((ap)->async_ring[((ap)->async_rget) & RINGMASK] & (c))
 315
 316 /* definitions for asy_progress */
 317 typedef enum {
 318         ASY_PROGRESS_REGS =     0x01,
 319         ASY_PROGRESS_SOFTINT =  0x02,
 320         ASY_PROGRESS_INT =      0x04,
 321         ASY_PROGRESS_MUTEX =    0x08,
 322         ASY_PROGRESS_ASYNC =    0x10,
 323         ASY_PROGRESS_MINOR =    0x20
 324 } asy_progress_t;
 325
 326 /*
 327  * Hardware channel common data. One structure per port.
 328  * Each of the fields in this structure is required to be protected by a
 329  * mutex lock at the highest priority at which it can be altered.
 330  * The asy_flags, and asy_next fields can be altered by interrupt
 331  * handling code that must be protected by the mutex whose handle is
 332  * stored in asy_excl_hi.  All others can be protected by the asy_excl
 333  * mutex, which is lower priority and adaptive.
 334  */
 335
 336 struct asycom {
 337 #ifdef DEBUG
 338         int             asy_debug;      /* per-instance debug flags */
 339 #endif
 340         asy_progress_t  asy_progress;   /* attach progress */
 341         int             asy_flags;      /* random flags  */
 342                                         /* protected by asy_excl_hi lock */
 343         uint_t          asy_hwtype;     /* HW type: ASY16550A, etc. */
 344         uint_t          asy_use_fifo;   /* HW FIFO use it or not ?? */
 345         uint_t          asy_fifo_buf;   /* With FIFO = 16, otherwise = 1 */
 346         uint_t          asy_flags2;     /* flags which don't change, no lock */
 347         uint8_t         *asy_ioaddr;    /* i/o address of ASY port */
 348         struct asyncline *asy_priv;     /* protocol private data -- asyncline */
 349         dev_info_t      *asy_dip;       /* dev_info */
 350         int             asy_unit;       /* which port */
 351         kmutex_t        asy_excl;       /* asy adaptive mutex */
 352         kmutex_t        asy_excl_hi;    /* asy spinlock mutex */
 353         kmutex_t        asy_soft_lock;  /* soft lock for guarding softpend. */
 354         int             asysoftpend;    /* Flag indicating soft int pending. */
 355
 356         ddi_softint_handle_t asy_soft_inth;
 357         uint_t          asy_soft_intr_pri;
 358
 359         ddi_intr_handle_t *asy_inth;
 360         size_t          asy_inth_sz;
 361         uint_t          asy_intr_pri;
 362         int             asy_intr_cnt;
 363         int             asy_intr_cap;
 364         int             asy_intr_type;
 365         int             asy_intr_types;
 366
 367         /*
 368          * The asy_soft_sr mutex should only be taken by the soft interrupt
 369          * handler and the driver DDI_SUSPEND/DDI_RESUME code.  It
 370          * shouldn't be taken by any code that may get called indirectly
 371          * by the soft interrupt handler (e.g. as a result of a put or
 372          * putnext call).
 373          */
 374         kmutex_t        asy_soft_sr;    /* soft int suspend/resume mutex */
 375         uchar_t         asy_msr;        /* saved modem status */
 376         uchar_t         asy_mcr;        /* soft carrier bits */
 377         uchar_t         asy_lcr;        /* console lcr bits */
 378         uchar_t         asy_bidx;       /* console baud rate index */
 379         tcflag_t        asy_cflag;      /* console mode bits */
 380         struct cons_polledio    polledio;       /* polled I/O functions */
 381         ddi_acc_handle_t        asy_iohandle;   /* Data access handle */
 382         tcflag_t        asy_ocflag;     /* old console mode bits */
 383         uchar_t         asy_com_port;   /* COM port number, or zero */
 384         uchar_t         asy_fifor;      /* FIFOR register setting */
 385         uint8_t         asy_acr;        /* 16950 additional control register */
 386 #ifdef DEBUG
 387         int             asy_msint_cnt;  /* number of times in async_msint */
 388 #endif
 389 };
 390
 391 /*
 392  * Asychronous protocol private data structure for ASY.
 393  * Each of the fields in the structure is required to be protected by
 394  * the lower priority lock except the fields that are set only at
 395  * base level but cleared (with out lock) at interrupt level.
 396  */
 397
 398 struct asyncline {
 399         int             async_flags;    /* random flags */
 400         kcondvar_t      async_flags_cv; /* condition variable for flags */
 401         kcondvar_t      async_ops_cv;   /* condition variable for async_ops */
 402         dev_t           async_dev;      /* device major/minor numbers */
 403         mblk_t          *async_xmitblk; /* transmit: active msg block */
 404         struct asycom   *async_common;  /* device common data */
 405         tty_common_t    async_ttycommon; /* tty driver common data */
 406         bufcall_id_t    async_wbufcid;  /* id for pending write-side bufcall */
 407         size_t          async_wbufcds;  /* Buffer size requested in bufcall */
 408         timeout_id_t    async_polltid;  /* softint poll timeout id */
 409         timeout_id_t    async_dtrtid;   /* delaying DTR turn on */
 410         timeout_id_t    async_utbrktid; /* hold minimum untimed break time id */
 411
 412         /*
 413          * The following fields are protected by the asy_excl_hi lock.
 414          * Some, such as async_flowc, are set only at the base level and
 415          * cleared (without the lock) only by the interrupt level.
 416          */
 417         uchar_t         *async_optr;    /* output pointer */
 418         int             async_ocnt;     /* output count */
 419         uint_t          async_rput;     /* producing pointer for input */
 420         uint_t          async_rget;     /* consuming pointer for input */
 421
 422         /*
 423          * Each character stuffed into the ring has two bytes associated
 424          * with it.  The first byte is used to indicate special conditions
 425          * and the second byte is the actual data.  The ring buffer
 426          * needs to be defined as ushort_t to accomodate this.
 427          */
 428         ushort_t        async_ring[RINGSIZE];
 429
 430         short           async_break;    /* break count */
 431         int             async_inflow_source; /* input flow control type */
 432
 433         union {
 434                 struct {
 435                         uchar_t _hw;    /* overrun (hw) */
 436                         uchar_t _sw;    /* overrun (sw) */
 437                 } _a;
 438                 ushort_t uover_overrun;
 439         } async_uover;
 440 #define async_overrun           async_uover._a.uover_overrun
 441 #define async_hw_overrun        async_uover._a._hw
 442 #define async_sw_overrun        async_uover._a._sw
 443         short           async_ext;      /* modem status change count */
 444         short           async_work;     /* work to do flag */
 445         timeout_id_t    async_timer;    /* close drain progress timer */
 446
 447         mblk_t          *async_suspqf;  /* front of suspend queue */
 448         mblk_t          *async_suspqb;  /* back of suspend queue */
 449         int             async_ops;      /* active operations counter */
 450 };
 451
 452 /* definitions for async_flags field */
 453 #define ASYNC_EXCL_OPEN  0x10000000     /* exclusive open */
 454 #define ASYNC_WOPEN      0x00000001     /* waiting for open to complete */
 455 #define ASYNC_ISOPEN     0x00000002     /* open is complete */
 456 #define ASYNC_OUT        0x00000004     /* line being used for dialout */
 457 #define ASYNC_CARR_ON    0x00000008     /* carrier on last time we looked */
 458 #define ASYNC_STOPPED    0x00000010     /* output is stopped */
 459 #define ASYNC_DELAY      0x00000020     /* waiting for delay to finish */
 460 #define ASYNC_BREAK      0x00000040     /* waiting for break to finish */
 461 #define ASYNC_BUSY       0x00000080     /* waiting for transmission to finish */
 462 #define ASYNC_DRAINING   0x00000100     /* waiting for output to drain */
 463 #define ASYNC_SERVICEIMM 0x00000200     /* queue soft interrupt as soon as */
 464 #define ASYNC_HW_IN_FLOW 0x00000400     /* input flow control in effect */
 465 #define ASYNC_HW_OUT_FLW 0x00000800     /* output flow control in effect */
 466 #define ASYNC_PROGRESS   0x00001000     /* made progress on output effort */
 467 #define ASYNC_CLOSING    0x00002000     /* processing close on stream */
 468 #define ASYNC_OUT_SUSPEND 0x00004000    /* waiting for TIOCSBRK to finish */
 469 #define ASYNC_HOLD_UTBRK 0x00008000     /* waiting for untimed break hold */
 470                                         /* the minimum time */
 471 #define ASYNC_DTR_DELAY  0x00010000     /* delaying DTR turn on */
 472 #define ASYNC_SW_IN_FLOW 0x00020000     /* sw input flow control in effect */
 473 #define ASYNC_SW_OUT_FLW 0x00040000     /* sw output flow control in effect */
 474 #define ASYNC_SW_IN_NEEDED 0x00080000   /* sw input flow control char is */
 475                                         /* needed to be sent */
 476 #define ASYNC_OUT_FLW_RESUME 0x00100000 /* output need to be resumed */
 477                                         /* because of transition of flow */
 478                                         /* control from stop to start */
 479 #define ASYNC_DDI_SUSPENDED  0x00200000 /* suspended by DDI */
 480 #define ASYNC_RESUME_BUFCALL 0x00400000 /* call bufcall when resumed by DDI */
 481
 482 /* definitions for asy_flags field */
 483 #define ASY_NEEDSOFT    0x00000001
 484 #define ASY_DOINGSOFT   0x00000002
 485 #define ASY_PPS         0x00000004
 486 #define ASY_PPS_EDGE    0x00000008
 487 #define ASY_DOINGSOFT_RETRY     0x00000010
 488 #define ASY_RTS_DTR_OFF 0x00000020
 489 #define ASY_IGNORE_CD   0x00000040
 490 #define ASY_CONSOLE     0x00000080
 491 #define ASY_DDI_SUSPENDED       0x00000100 /* suspended by DDI */
 492
 493 /* definitions for asy_flags2 field */
 494 #define ASY2_NO_LOOPBACK 0x00000001     /* Device doesn't support loopback */
 495
 496 /* definitions for async_inflow_source field in struct asyncline */
 497 #define IN_FLOW_NULL    0x00000000
 498 #define IN_FLOW_RINGBUFF        0x00000001
 499 #define IN_FLOW_STREAMS 0x00000002
 500 #define IN_FLOW_USER    0x00000004
 501
 502 /*
 503  * OUTLINE defines the high-order flag bit in the minor device number that
 504  * controls use of a tty line for dialin and dialout simultaneously.
 505  */
 506 #ifdef _LP64
 507 #define OUTLINE         (1 << (NBITSMINOR32 - 1))
 508 #else
 509 #define OUTLINE         (1 << (NBITSMINOR - 1))
 510 #endif
 511 #define UNIT(x)         (getminor(x) & ~OUTLINE)
 512
 513 /* This corresponds to DDI_SOFTINT_MED used by the old softint routines. */
 514 #define ASY_SOFT_INT_PRI        6
 515
 516
 517 #ifdef __cplusplus
 518 }
 519 #endif
 520
 521 #endif  /* _SYS_ASY_H */