usr/src/uts/common/io/rtw/sa2400reg.h

   1 /*
   2  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
   3  * Use is subject to license terms.
   4  */
   5 /*
   6  * Copyright (c) 2005 David Young.  All rights reserved.
   7  *
   8  * This code was written by David Young.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
  23  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  24  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  25  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
  26  * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  27  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  28  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  31  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  33  * OF SUCH DAMAGE.
  34  */
  35 #ifndef _SA2400REG_H_
  36 #define _SA2400REG_H_
  37
  38 #ifdef __cplusplus
  39 extern "C" {
  40 #endif
  41
  42 /*
  43  * Serial bus format for Philips SA2400 Single-chip Transceiver.
  44  */
  45 #define SA2400_TWI_DATA_MASK    BITS(31, 8)
  46 #define SA2400_TWI_WREN         BIT(7)          /* enable write */
  47 #define SA2400_TWI_ADDR_MASK    BITS(6, 0)
  48
  49 /*
  50  * Registers for Philips SA2400 Single-chip Transceiver.
  51  */
  52 #define SA2400_SYNA             0               /* Synthesizer Register A */
  53 /*
  54  * fractional modulus select,
  55  * 0: /8 (default)
  56  * 1: /5
  57  */
  58 #define SA2400_SYNA_FM          BIT(21)
  59 /*
  60  * fractional increment value,
  61  * 0 to 7, default 4
  62  */
  63 #define SA2400_SYNA_NF_MASK     BITS(20, 18)
  64 /*
  65  * main divider division ratio,
  66  * 512 to 65535, default 615
  67  */
  68 #define SA2400_SYNA_N_MASK      BITS(17, 2)
  69
  70 #define SA2400_SYNB             1               /* Synthesizer Register B */
  71 /*
  72  * reference divider ratio,
  73  * 4 to 1023, default 11
  74  */
  75
  76 #define SA2400_SYNB_R_MASK      BITS(21, 12)
  77 #define SA2400_SYNB_L_MASK      BITS(11, 10)    /* lock detect mode */
  78 #define SA2400_SYNB_L_INACTIVE0 LSHIFT(0, SA2400_SYNB_L_MASK)
  79 #define SA2400_SYNB_L_INACTIVE1 LSHIFT(1, SA2400_SYNB_L_MASK)
  80 #define SA2400_SYNB_L_NORMAL    LSHIFT(2, SA2400_SYNB_L_MASK)
  81 #define SA2400_SYNB_L_INACTIVE2 LSHIFT(3, SA2400_SYNB_L_MASK)
  82
  83 /*
  84  * power on/off,
  85  * 0: inverted chip mode control
  86  * 1: as defined by chip mode (see SA2400_OPMODE)
  87  */
  88
  89 #define SA2400_SYNB_ON          BIT(9)
  90 #define SA2400_SYNB_ONE         BIT(8)          /* always 1 */
  91 /*
  92  * fractional compensation
  93  * charge pump current DAC,
  94  * 0 to 255, default 80.
  95  */
  96
  97 #define SA2400_SYNB_FC_MASK     BITS(7, 0)
  98 #define SA2400_SYNC             2               /* Synthesizer Register C */
  99 #define SA2400_SYNC_CP_MASK     BITS(7, 6) /* charge pump current setting */
 100 #define SA2400_SYNC_CP_NORMAL_  LSHIFT(0, SA2400_SYNC_CP_MASK)
 101 #define SA2400_SYNC_CP_THIRD_   LSHIFT(1, SA2400_SYNC_CP_MASK)
 102 #define SA2400_SYNC_CP_NORMAL   LSHIFT(2, SA2400_SYNC_CP_MASK) /* recommended */
 103 #define SA2400_SYNC_CP_THIRD    LSHIFT(3, SA2400_SYNC_CP_MASK)
 104
 105 /*
 106  * comparison divider select,
 107  * 0 to 4, extra division
 108  * ratio is 2**SM.
 109  */
 110 #define SA2400_SYNC_SM_MASK     BITS(5, 3)
 111 #define SA2400_SYNC_ZERO        BIT(2)          /* always 0 */
 112
 113 #define SA2400_SYND             3               /* Synthesizer Register D */
 114 #define SA2400_SYND_ZERO1_MASK  BITS(21, 17)    /* always 0 */
 115 /*
 116  * T[phpsu], 1: disable
 117  * PHP speedup pump,
 118  * overrides SA2400_SYND_TSPU
 119  */
 120 #define SA2400_SYND_TPHPSU      BIT(16)
 121 /*
 122  * T[spu], 1: speedup on,
 123  * 0: speedup off
 124  */
 125 #define SA2400_SYND_TPSU        BIT(15)
 126 #define SA2400_SYND_ZERO2_MASK  BITS(14, 3)     /* always 0 */
 127 /*
 128  * Operating mode, filter tuner,
 129  * other controls
 130  */
 131 #define SA2400_OPMODE           4
 132 /*
 133  * 1: in Rx mode, RSSI-ADC always on
 134  * 0: RSSI-ADC only on during AGC
 135  */
 136 #define SA2400_OPMODE_ADC       BIT(19)
 137 /*
 138  * read-only filter tuner error:
 139  * 1 if tuner out of range
 140  */
 141 #define SA2400_OPMODE_FTERR     BIT(18)
 142 /*
 143  * Rx & Tx filter tuning, write tuning value (test mode only) or
 144  * read tuner setting (in normal mode).
 145  */
 146 #define SA2400_OPMODE_FILTTUNE_MASK     BITS(17, 15)
 147 /*
 148  * external reference voltage
 149  * (pad v2p5) on
 150  */
 151 #define SA2400_OPMODE_V2P5      BIT(14)
 152 #define SA2400_OPMODE_I1M       BIT(13) /* external reference current ... */
 153 #define SA2400_OPMODE_I0P3      BIT(12) /* external reference current ... */
 154 /*
 155  * xtal input frequency,
 156  * 0: 44 MHz
 157  * 1: 22 MHz
 158  */
 159 #define SA2400_OPMODE_IN22      BIT(10)
 160 #define SA2400_OPMODE_CLK       BIT(9)  /* reference clock output on */
 161 #define SA2400_OPMODE_XO        BIT(8)  /* xtal oscillator on */
 162 #define SA2400_OPMODE_DIGIN     BIT(7)  /* use digital Tx inputs (FIRDAC) */
 163 /*
 164  * Rx output common mode voltage,
 165  * 0: V[DD]/2
 166  * 1: 1.25V
 167  */
 168 #define SA2400_OPMODE_RXLV      BIT(6)
 169 /*
 170  * make internal vco
 171  * available at vco pads (vcoextout)
 172  */
 173 #define SA2400_OPMODE_VEO       BIT(5)
 174 #define SA2400_OPMODE_VEI       BIT(4)  /* use external vco input (vcoextin) */
 175 /* main operating mode */
 176 #define SA2400_OPMODE_MODE_MASK         BITS(3, 0)
 177 #define SA2400_OPMODE_MODE_SLEEP        LSHIFT(0, SA2400_OPMODE_MODE_MASK)
 178 #define SA2400_OPMODE_MODE_TXRX         LSHIFT(1, SA2400_OPMODE_MODE_MASK)
 179 #define SA2400_OPMODE_MODE_WAIT         LSHIFT(2, SA2400_OPMODE_MODE_MASK)
 180 #define SA2400_OPMODE_MODE_RXMGC        LSHIFT(3, SA2400_OPMODE_MODE_MASK)
 181 #define SA2400_OPMODE_MODE_FCALIB       LSHIFT(4, SA2400_OPMODE_MODE_MASK)
 182 #define SA2400_OPMODE_MODE_DCALIB       LSHIFT(5, SA2400_OPMODE_MODE_MASK)
 183 #define SA2400_OPMODE_MODE_FASTTXRXMGC  LSHIFT(6, SA2400_OPMODE_MODE_MASK)
 184 #define SA2400_OPMODE_MODE_RESET        LSHIFT(7, SA2400_OPMODE_MODE_MASK)
 185 #define SA2400_OPMODE_MODE_VCOCALIB     LSHIFT(8, SA2400_OPMODE_MODE_MASK)
 186
 187 #define SA2400_OPMODE_DEFAULTS                                          \
 188         (SA2400_OPMODE_XO | SA2400_OPMODE_RXLV | SA2400_OPMODE_CLK |    \
 189         SA2400_OPMODE_I0P3 | LSHIFT(3, SA2400_OPMODE_FILTTUNE_MASK))
 190
 191 #define SA2400_AGC              5               /* AGC adjustment */
 192 /*
 193  * fine-tune AGC target:
 194  * -7dB to 7dB, sign bit ...
 195  */
 196 #define SA2400_AGC_TARGETSIGN   BIT(23)
 197 #define SA2400_AGC_TARGET_MASK  BITS(22, 20)    /* ... plus 0dB - 7dB */
 198 /*
 199  * maximum AGC gain, 0 to 31, (yields 54dB to 85dB)
 200  */
 201 #define SA2400_AGC_MAXGAIN_MASK BITS(19, 15)
 202 /*
 203  * write: settling time after baseband gain switching, units of
 204  *        182 nanoseconds.
 205  * read:  output of RSSI/Tx-peak detector's ADC in 5-bit Gray code.
 206  */
 207 #define SA2400_AGC_BBPDELAY_MASK        BITS(14, 10)
 208 #define SA2400_AGC_ADCVAL_MASK          SA2400_AGC_BBPDELAY_MASK
 209
 210 /*
 211  * write: settling time after LNA gain switching, units of
 212  *        182 nanoseconds
 213  * read:  2nd sample of RSSI in AGC cycle
 214  */
 215 #define SA2400_AGC_LNADELAY_MASK        BITS(9, 5)
 216 #define SA2400_AGC_SAMPLE2_MASK         SA2400_AGC_LNADELAY_MASK
 217
 218 /*
 219  * write: time between turning on Rx and AGCSET, units of
 220  *        182 nanoseconds
 221  * read:  1st sample of RSSI in AGC cycle
 222  */
 223 #define SA2400_AGC_RXONDELAY_MASK       BITS(4, 0)
 224 #define SA2400_AGC_SAMPLE1_MASK         SA2400_AGC_RXONDELAY_MASK
 225
 226 #define SA2400_MANRX            6       /* Manual receiver control settings */
 227 /*
 228  * 1: AGC w/ high S/N---switch LNA at
 229  *    step 52 (recommended)
 230  * 0: switch LNA at step 60
 231  */
 232 #define SA2400_MANRX_AHSN       BIT(23)
 233
 234 /*
 235  * If _RXOSQON, Q offset is
 236  * (_RXOSQSIGN ? -1 : 1) * (1 + _RXOSQ_MASK) * 8 millivolts,
 237  * otherwise, Q offset is 0.
 238  *
 239  * Ditto I offset.
 240  */
 241 #define SA2400_MANRX_RXOSQON    BIT(22)         /* Rx Q-channel correction. */
 242 #define SA2400_MANRX_RXOSQSIGN  BIT(21)
 243 #define SA2400_MANRX_RXOSQ_MASK BITS(20, 18)
 244
 245 #define SA2400_MANRX_RXOSION    BIT(17)         /* Rx I-channel correction. */
 246 #define SA2400_MANRX_RXOSISIGN  BIT(16)
 247 #define SA2400_MANRX_RXOSI_MASK BITS(15, 13)
 248 /*
 249  * use 10MHz offset cancellation cornerpoint for brief period
 250  * after each gain change
 251  */
 252 #define SA2400_MANRX_TEN        BIT(12)
 253
 254 /*
 255  * DC offset cancellation cornerpoint select
 256  * write: in RXMGC, set the cornerpoint
 257  * read:  in other modes, read AGC-controlled cornerpoint
 258  */
 259 #define SA2400_MANRX_CORNERFREQ_MASK    BITS(11, 10)
 260
 261 /*
 262  * write: in RXMGC mode, sets receiver gain
 263  * read:  in other modes, read AGC-controlled gain
 264  */
 265 #define SA2400_MANRX_RXGAIN_MASK        BITS(9, 0)
 266
 267 #define SA2400_TX       7               /* Transmitter settings */
 268 /*
 269  * Tx offsets
 270  * write: in test mode, sets the offsets
 271  * read:  in normal mode, returns automatic settings
 272  */
 273 #define SA2400_TX_TXOSQON       BIT(19)
 274 #define SA2400_TX_TXOSQSIGN     BIT(18)
 275 #define SA2400_TX_TXOSQ_MASK    BITS(17, 15)
 276 #define SA2400_TX_TXOSION       BIT(14)
 277 #define SA2400_TX_TXOSISIGN     BIT(13)
 278 #define SA2400_TX_TXOSI_MASK    BITS(12, 10)
 279
 280 /*
 281  * Ramp-up delay,
 282  * 0: 1us
 283  * 1: 2us
 284  * 2: 3us
 285  * 3: 4us
 286  * datasheet says, "ramp-up
 287  * time always 1us". huh?
 288  */
 289 #define SA2400_TX_RAMP_MASK     BITS(9, 8)
 290 /*
 291  * Transmitter gain settings
 292  * for TXHI output
 293  */
 294 #define SA2400_TX_HIGAIN_MASK   BITS(7, 4)
 295 /*
 296  * Transmitter gain settings
 297  * for TXLO output
 298  */
 299 #define SA2400_TX_LOGAIN_MASK   BITS(3, 0)
 300
 301 #define SA2400_VCO      8                       /* VCO settings */
 302 #define SA2400_VCO_ZERO         BITS(6, 5)      /* always zero */
 303 /*
 304  * VCO calibration error flag---no
 305  * band with low enough frequency
 306  * could be found
 307  */
 308 #define SA2400_VCO_VCERR        BIT(4)
 309 /*
 310  * VCO band,
 311  * write: in test mode, sets
 312  *        VCO band
 313  * read:  in normal mode,
 314  *        the result of
 315  *        calibration (VCOCAL).
 316  *        0 = highest
 317  *        frequencies
 318  */
 319 #define SA2400_VCO_VCOBAND_MASK BITS(3, 0)
 320 #ifdef __cplusplus
 321 }
 322 #endif
 323
 324 #endif /* _SA2400REG_H_ */