usr/src/uts/sun/sys/scsi/adapters/espreg.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License, Version 1.0 only
   6  * (the "License").  You may not use this file except in compliance
   7  * with the License.
   8  *
   9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  10  * or http://www.opensolaris.org/os/licensing.
  11  * See the License for the specific language governing permissions
  12  * and limitations under the License.
  13  *
  14  * When distributing Covered Code, include this CDDL HEADER in each
  15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  16  * If applicable, add the following below this CDDL HEADER, with the
  17  * fields enclosed by brackets "[]" replaced with your own identifying
  18  * information: Portions Copyright [yyyy] [name of copyright owner]
  19  *
  20  * CDDL HEADER END
  21  */
  22 /*
  23  * Copyright (c) 1996-1998 by Sun Microsystems, Inc.
  24  * All rights reserved.
  25  */
  26
  27 #ifndef _SYS_SCSI_ADAPTERS_ESPREG_H
  28 #define _SYS_SCSI_ADAPTERS_ESPREG_H
  29
  30 #pragma ident   "%Z%%M% %I%     %E% SMI"
  31
  32 /*
  33  * Hardware definitions for ESP (Enhanced SCSI Processor) generation chips.
  34  */
  35
  36 /*
  37  * Include definition of DMA, DMA+, and ESC gate arrays
  38  */
  39
  40 #include <sys/dmaga.h>
  41
  42 #ifdef  __cplusplus
  43 extern "C" {
  44 #endif
  45
  46 /*
  47  * ESP register definitions.
  48  */
  49
  50 /*
  51  * All current Sun implementations use the following layout.
  52  * That is, the ESP registers are always byte-wide, but are
  53  * accessed 32-bit words apart. Notice also that the byte-ordering
  54  * is big-endian.
  55  */
  56
  57 struct espreg {
  58         uint8_t esp_xcnt_lo;            /* RW: transfer counter (low byte) */
  59                                         uint8_t _pad1, _pad2, _pad3;
  60
  61         uint8_t esp_xcnt_mid;           /* RW: transfer counter (mid byte) */
  62                                         uint8_t _pad5, _pad6, _pad7;
  63
  64         uint8_t esp_fifo_data;          /* RW: fifo data buffer */
  65                                         uint8_t _pad9, _pad10, _pad11;
  66
  67         uint8_t esp_cmd;                /* RW: command register */
  68                                         uint8_t _pad13, _pad14, _pad15;
  69
  70         uint8_t esp_stat;               /* R: status register */
  71 #define esp_busid       esp_stat        /* W: bus id for sel/resel */
  72                                         uint8_t _pad17, _pad18, _pad19;
  73
  74
  75         uint8_t esp_intr;               /* R: interrupt status register */
  76 #define esp_timeout     esp_intr        /* W: sel/resel timeout */
  77                                         uint8_t _pad21, _pad22, _pad23;
  78
  79
  80         uint8_t esp_step;               /* R: sequence step register */
  81 #define esp_sync_period esp_step        /* W: synchronous period */
  82                                         uint8_t _pad25, _pad26, _pad27;
  83
  84
  85         uint8_t esp_fifo_flag;          /* R: fifo flag register */
  86 #define esp_sync_offset esp_fifo_flag   /* W: synchronous offset */
  87                                         uint8_t _pad29, _pad30, _pad31;
  88
  89
  90         uint8_t esp_conf;               /* RW: configuration register */
  91                                         uint8_t _pad33, _pad34, _pad35;
  92
  93
  94         uint8_t esp_clock_conv;         /* W: clock conversion register */
  95                                         uint8_t _pad37, _pad38, _pad39;
  96
  97
  98         uint8_t esp_test;               /* RW: test register */
  99                                         uint8_t _pad41, _pad42, _pad43;
 100
 101
 102         uint8_t esp_conf2;              /* ESP-II configuration register */
 103                                         uint8_t _pad45, _pad46, _pad47;
 104
 105         uint8_t esp_conf3;              /* ESP-III configuration register */
 106                                         uint8_t _pad49, _pad50, _pad51;
 107
 108                                         uint8_t _pad52, _pad53, _pad54, _pad55;
 109
 110         uint8_t esp_xcnt_hi;            /* RW: transfer counter (hi byte) */
 111 #define esp_id_code esp_xcnt_hi         /* R: part-unique id code */
 112                                         uint8_t _pad57, _pad58, _pad59;
 113
 114         uint8_t esp_fifo_bottom;        /* RW: fifo data bottom */
 115                                         uint8_t _pad61, _pad62, _pad63;
 116 };
 117
 118
 119 /*
 120  * ESP command register definitions
 121  */
 122
 123 /*
 124  * These commands may be used at any time with the ESP chip.
 125  * None generate an interrupt, per se, although if you have
 126  * enabled detection of SCSI reset in setting the configuration
 127  * register, a CMD_RESET_SCSI will generate an interrupt.
 128  * Therefore, it is recommended that if you use the CMD_RESET_SCSI
 129  * command, you at least temporarily disable recognition of
 130  * SCSI reset in the configuration register.
 131  */
 132
 133 #define CMD_NOP         0x0
 134 #define CMD_FLUSH       0x1
 135 #define CMD_RESET_ESP   0x2
 136 #define CMD_RESET_SCSI  0x3
 137
 138 /*
 139  * These commands will only work if the ESP is in the
 140  * 'disconnected' state:
 141  */
 142
 143 #define CMD_RESEL_SEQ   0x40
 144 #define CMD_SEL_NOATN   0x41
 145 #define CMD_SEL_ATN     0x42
 146 #define CMD_SEL_STOP    0x43
 147 #define CMD_EN_RESEL    0x44    /* (no interrupt generated) */
 148 #define CMD_DIS_RESEL   0x45
 149 #define CMD_SEL_ATN3    0x46    /* (ESP100A/200, ESP236 only) */
 150
 151 /*
 152  * These commands will only work if the ESP is connected as
 153  * an initiator to a target:
 154  */
 155
 156 #define CMD_TRAN_INFO   0x10
 157 #define CMD_COMP_SEQ    0x11
 158 #define CMD_MSG_ACPT    0x12
 159 #define CMD_TRAN_PAD    0x18
 160 #define CMD_SET_ATN     0x1a    /* (no interrupt generated) */
 161 #define CMD_CLR_ATN     0x1b    /* (no interrupt generated) (ESP236 only) */
 162
 163 /*
 164  * These commands will only work if the ESP is connected as
 165  * a target to an initiator:
 166  */
 167 #define CMD_DISCONNECT  0x27    /* (no interrupt generated) */
 168
 169 /*
 170  * DMA enable bit
 171  */
 172
 173 #define CMD_DMA         0x80
 174
 175 /*
 176  * ESP fifo register definitions (read only)
 177  *
 178  * The first four bits are the count of bytes
 179  * in the fifo.
 180  *
 181  * Bit 5 is a 'offset counter not zero' flag for
 182  * the ESP100 only. On the ESP100A, the top 3 bits
 183  * of the fifo register are the 3 bits of the Sequence
 184  * Step register (if the ESP100A is not in TEST mode.
 185  * If the ESP100A is in TEST mode, then bit 5 has
 186  * the 'offset counter not zero' function). At least,
 187  * so states the documentation.
 188  *
 189  */
 190
 191 #define FIFOSIZE                16
 192 #define MAX_FIFO_FLAG           (FIFOSIZE-1)
 193 #define ESP_FIFO_ONZ            0x20
 194
 195
 196 /*
 197  * ESP status register definitions (read only)
 198  */
 199
 200 #define ESP_STAT_RES    0x80    /* reserved (ESP100, ESP100A) */
 201 #define ESP_STAT_IPEND  0x80    /* interrupt pending (ESP-236 only) */
 202 #define ESP_STAT_GERR   0x40    /* gross error */
 203 #define ESP_STAT_PERR   0x20    /* parity error */
 204 #define ESP_STAT_XZERO  0x10    /* transfer counter zero */
 205 #define ESP_STAT_XCMP   0x8     /* transfer completed (target mode only) */
 206 #define ESP_STAT_MSG    0x4     /* scsi phase bit: MSG */
 207 #define ESP_STAT_CD     0x2     /* scsi phase bit: CD */
 208 #define ESP_STAT_IO     0x1     /* scsi phase bit: IO */
 209
 210 #define ESP_STAT_BITS   \
 211         "\20\10IPND\07GERR\06PERR\05XZERO\04XCMP\03MSG\02CD\01IO"
 212
 213 /*
 214  * settings of status to reflect different information transfer phases
 215  */
 216
 217 #define ESP_PHASE_MASK          (ESP_STAT_MSG | ESP_STAT_CD | ESP_STAT_IO)
 218 #define ESP_PHASE_DATA_OUT      0
 219 #define ESP_PHASE_DATA_IN       (ESP_STAT_IO)
 220 #define ESP_PHASE_COMMAND       (ESP_STAT_CD)
 221 #define ESP_PHASE_STATUS        (ESP_STAT_CD | ESP_STAT_IO)
 222 #define ESP_PHASE_MSG_OUT       (ESP_STAT_MSG | ESP_STAT_CD)
 223 #define ESP_PHASE_MSG_IN        (ESP_STAT_MSG | ESP_STAT_CD | ESP_STAT_IO)
 224
 225 /*
 226  * ESP interrupt status register definitions (read only)
 227  */
 228
 229 #define ESP_INT_RESET   0x80    /* SCSI reset detected */
 230 #define ESP_INT_ILLEGAL 0x40    /* illegal cmd */
 231 #define ESP_INT_DISCON  0x20    /* disconnect */
 232 #define ESP_INT_BUS     0x10    /* bus service */
 233 #define ESP_INT_FCMP    0x8     /* function completed */
 234 #define ESP_INT_RESEL   0x4     /* reselected */
 235 #define ESP_INT_SELATN  0x2     /* selected with ATN */
 236 #define ESP_INT_SEL     0x1     /* selected without ATN */
 237
 238 #define ESP_INT_BITS    \
 239         "\20\10RST\07ILL\06DISC\05BUS\04FCMP\03RESEL\02SATN\01SEL"
 240
 241 /*
 242  * ESP step register- only the least significant 3 bits are valid
 243  */
 244
 245 #define ESP_STEP_MASK   0x7
 246
 247 #define ESP_STEP_ARBSEL 0       /* Arbitration and select completed. */
 248                                 /* Not MESSAGE OUT phase. ATN* asserted. */
 249
 250 #define ESP_STEP_SENTID 1       /* Sent one message byte. ATN* asserted. */
 251                                 /* (SELECT AND STOP command only). */
 252
 253 #define ESP_STEP_NOTCMD 2       /* For SELECT WITH ATN command: */
 254                                 /*      Sent one message byte. ATN* off. */
 255                                 /*      Not COMMAND phase. */
 256                                 /* For SELECT WITHOUT ATN command: */
 257                                 /*      Not COMMAND phase. */
 258                                 /* For SELECT WITH ATN3 command: */
 259                                 /*      Sent one to three message bytes. */
 260                                 /*      Stopped due to unexpected phase */
 261                                 /*      change. If third message byte */
 262                                 /*      not sent, ATN* asserted.  */
 263
 264 #define ESP_STEP_PCMD   3       /* Not all of command bytes transferred */
 265                                 /* due to premature phase change. */
 266
 267 #define ESP_STEP_DONE   4       /* Complete sequence. */
 268 #define ESP_STEP_DONE5  5       /* Sometimes 5,6,7 occur on FAS101 instead */
 269 #define ESP_STEP_DONE6  6       /* of step == 4 due to flaky signals or */
 270 #define ESP_STEP_DONE7  7       /* bug in the chip */
 271
 272
 273 /*
 274  * ESP configuration register definitions (read/write)
 275  */
 276
 277 #define ESP_CONF_SLOWMODE       0x80    /* slow cable mode */
 278 #define ESP_CONF_DISRINT        0x40    /* disable reset int */
 279 #define ESP_CONF_PARTEST        0x20    /* parity test mode */
 280 #define ESP_CONF_PAREN          0x10    /* enable parity */
 281 #define ESP_CONF_CHIPTEST       0x8     /* chip test mode */
 282 #define ESP_CONF_BUSID          0x7     /* last 3 bits to be host id */
 283
 284 #define DEFAULT_HOSTID          7
 285
 286 /*
 287  * ESP test register definitions (read/write)
 288  */
 289
 290 #define ESP_TEST_TGT            0x1     /* target test mode */
 291 #define ESP_TEST_INI            0x2     /* initiator test mode */
 292 #define ESP_TEST_TRI            0x4     /* tristate test mode */
 293
 294 /*
 295  * ESP configuration register #2 definitions (read/write)
 296  * (ESP100A, ESP200, or ESP236 only)
 297  */
 298
 299 #define ESP_CONF2_RESETF        0x80    /* Reserve FIFO byte (ESP-236 only) */
 300
 301 #define ESP_CONF2_FENABLE       0x40    /* Features Enable (FAS100,216 only) */
 302
 303 #define ESP_CONF2_STATPL        0x40    /* Enable Status Phase Latch */
 304                                         /* (ESP-236 only) */
 305
 306 #define ESP_CONF2_BYTECM        0x20    /* Enable Byte Control Mode */
 307                                         /* (ESP-236 only) */
 308
 309 #define ESP_CONF2_TRIDMA        0x10    /* Tristate DMA REQ */
 310 #define ESP_CONF2_SCSI2         0x8     /* SCSI-2 mode (target mode only) */
 311 #define ESP_CONF2_TBADPAR       0x4     /* Target Bad Parity Abort */
 312
 313 #define ESP_CONF2_REGPAR        0x2     /* Register Parity Enable */
 314                                         /* (ESP200, ESP236 only) */
 315
 316 #define ESP_CONF2_DMAPAR        0x1     /* DMA parity enable */
 317                                         /* (ESP200, ESP236 only) */
 318
 319 /*
 320  * ESP configuration #3 register definitions (read/write)
 321  * (ESP236, FAS236, and FAS100A)
 322  * Unfortunately, emulex has not been very consistent here
 323  */
 324
 325 #define ESP_CONF3_236_IDRESCHK  0x80    /* ID message checking */
 326 #define ESP_CONF3_236_QUENB     0x40    /* 3-byte msg support */
 327 #define ESP_CONF3_236_CDB10     0x20    /* group 2 scsi-2 support */
 328 #define ESP_CONF3_236_FASTSCSI  0x10    /* 10 MB/S fast scsi mode */
 329 #define ESP_CONF3_236_FASTCLK   0x8     /* fast clock mode */
 330 #define ESP_CONF3_236_SAVERESB  0x4     /* save residual byte */
 331 #define ESP_CONF3_236_ALTDMA    0x2     /* enable alternate DMA mode */
 332 #define ESP_CONF3_236_THRESH8   0x1     /* enable threshold-8 mode */
 333
 334 #define ESP_CONF3_100A_IDRESCHK 0x10    /* ID message checking */
 335 #define ESP_CONF3_100A_QUENB    0x8     /* 3-byte msg support */
 336 #define ESP_CONF3_100A_CDB10    0x4     /* group 2 scsi-2 support */
 337 #define ESP_CONF3_100A_FASTSCSI 0x2     /* 10 MB/S fast scsi mode */
 338 #define ESP_CONF3_100A_FASTCLK  0x1     /* fast clock mode */
 339
 340
 341 /*
 342  * ESP part-unique id code definitions (read only)
 343  * (FAS236 and FAS100A only)
 344  */
 345
 346 #define ESP_FAS100A             0x0     /* chip family code 0 */
 347 #define ESP_FAS236              0x2     /* chip family code 2 */
 348 #define ESP_REV_MASK            0x7     /* revision level mask */
 349 #define ESP_FCODE_MASK          0xf8    /* revision family code mask */
 350
 351
 352 /*
 353  * Macros to get/set an integer (long or short) word into the 2 or 3  8-bit
 354  * registers that constitute the ESP's counter register.
 355  */
 356
 357 #define SET_ESP_COUNT_16(ep, val)       \
 358         (ep)->esp_xcnt_lo = (uint8_t)(val), \
 359         (ep)->esp_xcnt_mid = (uint8_t)((val) >> 8)
 360 #define GET_ESP_COUNT_16(ep, val)       \
 361         (val) = (uint32_t)(ep)->esp_xcnt_lo |\
 362         (((uint32_t)(ep)->esp_xcnt_mid) << 8)
 363 #define SET_ESP_COUNT_24(ep, val)       \
 364         (ep)->esp_xcnt_lo = (uint8_t)(val), \
 365         (ep)->esp_xcnt_mid = (uint8_t)((val) >> 8), \
 366         (ep)->esp_xcnt_hi = (uint8_t)((val) >> 16)
 367 #define GET_ESP_COUNT_24(ep, val)       \
 368         (val) = (uint32_t)(ep)->esp_xcnt_lo | \
 369         (((uint32_t)(ep)->esp_xcnt_mid) << 8) | \
 370         (((uint32_t)(ep)->esp_xcnt_hi) << 16)
 371
 372 #define GET_ESP_COUNT(ep, val)  \
 373         if (esp->e_espconf2 & ESP_CONF2_FENABLE) \
 374                 GET_ESP_COUNT_24(ep, val); \
 375         else \
 376                 GET_ESP_COUNT_16(ep, val);
 377
 378 #define SET_ESP_COUNT(ep, val)  \
 379         if (esp->e_espconf2 & ESP_CONF2_FENABLE) \
 380                 SET_ESP_COUNT_24(ep, val); \
 381         else \
 382                 SET_ESP_COUNT_16(ep, val);
 383
 384 /*
 385  * The counter is a 16 bit counter only for the ESP.
 386  * If loaded with zero, it will do the full 64kb. If
 387  * we define maxcount to be 64kb, then the low order
 388  * 16 bits will be zero, and the register will be
 389  * properly loaded.
 390  * For FAS chips we can use the 24 bit counter
 391  */
 392 #define ESP_MAX_DMACOUNT \
 393         ((esp->e_espconf2 & ESP_CONF2_FENABLE) ? 0x1000000 : 0x10000)
 394
 395 /*
 396  * ESP Clock constants
 397  */
 398
 399 /*
 400  * The probe routine will select amongst these values
 401  * and stuff it into the tag e_clock_conv in the private host
 402  * adapter structure (see below) (as well as the the register esp_clock_conv
 403  * on the chip)
 404  */
 405
 406 #define CLOCK_10MHZ             2
 407 #define CLOCK_15MHZ             3
 408 #define CLOCK_20MHZ             4
 409 #define CLOCK_25MHZ             5
 410 #define CLOCK_30MHZ             6
 411 #define CLOCK_35MHZ             7
 412 #define CLOCK_40MHZ             8       /* really 0 */
 413 #define CLOCK_MASK              0x7
 414
 415 /*
 416  * This yields nanoseconds per input clock tick
 417  */
 418
 419 #define CLOCK_PERIOD(mhz)       (1000 * MEG) / (mhz / 1000)
 420 #define CONVERT_PERIOD(time)    ((time) + 3) >> 2
 421
 422 /*
 423  * Formula to compute the select/reselect timeout register value:
 424  *
 425  *      Time_unit = 7682 * CCF * Input_Clock_Period
 426  *
 427  * where Time_unit && Input_Clock_Period should be in the same units.
 428  * CCF = Clock Conversion Factor from CLOCK_XMHZ above.
 429  * Desired_Timeout_Period = 250 ms.
 430  *
 431  */
 432
 433 #define ESP_CLOCK_DELAY 7682
 434 #define ESP_CLOCK_TICK(esp)     \
 435         ((uint_t)ESP_CLOCK_DELAY * (uint_t)(esp)->e_clock_conv * \
 436         (uint_t)(esp)->e_clock_cycle) / (uint_t)1000
 437 #define ESP_SEL_TIMEOUT (250 * MEG)
 438 #define ESP_CLOCK_TIMEOUT(tick, selection_timeout) \
 439         (((selection_timeout) * MEG) + (tick) - 1) / (tick)
 440
 441 /*
 442  * Max/Min number of clock cycles for synchronous period
 443  */
 444
 445 #define MIN_SYNC_FAST(esp)      4
 446 #define MIN_SYNC_SLOW(esp)      \
 447         (((esp)->e_espconf & ESP_CONF_SLOWMODE)? 5 : 4)
 448 #define MIN_SYNC(esp)   \
 449         (((esp)->e_options & ESP_OPT_FAS) ? \
 450         (MIN_SYNC_FAST((esp))) :  (MIN_SYNC_SLOW((esp))))
 451 #define MAX_SYNC(esp)           35
 452 #define SYNC_PERIOD_MASK        0x1F
 453
 454 /*
 455  * Max/Min time (in nanoseconds) between successive Req/Ack
 456  */
 457
 458 #define MIN_SYNC_TIME(esp)      \
 459         ((uint_t)MIN_SYNC((esp)) * (uint_t)((esp)->e_clock_cycle)) / \
 460             (uint_t)1000
 461 #define MAX_SYNC_TIME(esp)      \
 462         ((uint_t)MAX_SYNC((esp)) * (uint_t)((esp)->e_clock_cycle)) / \
 463             (uint_t)1000
 464
 465 /*
 466  * Max/Min Period values (appropriate for SYNCHRONOUS message).
 467  * We round up here to make sure that we are always slower
 468  * (longer time period).
 469  */
 470
 471 #define MIN_SYNC_PERIOD(esp)    (CONVERT_PERIOD(MIN_SYNC_TIME((esp))))
 472 #define MAX_SYNC_PERIOD(esp)    (CONVERT_PERIOD(MAX_SYNC_TIME((esp))))
 473
 474 /*
 475  * According to the Emulex application notes for this part,
 476  * the ability to receive synchronous data is independent
 477  * of the ESP chip's input clock rate, and is fixed at
 478  * a maximum 5.6 mb/s (180 ns/byte).
 479  *
 480  * Therefore, we could tell targets that we can *receive*
 481  * synchronous data this fast.
 482  * However, the rest of the transfer is still at 5.0 MB/sec so to keep it
 483  * simple, we negotiate 200 ns
 484  * On a c2,  a period of 45 and 50 result in the same register value (8) and
 485  * consequently 5 MB/sec.
 486  */
 487
 488 #define DEFAULT_SYNC_PERIOD             200             /* 5.0 MB/s */
 489 #define DEFAULT_FASTSYNC_PERIOD         100             /* 10.0 MB/s */
 490
 491 #define FASTSCSI_THRESHOLD              50              /* 5.0 MB/s */
 492
 493
 494 /*
 495  * Short hand macro convert parameter in
 496  * nanoseconds/byte into k-bytes/second.
 497  */
 498
 499 #define ESP_SYNC_KBPS(ns)       ((((1000 * MEG) / (ns)) + 999) / 1000)
 500
 501
 502 /*
 503  * Default Synchronous offset.
 504  * (max # of allowable outstanding REQ)
 505  */
 506
 507 #define DEFAULT_OFFSET  15
 508
 509 /*
 510  * Chip type defines && macros
 511  */
 512
 513 #define ESP100          0
 514 #define NCR53C90        0
 515 #define ESP100A         1
 516 #define NCR53C90A       1
 517 #define ESP236          2
 518 #define FAS100          3
 519 #define FAS100A         3
 520 #define FAS236          4
 521 #define FAST            5
 522
 523 #define IS_53C90(esp)   ((esp)->e_type == NCR53C90)
 524
 525 /*
 526  * Compatibility hacks
 527  */
 528
 529 #define ESP_SIZE                0x2000          /* ESP and DVMA space */
 530
 531 #define DMAGA_OFFSET            0x1000          /* Offset of DMA registers */
 532                                                 /* for STINGRAY && HYDRA. */
 533
 534 #ifdef  __cplusplus
 535 }
 536 #endif
 537
 538 #endif  /* _SYS_SCSI_ADAPTERS_ESPREG_H */