4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
30 /* IntelVersion: 1.161 v3_3_14_3_BHSW1 */
34 static s32
e1000_copper_link_autoneg(struct e1000_hw
*hw
);
35 static s32
e1000_phy_setup_autoneg(struct e1000_hw
*hw
);
37 /* Cable length tables */
38 static const u16 e1000_m88_cable_length_table
[] =
39 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
};
41 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
42 (sizeof (e1000_m88_cable_length_table) / \
43 sizeof (e1000_m88_cable_length_table[0]))
45 static const u16 e1000_igp_2_cable_length_table
[] =
46 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
47 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
48 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
49 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
50 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
51 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
52 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
53 104, 109, 114, 118, 121, 124};
55 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
56 (sizeof (e1000_igp_2_cable_length_table) / \
57 sizeof (e1000_igp_2_cable_length_table[0]))
60 * e1000_init_phy_ops_generic - Initialize PHY function pointers
61 * @hw: pointer to the HW structure
63 * Setups up the function pointers to no-op functions
66 e1000_init_phy_ops_generic(struct e1000_hw
*hw
)
68 struct e1000_phy_info
*phy
= &hw
->phy
;
69 DEBUGFUNC("e1000_init_phy_ops_generic");
71 /* Initialize function pointers */
72 phy
->ops
.init_params
= e1000_null_ops_generic
;
73 phy
->ops
.acquire
= e1000_null_ops_generic
;
74 phy
->ops
.check_polarity
= e1000_null_ops_generic
;
75 phy
->ops
.check_reset_block
= e1000_null_ops_generic
;
76 phy
->ops
.commit
= e1000_null_ops_generic
;
77 phy
->ops
.force_speed_duplex
= e1000_null_ops_generic
;
78 phy
->ops
.get_cfg_done
= e1000_null_ops_generic
;
79 phy
->ops
.get_cable_length
= e1000_null_ops_generic
;
80 phy
->ops
.get_info
= e1000_null_ops_generic
;
81 phy
->ops
.read_reg
= e1000_null_read_reg
;
82 phy
->ops
.read_reg_locked
= e1000_null_read_reg
;
83 phy
->ops
.release
= e1000_null_phy_generic
;
84 phy
->ops
.reset
= e1000_null_ops_generic
;
85 phy
->ops
.set_d0_lplu_state
= e1000_null_lplu_state
;
86 phy
->ops
.set_d3_lplu_state
= e1000_null_lplu_state
;
87 phy
->ops
.write_reg
= e1000_null_write_reg
;
88 phy
->ops
.write_reg_locked
= e1000_null_write_reg
;
89 phy
->ops
.power_up
= e1000_null_phy_generic
;
90 phy
->ops
.power_down
= e1000_null_phy_generic
;
94 * e1000_null_read_reg - No-op function, return 0
95 * @hw: pointer to the HW structure
98 e1000_null_read_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
100 DEBUGFUNC("e1000_null_read_reg");
101 UNREFERENCED_3PARAMETER(hw
, offset
, data
);
102 return (E1000_SUCCESS
);
106 * e1000_null_phy_generic - No-op function, return void
107 * @hw: pointer to the HW structure
110 e1000_null_phy_generic(struct e1000_hw
*hw
)
112 DEBUGFUNC("e1000_null_phy_generic");
113 UNREFERENCED_1PARAMETER(hw
);
117 * e1000_null_lplu_state - No-op function, return 0
118 * @hw: pointer to the HW structure
121 e1000_null_lplu_state(struct e1000_hw
*hw
, bool active
)
123 DEBUGFUNC("e1000_null_lplu_state");
124 UNREFERENCED_2PARAMETER(hw
, active
);
125 return (E1000_SUCCESS
);
129 * e1000_null_write_reg - No-op function, return 0
130 * @hw: pointer to the HW structure
133 e1000_null_write_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
)
135 DEBUGFUNC("e1000_null_write_reg");
136 UNREFERENCED_3PARAMETER(hw
, offset
, data
);
137 return (E1000_SUCCESS
);
141 * e1000_check_reset_block_generic - Check if PHY reset is blocked
142 * @hw: pointer to the HW structure
144 * Read the PHY management control register and check whether a PHY reset
145 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
146 * return E1000_BLK_PHY_RESET (12).
149 e1000_check_reset_block_generic(struct e1000_hw
*hw
)
153 DEBUGFUNC("e1000_check_reset_block");
155 manc
= E1000_READ_REG(hw
, E1000_MANC
);
157 return (manc
& E1000_MANC_BLK_PHY_RST_ON_IDE
) ?
158 E1000_BLK_PHY_RESET
: E1000_SUCCESS
;
162 * e1000_get_phy_id - Retrieve the PHY ID and revision
163 * @hw: pointer to the HW structure
165 * Reads the PHY registers and stores the PHY ID and possibly the PHY
166 * revision in the hardware structure.
169 e1000_get_phy_id(struct e1000_hw
*hw
)
171 struct e1000_phy_info
*phy
= &hw
->phy
;
172 s32 ret_val
= E1000_SUCCESS
;
175 DEBUGFUNC("e1000_get_phy_id");
177 if (!(phy
->ops
.read_reg
))
180 ret_val
= phy
->ops
.read_reg(hw
, PHY_ID1
, &phy_id
);
184 phy
->id
= (u32
)(phy_id
<< 16);
186 ret_val
= phy
->ops
.read_reg(hw
, PHY_ID2
, &phy_id
);
190 phy
->id
|= (u32
)(phy_id
& PHY_REVISION_MASK
);
191 phy
->revision
= (u32
)(phy_id
& ~PHY_REVISION_MASK
);
198 * e1000_phy_reset_dsp_generic - Reset PHY DSP
199 * @hw: pointer to the HW structure
201 * Reset the digital signal processor.
204 e1000_phy_reset_dsp_generic(struct e1000_hw
*hw
)
206 s32 ret_val
= E1000_SUCCESS
;
208 DEBUGFUNC("e1000_phy_reset_dsp_generic");
210 if (!(hw
->phy
.ops
.write_reg
))
213 ret_val
= hw
->phy
.ops
.write_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xC1);
217 ret_val
= hw
->phy
.ops
.write_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0);
224 * e1000_read_phy_reg_mdic - Read MDI control register
225 * @hw: pointer to the HW structure
226 * @offset: register offset to be read
227 * @data: pointer to the read data
229 * Reads the MDI control register in the PHY at offset and stores the
230 * information read to data.
233 e1000_read_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
235 struct e1000_phy_info
*phy
= &hw
->phy
;
237 s32 ret_val
= E1000_SUCCESS
;
239 DEBUGFUNC("e1000_read_phy_reg_mdic");
242 * Set up Op-code, Phy Address, and register offset in the MDI
243 * Control register. The MAC will take care of interfacing with the
244 * PHY to retrieve the desired data.
246 mdic
= ((offset
<< E1000_MDIC_REG_SHIFT
) |
247 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
248 (E1000_MDIC_OP_READ
));
250 E1000_WRITE_REG(hw
, E1000_MDIC
, mdic
);
253 * Poll the ready bit to see if the MDI read completed
254 * Increasing the time out as testing showed failures with
257 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
259 mdic
= E1000_READ_REG(hw
, E1000_MDIC
);
260 if (mdic
& E1000_MDIC_READY
)
263 if (!(mdic
& E1000_MDIC_READY
)) {
264 DEBUGOUT("MDI Read did not complete\n");
265 ret_val
= -E1000_ERR_PHY
;
268 if (mdic
& E1000_MDIC_ERROR
) {
269 DEBUGOUT("MDI Error\n");
270 ret_val
= -E1000_ERR_PHY
;
280 * e1000_write_phy_reg_mdic - Write MDI control register
281 * @hw: pointer to the HW structure
282 * @offset: register offset to write to
283 * @data: data to write to register at offset
285 * Writes data to MDI control register in the PHY at offset.
288 e1000_write_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16 data
)
290 struct e1000_phy_info
*phy
= &hw
->phy
;
292 s32 ret_val
= E1000_SUCCESS
;
294 DEBUGFUNC("e1000_write_phy_reg_mdic");
297 * Set up Op-code, Phy Address, and register offset in the MDI
298 * Control register. The MAC will take care of interfacing with the
299 * PHY to retrieve the desired data.
301 mdic
= (((u32
)data
) |
302 (offset
<< E1000_MDIC_REG_SHIFT
) |
303 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
304 (E1000_MDIC_OP_WRITE
));
306 E1000_WRITE_REG(hw
, E1000_MDIC
, mdic
);
309 * Poll the ready bit to see if the MDI read completed
310 * Increasing the time out as testing showed failures with
313 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
315 mdic
= E1000_READ_REG(hw
, E1000_MDIC
);
316 if (mdic
& E1000_MDIC_READY
)
319 if (!(mdic
& E1000_MDIC_READY
)) {
320 DEBUGOUT("MDI Write did not complete\n");
321 ret_val
= -E1000_ERR_PHY
;
324 if (mdic
& E1000_MDIC_ERROR
) {
325 DEBUGOUT("MDI Error\n");
326 ret_val
= -E1000_ERR_PHY
;
335 * e1000_read_phy_reg_i2c - Read PHY register using i2c
336 * @hw: pointer to the HW structure
337 * @offset: register offset to be read
338 * @data: pointer to the read data
340 * Reads the PHY register at offset using the i2c interface and stores the
341 * retrieved information in data.
344 e1000_read_phy_reg_i2c(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
346 struct e1000_phy_info
*phy
= &hw
->phy
;
349 DEBUGFUNC("e1000_read_phy_reg_i2c");
352 * Set up Op-code, Phy Address, and register address in the I2CCMD
353 * register. The MAC will take care of interfacing with the
354 * PHY to retrieve the desired data.
356 i2ccmd
= ((offset
<< E1000_I2CCMD_REG_ADDR_SHIFT
) |
357 (phy
->addr
<< E1000_I2CCMD_PHY_ADDR_SHIFT
) |
358 (E1000_I2CCMD_OPCODE_READ
));
360 E1000_WRITE_REG(hw
, E1000_I2CCMD
, i2ccmd
);
362 /* Poll the ready bit to see if the I2C read completed */
363 for (i
= 0; i
< E1000_I2CCMD_PHY_TIMEOUT
; i
++) {
365 i2ccmd
= E1000_READ_REG(hw
, E1000_I2CCMD
);
366 if (i2ccmd
& E1000_I2CCMD_READY
)
369 if (!(i2ccmd
& E1000_I2CCMD_READY
)) {
370 DEBUGOUT("I2CCMD Read did not complete\n");
371 return (-E1000_ERR_PHY
);
373 if (i2ccmd
& E1000_I2CCMD_ERROR
) {
374 DEBUGOUT("I2CCMD Error bit set\n");
375 return (-E1000_ERR_PHY
);
378 /* Need to byte-swap the 16-bit value. */
379 *data
= ((i2ccmd
>> 8) & 0x00FF) | ((i2ccmd
<< 8) & 0xFF00);
381 return (E1000_SUCCESS
);
385 * e1000_write_phy_reg_i2c - Write PHY register using i2c
386 * @hw: pointer to the HW structure
387 * @offset: register offset to write to
388 * @data: data to write at register offset
390 * Writes the data to PHY register at the offset using the i2c interface.
393 e1000_write_phy_reg_i2c(struct e1000_hw
*hw
, u32 offset
, u16 data
)
395 struct e1000_phy_info
*phy
= &hw
->phy
;
397 u16 phy_data_swapped
;
399 DEBUGFUNC("e1000_write_phy_reg_i2c");
401 /* Swap the data bytes for the I2C interface */
402 phy_data_swapped
= ((data
>> 8) & 0x00FF) | ((data
<< 8) & 0xFF00);
405 * Set up Op-code, Phy Address, and register address in the I2CCMD
406 * register. The MAC will take care of interfacing with the
407 * PHY to retrieve the desired data.
409 i2ccmd
= ((offset
<< E1000_I2CCMD_REG_ADDR_SHIFT
) |
410 (phy
->addr
<< E1000_I2CCMD_PHY_ADDR_SHIFT
) |
411 E1000_I2CCMD_OPCODE_WRITE
|
414 E1000_WRITE_REG(hw
, E1000_I2CCMD
, i2ccmd
);
416 /* Poll the ready bit to see if the I2C read completed */
417 for (i
= 0; i
< E1000_I2CCMD_PHY_TIMEOUT
; i
++) {
419 i2ccmd
= E1000_READ_REG(hw
, E1000_I2CCMD
);
420 if (i2ccmd
& E1000_I2CCMD_READY
)
423 if (!(i2ccmd
& E1000_I2CCMD_READY
)) {
424 DEBUGOUT("I2CCMD Write did not complete\n");
425 return (-E1000_ERR_PHY
);
427 if (i2ccmd
& E1000_I2CCMD_ERROR
) {
428 DEBUGOUT("I2CCMD Error bit set\n");
429 return (-E1000_ERR_PHY
);
432 return (E1000_SUCCESS
);
436 * e1000_read_phy_reg_m88 - Read m88 PHY register
437 * @hw: pointer to the HW structure
438 * @offset: register offset to be read
439 * @data: pointer to the read data
441 * Acquires semaphore, if necessary, then reads the PHY register at offset
442 * and storing the retrieved information in data. Release any acquired
443 * semaphores before exiting.
446 e1000_read_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
448 s32 ret_val
= E1000_SUCCESS
;
450 DEBUGFUNC("e1000_read_phy_reg_m88");
452 if (!(hw
->phy
.ops
.acquire
))
455 ret_val
= hw
->phy
.ops
.acquire(hw
);
459 ret_val
= e1000_read_phy_reg_mdic(hw
,
460 MAX_PHY_REG_ADDRESS
& offset
, data
);
462 hw
->phy
.ops
.release(hw
);
469 * e1000_write_phy_reg_m88 - Write m88 PHY register
470 * @hw: pointer to the HW structure
471 * @offset: register offset to write to
472 * @data: data to write at register offset
474 * Acquires semaphore, if necessary, then writes the data to PHY register
475 * at the offset. Release any acquired semaphores before exiting.
478 e1000_write_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16 data
)
480 s32 ret_val
= E1000_SUCCESS
;
482 DEBUGFUNC("e1000_write_phy_reg_m88");
484 if (!(hw
->phy
.ops
.acquire
))
487 ret_val
= hw
->phy
.ops
.acquire(hw
);
491 ret_val
= e1000_write_phy_reg_mdic(hw
,
492 MAX_PHY_REG_ADDRESS
& offset
, data
);
494 hw
->phy
.ops
.release(hw
);
501 * __e1000_read_phy_reg_igp - Read igp PHY register
502 * @hw: pointer to the HW structure
503 * @offset: register offset to be read
504 * @data: pointer to the read data
505 * @locked: semaphore has already been acquired or not
507 * Acquires semaphore, if necessary, then reads the PHY register at offset
508 * and stores the retrieved information in data. Release any acquired
509 * semaphores before exiting.
512 __e1000_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
515 s32 ret_val
= E1000_SUCCESS
;
517 DEBUGFUNC("__e1000_read_phy_reg_igp");
520 if (!(hw
->phy
.ops
.acquire
))
523 ret_val
= hw
->phy
.ops
.acquire(hw
);
528 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
529 ret_val
= e1000_write_phy_reg_mdic(hw
,
530 IGP01E1000_PHY_PAGE_SELECT
, (u16
)offset
);
535 ret_val
= e1000_read_phy_reg_mdic(hw
,
536 MAX_PHY_REG_ADDRESS
& offset
, data
);
540 hw
->phy
.ops
.release(hw
);
547 * e1000_read_phy_reg_igp - Read igp PHY register
548 * @hw: pointer to the HW structure
549 * @offset: register offset to be read
550 * @data: pointer to the read data
552 * Acquires semaphore then reads the PHY register at offset and stores the
553 * retrieved information in data.
554 * Release the acquired semaphore before exiting.
557 e1000_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
559 return (__e1000_read_phy_reg_igp(hw
, offset
, data
, false));
563 * e1000_read_phy_reg_igp_locked - Read igp PHY register
564 * @hw: pointer to the HW structure
565 * @offset: register offset to be read
566 * @data: pointer to the read data
568 * Reads the PHY register at offset and stores the retrieved information
569 * in data. Assumes semaphore already acquired.
572 e1000_read_phy_reg_igp_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
574 return (__e1000_read_phy_reg_igp(hw
, offset
, data
, true));
578 * __e1000_write_phy_reg_igp - Write igp PHY register
579 * @hw: pointer to the HW structure
580 * @offset: register offset to write to
581 * @data: data to write at register offset
582 * @locked: semaphore has already been acquired or not
584 * Acquires semaphore, if necessary, then writes the data to PHY register
585 * at the offset. Release any acquired semaphores before exiting.
588 __e1000_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
,
591 s32 ret_val
= E1000_SUCCESS
;
593 DEBUGFUNC("__e1000_write_phy_reg_igp");
596 if (!(hw
->phy
.ops
.acquire
))
599 ret_val
= hw
->phy
.ops
.acquire(hw
);
604 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
605 ret_val
= e1000_write_phy_reg_mdic(hw
,
606 IGP01E1000_PHY_PAGE_SELECT
, (u16
)offset
);
611 ret_val
= e1000_write_phy_reg_mdic(hw
,
612 MAX_PHY_REG_ADDRESS
& offset
, data
);
616 hw
->phy
.ops
.release(hw
);
623 * e1000_write_phy_reg_igp - Write igp PHY register
624 * @hw: pointer to the HW structure
625 * @offset: register offset to write to
626 * @data: data to write at register offset
628 * Acquires semaphore then writes the data to PHY register
629 * at the offset. Release any acquired semaphores before exiting.
632 e1000_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
)
634 return (__e1000_write_phy_reg_igp(hw
, offset
, data
, false));
638 * e1000_write_phy_reg_igp_locked - Write igp PHY register
639 * @hw: pointer to the HW structure
640 * @offset: register offset to write to
641 * @data: data to write at register offset
643 * Writes the data to PHY register at the offset.
644 * Assumes semaphore already acquired.
647 e1000_write_phy_reg_igp_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
649 return (__e1000_write_phy_reg_igp(hw
, offset
, data
, true));
653 * __e1000_read_kmrn_reg - Read kumeran register
654 * @hw: pointer to the HW structure
655 * @offset: register offset to be read
656 * @data: pointer to the read data
657 * @locked: semaphore has already been acquired or not
659 * Acquires semaphore, if necessary. Then reads the PHY register at offset
660 * using the kumeran interface. The information retrieved is stored in data.
661 * Release any acquired semaphores before exiting.
664 __e1000_read_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
, bool locked
)
667 s32 ret_val
= E1000_SUCCESS
;
669 DEBUGFUNC("__e1000_read_kmrn_reg_generic");
672 if (!(hw
->phy
.ops
.acquire
))
675 ret_val
= hw
->phy
.ops
.acquire(hw
);
680 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
681 E1000_KMRNCTRLSTA_OFFSET
) | E1000_KMRNCTRLSTA_REN
;
682 E1000_WRITE_REG(hw
, E1000_KMRNCTRLSTA
, kmrnctrlsta
);
686 kmrnctrlsta
= E1000_READ_REG(hw
, E1000_KMRNCTRLSTA
);
687 *data
= (u16
)kmrnctrlsta
;
690 hw
->phy
.ops
.release(hw
);
697 * e1000_read_kmrn_reg_generic - Read kumeran register
698 * @hw: pointer to the HW structure
699 * @offset: register offset to be read
700 * @data: pointer to the read data
702 * Acquires semaphore then reads the PHY register at offset using the
703 * kumeran interface. The information retrieved is stored in data.
704 * Release the acquired semaphore before exiting.
707 e1000_read_kmrn_reg_generic(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
709 return (__e1000_read_kmrn_reg(hw
, offset
, data
, false));
713 * e1000_read_kmrn_reg_locked - Read kumeran register
714 * @hw: pointer to the HW structure
715 * @offset: register offset to be read
716 * @data: pointer to the read data
718 * Reads the PHY register at offset using the kumeran interface. The
719 * information retrieved is stored in data.
720 * Assumes semaphore already acquired.
723 e1000_read_kmrn_reg_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
725 return (__e1000_read_kmrn_reg(hw
, offset
, data
, true));
729 * __e1000_write_kmrn_reg - Write kumeran register
730 * @hw: pointer to the HW structure
731 * @offset: register offset to write to
732 * @data: data to write at register offset
733 * @locked: semaphore has already been acquired or not
735 * Acquires semaphore, if necessary. Then write the data to PHY register
736 * at the offset using the kumeran interface. Release any acquired semaphores
740 __e1000_write_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
, bool locked
)
743 s32 ret_val
= E1000_SUCCESS
;
745 DEBUGFUNC("e1000_write_kmrn_reg_generic");
748 if (!(hw
->phy
.ops
.acquire
))
751 ret_val
= hw
->phy
.ops
.acquire(hw
);
756 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
757 E1000_KMRNCTRLSTA_OFFSET
) | data
;
758 E1000_WRITE_REG(hw
, E1000_KMRNCTRLSTA
, kmrnctrlsta
);
763 hw
->phy
.ops
.release(hw
);
770 * e1000_write_kmrn_reg_generic - Write kumeran register
771 * @hw: pointer to the HW structure
772 * @offset: register offset to write to
773 * @data: data to write at register offset
775 * Acquires semaphore then writes the data to the PHY register at the offset
776 * using the kumeran interface. Release the acquired semaphore before exiting.
779 e1000_write_kmrn_reg_generic(struct e1000_hw
*hw
, u32 offset
, u16 data
)
781 return (__e1000_write_kmrn_reg(hw
, offset
, data
, false));
785 * e1000_write_kmrn_reg_locked - Write kumeran register
786 * @hw: pointer to the HW structure
787 * @offset: register offset to write to
788 * @data: data to write at register offset
790 * Write the data to PHY register at the offset using the kumeran interface.
791 * Assumes semaphore already acquired.
794 e1000_write_kmrn_reg_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
796 return (__e1000_write_kmrn_reg(hw
, offset
, data
, true));
800 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
801 * @hw: pointer to the HW structure
803 * Sets up Carrier-sense on Transmit and downshift values.
806 e1000_copper_link_setup_82577(struct e1000_hw
*hw
)
808 struct e1000_phy_info
*phy
= &hw
->phy
;
812 DEBUGFUNC("e1000_copper_link_setup_82577");
814 if (phy
->reset_disable
) {
815 ret_val
= E1000_SUCCESS
;
819 if (phy
->type
== e1000_phy_82580
) {
820 ret_val
= hw
->phy
.ops
.reset(hw
);
822 DEBUGOUT("Error resetting the PHY.\n");
827 /* Enable CRS on TX. This must be set for half-duplex operation. */
828 ret_val
= phy
->ops
.read_reg(hw
, I82577_CFG_REG
, &phy_data
);
832 phy_data
|= I82577_CFG_ASSERT_CRS_ON_TX
;
834 /* Enable downshift */
835 phy_data
|= I82577_CFG_ENABLE_DOWNSHIFT
;
837 ret_val
= phy
->ops
.write_reg(hw
, I82577_CFG_REG
, phy_data
);
844 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
845 * @hw: pointer to the HW structure
847 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
848 * and downshift values are set also.
851 e1000_copper_link_setup_m88(struct e1000_hw
*hw
)
853 struct e1000_phy_info
*phy
= &hw
->phy
;
857 DEBUGFUNC("e1000_copper_link_setup_m88");
859 if (phy
->reset_disable
) {
860 ret_val
= E1000_SUCCESS
;
864 /* Enable CRS on TX. This must be set for half-duplex operation. */
865 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
869 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
873 * MDI/MDI-X = 0 (default)
874 * 0 - Auto for all speeds
877 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
879 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
883 phy_data
|= M88E1000_PSCR_MDI_MANUAL_MODE
;
886 phy_data
|= M88E1000_PSCR_MDIX_MANUAL_MODE
;
889 phy_data
|= M88E1000_PSCR_AUTO_X_1000T
;
893 phy_data
|= M88E1000_PSCR_AUTO_X_MODE
;
899 * disable_polarity_correction = 0 (default)
900 * Automatic Correction for Reversed Cable Polarity
904 phy_data
&= ~M88E1000_PSCR_POLARITY_REVERSAL
;
905 if (phy
->disable_polarity_correction
== 1)
906 phy_data
|= M88E1000_PSCR_POLARITY_REVERSAL
;
908 ret_val
= phy
->ops
.write_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
912 if (phy
->revision
< E1000_REVISION_4
) {
914 * Force TX_CLK in the Extended PHY Specific Control Register
917 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
,
922 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
924 if ((phy
->revision
== E1000_REVISION_2
) &&
925 (phy
->id
== M88E1111_I_PHY_ID
)) {
926 /* 82573L PHY - set the downshift counter to 5x. */
927 phy_data
&= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK
;
928 phy_data
|= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X
;
930 /* Configure Master and Slave downshift values */
931 phy_data
&= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
|
932 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK
);
933 phy_data
|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
|
934 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X
);
936 ret_val
= phy
->ops
.write_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
,
942 /* Commit the changes. */
943 ret_val
= phy
->ops
.commit(hw
);
945 DEBUGOUT("Error committing the PHY changes\n");
954 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
955 * @hw: pointer to the HW structure
957 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
961 e1000_copper_link_setup_igp(struct e1000_hw
*hw
)
963 struct e1000_phy_info
*phy
= &hw
->phy
;
967 DEBUGFUNC("e1000_copper_link_setup_igp");
969 if (phy
->reset_disable
) {
970 ret_val
= E1000_SUCCESS
;
974 ret_val
= hw
->phy
.ops
.reset(hw
);
976 DEBUGOUT("Error resetting the PHY.\n");
981 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
982 * timeout issues when LFS is enabled.
987 * The NVM settings will configure LPLU in D3 for
990 if (phy
->type
== e1000_phy_igp
) {
991 /* disable lplu d3 during driver init */
992 ret_val
= hw
->phy
.ops
.set_d3_lplu_state(hw
, false);
994 DEBUGOUT("Error Disabling LPLU D3\n");
999 /* disable lplu d0 during driver init */
1000 if (hw
->phy
.ops
.set_d0_lplu_state
) {
1001 ret_val
= hw
->phy
.ops
.set_d0_lplu_state(hw
, false);
1003 DEBUGOUT("Error Disabling LPLU D0\n");
1007 /* Configure mdi-mdix settings */
1008 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, &data
);
1012 data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1014 switch (phy
->mdix
) {
1016 data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1019 data
|= IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1023 data
|= IGP01E1000_PSCR_AUTO_MDIX
;
1026 ret_val
= phy
->ops
.write_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, data
);
1030 /* set auto-master slave resolution settings */
1031 if (hw
->mac
.autoneg
) {
1033 * when autonegotiation advertisement is only 1000Mbps then we
1034 * should disable SmartSpeed and enable Auto MasterSlave
1035 * resolution as hardware default.
1037 if (phy
->autoneg_advertised
== ADVERTISE_1000_FULL
) {
1038 /* Disable SmartSpeed */
1039 ret_val
= phy
->ops
.read_reg(hw
,
1040 IGP01E1000_PHY_PORT_CONFIG
, &data
);
1044 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1045 ret_val
= phy
->ops
.write_reg(hw
,
1046 IGP01E1000_PHY_PORT_CONFIG
, data
);
1050 /* Set auto Master/Slave resolution process */
1051 ret_val
= phy
->ops
.read_reg(hw
, PHY_1000T_CTRL
, &data
);
1055 data
&= ~CR_1000T_MS_ENABLE
;
1056 ret_val
= phy
->ops
.write_reg(hw
, PHY_1000T_CTRL
, data
);
1061 ret_val
= phy
->ops
.read_reg(hw
, PHY_1000T_CTRL
, &data
);
1065 /* load defaults for future use */
1066 phy
->original_ms_type
= (data
& CR_1000T_MS_ENABLE
) ?
1067 ((data
& CR_1000T_MS_VALUE
) ?
1068 e1000_ms_force_master
:
1069 e1000_ms_force_slave
) :
1072 switch (phy
->ms_type
) {
1073 case e1000_ms_force_master
:
1074 data
|= (CR_1000T_MS_ENABLE
| CR_1000T_MS_VALUE
);
1076 case e1000_ms_force_slave
:
1077 data
|= CR_1000T_MS_ENABLE
;
1078 data
&= ~(CR_1000T_MS_VALUE
);
1081 data
&= ~CR_1000T_MS_ENABLE
;
1085 ret_val
= phy
->ops
.write_reg(hw
, PHY_1000T_CTRL
, data
);
1095 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1096 * @hw: pointer to the HW structure
1098 * Performs initial bounds checking on autoneg advertisement parameter, then
1099 * configure to advertise the full capability. Setup the PHY to autoneg
1100 * and restart the negotiation process between the link partner. If
1101 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1104 e1000_copper_link_autoneg(struct e1000_hw
*hw
)
1106 struct e1000_phy_info
*phy
= &hw
->phy
;
1110 DEBUGFUNC("e1000_copper_link_autoneg");
1113 * Perform some bounds checking on the autoneg advertisement
1116 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
1119 * If autoneg_advertised is zero, we assume it was not defaulted
1120 * by the calling code so we set to advertise full capability.
1122 if (phy
->autoneg_advertised
== 0)
1123 phy
->autoneg_advertised
= phy
->autoneg_mask
;
1125 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1126 ret_val
= e1000_phy_setup_autoneg(hw
);
1128 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1131 DEBUGOUT("Restarting Auto-Neg\n");
1134 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1135 * the Auto Neg Restart bit in the PHY control register.
1137 ret_val
= phy
->ops
.read_reg(hw
, PHY_CONTROL
, &phy_ctrl
);
1141 phy_ctrl
|= (MII_CR_AUTO_NEG_EN
| MII_CR_RESTART_AUTO_NEG
);
1142 ret_val
= phy
->ops
.write_reg(hw
, PHY_CONTROL
, phy_ctrl
);
1147 * Does the user want to wait for Auto-Neg to complete here, or
1148 * check at a later time (for example, callback routine).
1150 if (phy
->autoneg_wait_to_complete
) {
1151 ret_val
= hw
->mac
.ops
.wait_autoneg(hw
);
1153 DEBUGOUT("Error while waiting for "
1154 "autoneg to complete\n");
1159 hw
->mac
.get_link_status
= true;
1166 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1167 * @hw: pointer to the HW structure
1169 * Reads the MII auto-neg advertisement register and/or the 1000T control
1170 * register and if the PHY is already setup for auto-negotiation, then
1171 * return successful. Otherwise, setup advertisement and flow control to
1172 * the appropriate values for the wanted auto-negotiation.
1175 e1000_phy_setup_autoneg(struct e1000_hw
*hw
)
1177 struct e1000_phy_info
*phy
= &hw
->phy
;
1179 u16 mii_autoneg_adv_reg
;
1180 u16 mii_1000t_ctrl_reg
= 0;
1182 DEBUGFUNC("e1000_phy_setup_autoneg");
1184 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
1186 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1187 ret_val
= phy
->ops
.read_reg(hw
, PHY_AUTONEG_ADV
, &mii_autoneg_adv_reg
);
1191 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
1192 /* Read the MII 1000Base-T Control Register (Address 9). */
1193 ret_val
= phy
->ops
.read_reg(hw
, PHY_1000T_CTRL
,
1194 &mii_1000t_ctrl_reg
);
1200 * Need to parse both autoneg_advertised and fc and set up
1201 * the appropriate PHY registers. First we will parse for
1202 * autoneg_advertised software override. Since we can advertise
1203 * a plethora of combinations, we need to check each bit
1208 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1209 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1210 * the 1000Base-T Control Register (Address 9).
1212 mii_autoneg_adv_reg
&= ~(NWAY_AR_100TX_FD_CAPS
|
1213 NWAY_AR_100TX_HD_CAPS
|
1214 NWAY_AR_10T_FD_CAPS
|
1215 NWAY_AR_10T_HD_CAPS
);
1216 mii_1000t_ctrl_reg
&= ~(CR_1000T_HD_CAPS
| CR_1000T_FD_CAPS
);
1218 DEBUGOUT1("autoneg_advertised %x\n", phy
->autoneg_advertised
);
1220 /* Do we want to advertise 10 Mb Half Duplex? */
1221 if (phy
->autoneg_advertised
& ADVERTISE_10_HALF
) {
1222 DEBUGOUT("Advertise 10mb Half duplex\n");
1223 mii_autoneg_adv_reg
|= NWAY_AR_10T_HD_CAPS
;
1226 /* Do we want to advertise 10 Mb Full Duplex? */
1227 if (phy
->autoneg_advertised
& ADVERTISE_10_FULL
) {
1228 DEBUGOUT("Advertise 10mb Full duplex\n");
1229 mii_autoneg_adv_reg
|= NWAY_AR_10T_FD_CAPS
;
1232 /* Do we want to advertise 100 Mb Half Duplex? */
1233 if (phy
->autoneg_advertised
& ADVERTISE_100_HALF
) {
1234 DEBUGOUT("Advertise 100mb Half duplex\n");
1235 mii_autoneg_adv_reg
|= NWAY_AR_100TX_HD_CAPS
;
1238 /* Do we want to advertise 100 Mb Full Duplex? */
1239 if (phy
->autoneg_advertised
& ADVERTISE_100_FULL
) {
1240 DEBUGOUT("Advertise 100mb Full duplex\n");
1241 mii_autoneg_adv_reg
|= NWAY_AR_100TX_FD_CAPS
;
1244 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1245 if (phy
->autoneg_advertised
& ADVERTISE_1000_HALF
)
1246 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1248 /* Do we want to advertise 1000 Mb Full Duplex? */
1249 if (phy
->autoneg_advertised
& ADVERTISE_1000_FULL
) {
1250 DEBUGOUT("Advertise 1000mb Full duplex\n");
1251 mii_1000t_ctrl_reg
|= CR_1000T_FD_CAPS
;
1255 * Check for a software override of the flow control settings, and
1256 * setup the PHY advertisement registers accordingly. If
1257 * auto-negotiation is enabled, then software will have to set the
1258 * "PAUSE" bits to the correct value in the Auto-Negotiation
1259 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1262 * The possible values of the "fc" parameter are:
1263 * 0: Flow control is completely disabled
1264 * 1: Rx flow control is enabled (we can receive pause frames
1265 * but not send pause frames).
1266 * 2: Tx flow control is enabled (we can send pause frames
1267 * but we do not support receiving pause frames).
1268 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1269 * other: No software override. The flow control configuration
1270 * in the EEPROM is used.
1272 switch (hw
->fc
.current_mode
) {
1275 * Flow control (Rx & Tx) is completely disabled by a
1276 * software over-ride.
1278 mii_autoneg_adv_reg
&= ~(NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1280 case e1000_fc_rx_pause
:
1282 * Rx Flow control is enabled, and Tx Flow control is
1283 * disabled, by a software over-ride.
1285 * Since there really isn't a way to advertise that we are
1286 * capable of Rx Pause ONLY, we will advertise that we
1287 * support both symmetric and asymmetric Rx PAUSE. Later
1288 * (in e1000_config_fc_after_link_up) we will disable the
1289 * hw's ability to send PAUSE frames.
1291 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1293 case e1000_fc_tx_pause
:
1295 * Tx Flow control is enabled, and Rx Flow control is
1296 * disabled, by a software over-ride.
1298 mii_autoneg_adv_reg
|= NWAY_AR_ASM_DIR
;
1299 mii_autoneg_adv_reg
&= ~NWAY_AR_PAUSE
;
1303 * Flow control (both Rx and Tx) is enabled by a software
1306 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1309 DEBUGOUT("Flow control param set incorrectly\n");
1310 ret_val
= -E1000_ERR_CONFIG
;
1314 ret_val
= phy
->ops
.write_reg(hw
, PHY_AUTONEG_ADV
, mii_autoneg_adv_reg
);
1318 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
);
1320 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
1321 ret_val
= phy
->ops
.write_reg(hw
,
1322 PHY_1000T_CTRL
, mii_1000t_ctrl_reg
);
1332 * e1000_setup_copper_link_generic - Configure copper link settings
1333 * @hw: pointer to the HW structure
1335 * Calls the appropriate function to configure the link for auto-neg or forced
1336 * speed and duplex. Then we check for link, once link is established calls
1337 * to configure collision distance and flow control are called. If link is
1338 * not established, we return -E1000_ERR_PHY (-2).
1341 e1000_setup_copper_link_generic(struct e1000_hw
*hw
)
1346 DEBUGFUNC("e1000_setup_copper_link_generic");
1348 if (hw
->mac
.autoneg
) {
1350 * Setup autoneg and flow control advertisement and perform
1353 ret_val
= e1000_copper_link_autoneg(hw
);
1358 * PHY will be set to 10H, 10F, 100H or 100F
1359 * depending on user settings.
1361 DEBUGOUT("Forcing Speed and Duplex\n");
1362 ret_val
= hw
->phy
.ops
.force_speed_duplex(hw
);
1364 DEBUGOUT("Error Forcing Speed and Duplex\n");
1370 * Check link status. Wait up to 100 microseconds for link to become
1373 ret_val
= e1000_phy_has_link_generic(hw
,
1374 COPPER_LINK_UP_LIMIT
,
1381 DEBUGOUT("Valid link established!!!\n");
1382 e1000_config_collision_dist_generic(hw
);
1383 ret_val
= e1000_config_fc_after_link_up_generic(hw
);
1385 DEBUGOUT("Unable to establish link!!!\n");
1393 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1394 * @hw: pointer to the HW structure
1396 * Calls the PHY setup function to force speed and duplex. Clears the
1397 * auto-crossover to force MDI manually. Waits for link and returns
1398 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1401 e1000_phy_force_speed_duplex_igp(struct e1000_hw
*hw
)
1403 struct e1000_phy_info
*phy
= &hw
->phy
;
1408 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1410 ret_val
= phy
->ops
.read_reg(hw
, PHY_CONTROL
, &phy_data
);
1414 e1000_phy_force_speed_duplex_setup(hw
, &phy_data
);
1416 ret_val
= phy
->ops
.write_reg(hw
, PHY_CONTROL
, phy_data
);
1421 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1422 * forced whenever speed and duplex are forced.
1424 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1428 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1429 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1431 ret_val
= phy
->ops
.write_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1435 DEBUGOUT1("IGP PSCR: %X\n", phy_data
);
1439 if (phy
->autoneg_wait_to_complete
) {
1440 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1442 ret_val
= e1000_phy_has_link_generic(hw
,
1450 DEBUGOUT("Link taking longer than expected.\n");
1453 ret_val
= e1000_phy_has_link_generic(hw
,
1466 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1467 * @hw: pointer to the HW structure
1469 * Calls the PHY setup function to force speed and duplex. Clears the
1470 * auto-crossover to force MDI manually. Resets the PHY to commit the
1471 * changes. If time expires while waiting for link up, we reset the DSP.
1472 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1473 * successful completion, else return corresponding error code.
1476 e1000_phy_force_speed_duplex_m88(struct e1000_hw
*hw
)
1478 struct e1000_phy_info
*phy
= &hw
->phy
;
1483 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1486 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1487 * forced whenever speed and duplex are forced.
1489 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1493 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1494 ret_val
= phy
->ops
.write_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1498 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data
);
1500 ret_val
= phy
->ops
.read_reg(hw
, PHY_CONTROL
, &phy_data
);
1504 e1000_phy_force_speed_duplex_setup(hw
, &phy_data
);
1506 ret_val
= phy
->ops
.write_reg(hw
, PHY_CONTROL
, phy_data
);
1510 /* Reset the phy to commit changes. */
1511 ret_val
= hw
->phy
.ops
.commit(hw
);
1515 if (phy
->autoneg_wait_to_complete
) {
1516 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1518 ret_val
= e1000_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1525 * We didn't get link.
1526 * Reset the DSP and cross our fingers.
1528 ret_val
= phy
->ops
.write_reg(hw
,
1529 M88E1000_PHY_PAGE_SELECT
,
1533 ret_val
= e1000_phy_reset_dsp_generic(hw
);
1539 ret_val
= e1000_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1545 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1550 * Resetting the phy means we need to re-force TX_CLK in the
1551 * Extended PHY Specific Control Register to 25MHz clock from
1552 * the reset value of 2.5MHz.
1554 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1555 ret_val
= phy
->ops
.write_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1560 * In addition, we must re-enable CRS on Tx for both half and full
1563 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1567 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1568 ret_val
= phy
->ops
.write_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1575 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1576 * @hw: pointer to the HW structure
1578 * Forces the speed and duplex settings of the PHY.
1579 * This is a function pointer entry point only called by
1580 * PHY setup routines.
1583 e1000_phy_force_speed_duplex_ife(struct e1000_hw
*hw
)
1585 struct e1000_phy_info
*phy
= &hw
->phy
;
1590 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1592 if (phy
->type
!= e1000_phy_ife
) {
1593 ret_val
= e1000_phy_force_speed_duplex_igp(hw
);
1597 ret_val
= phy
->ops
.read_reg(hw
, PHY_CONTROL
, &data
);
1601 e1000_phy_force_speed_duplex_setup(hw
, &data
);
1603 ret_val
= phy
->ops
.write_reg(hw
, PHY_CONTROL
, data
);
1607 /* Disable MDI-X support for 10/100 */
1608 ret_val
= phy
->ops
.read_reg(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
1612 data
&= ~IFE_PMC_AUTO_MDIX
;
1613 data
&= ~IFE_PMC_FORCE_MDIX
;
1615 ret_val
= phy
->ops
.write_reg(hw
, IFE_PHY_MDIX_CONTROL
, data
);
1619 DEBUGOUT1("IFE PMC: %X\n", data
);
1623 if (phy
->autoneg_wait_to_complete
) {
1624 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1626 ret_val
= e1000_phy_has_link_generic(hw
,
1627 PHY_FORCE_LIMIT
, 100000, &link
);
1632 DEBUGOUT("Link taking longer than expected.\n");
1635 ret_val
= e1000_phy_has_link_generic(hw
,
1636 PHY_FORCE_LIMIT
, 100000, &link
);
1645 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1646 * @hw: pointer to the HW structure
1647 * @phy_ctrl: pointer to current value of PHY_CONTROL
1649 * Forces speed and duplex on the PHY by doing the following: disable flow
1650 * control, force speed/duplex on the MAC, disable auto speed detection,
1651 * disable auto-negotiation, configure duplex, configure speed, configure
1652 * the collision distance, write configuration to CTRL register. The
1653 * caller must write to the PHY_CONTROL register for these settings to
1657 e1000_phy_force_speed_duplex_setup(struct e1000_hw
*hw
, u16
*phy_ctrl
)
1659 struct e1000_mac_info
*mac
= &hw
->mac
;
1662 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1664 /* Turn off flow control when forcing speed/duplex */
1665 hw
->fc
.current_mode
= e1000_fc_none
;
1667 /* Force speed/duplex on the mac */
1668 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
1669 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1670 ctrl
&= ~E1000_CTRL_SPD_SEL
;
1672 /* Disable Auto Speed Detection */
1673 ctrl
&= ~E1000_CTRL_ASDE
;
1675 /* Disable autoneg on the phy */
1676 *phy_ctrl
&= ~MII_CR_AUTO_NEG_EN
;
1678 /* Forcing Full or Half Duplex? */
1679 if (mac
->forced_speed_duplex
& E1000_ALL_HALF_DUPLEX
) {
1680 ctrl
&= ~E1000_CTRL_FD
;
1681 *phy_ctrl
&= ~MII_CR_FULL_DUPLEX
;
1682 DEBUGOUT("Half Duplex\n");
1684 ctrl
|= E1000_CTRL_FD
;
1685 *phy_ctrl
|= MII_CR_FULL_DUPLEX
;
1686 DEBUGOUT("Full Duplex\n");
1689 /* Forcing 10mb or 100mb? */
1690 if (mac
->forced_speed_duplex
& E1000_ALL_100_SPEED
) {
1691 ctrl
|= E1000_CTRL_SPD_100
;
1692 *phy_ctrl
|= MII_CR_SPEED_100
;
1693 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_10
);
1694 DEBUGOUT("Forcing 100mb\n");
1696 ctrl
&= ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1698 *phy_ctrl
|= MII_CR_SPEED_10
;
1699 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_100
);
1700 DEBUGOUT("Forcing 10mb\n");
1703 e1000_config_collision_dist_generic(hw
);
1705 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
);
1709 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1710 * @hw: pointer to the HW structure
1711 * @active: boolean used to enable/disable lplu
1713 * Success returns 0, Failure returns 1
1715 * The low power link up (lplu) state is set to the power management level D3
1716 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1717 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1718 * is used during Dx states where the power conservation is most important.
1719 * During driver activity, SmartSpeed should be enabled so performance is
1723 e1000_set_d3_lplu_state_generic(struct e1000_hw
*hw
, bool active
)
1725 struct e1000_phy_info
*phy
= &hw
->phy
;
1726 s32 ret_val
= E1000_SUCCESS
;
1729 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1731 if (!(hw
->phy
.ops
.read_reg
))
1734 ret_val
= phy
->ops
.read_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
1739 data
&= ~IGP02E1000_PM_D3_LPLU
;
1740 ret_val
= phy
->ops
.write_reg(hw
,
1741 IGP02E1000_PHY_POWER_MGMT
,
1746 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1747 * during Dx states where the power conservation is most
1748 * important. During driver activity we should enable
1749 * SmartSpeed, so performance is maintained.
1751 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1752 ret_val
= phy
->ops
.read_reg(hw
,
1753 IGP01E1000_PHY_PORT_CONFIG
,
1758 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1759 ret_val
= phy
->ops
.write_reg(hw
,
1760 IGP01E1000_PHY_PORT_CONFIG
,
1764 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1765 ret_val
= phy
->ops
.read_reg(hw
,
1766 IGP01E1000_PHY_PORT_CONFIG
,
1771 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1772 ret_val
= phy
->ops
.write_reg(hw
,
1773 IGP01E1000_PHY_PORT_CONFIG
,
1778 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1779 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1780 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1781 data
|= IGP02E1000_PM_D3_LPLU
;
1782 ret_val
= phy
->ops
.write_reg(hw
,
1783 IGP02E1000_PHY_POWER_MGMT
,
1788 /* When LPLU is enabled, we should disable SmartSpeed */
1789 ret_val
= phy
->ops
.read_reg(hw
,
1790 IGP01E1000_PHY_PORT_CONFIG
,
1795 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1796 ret_val
= phy
->ops
.write_reg(hw
,
1797 IGP01E1000_PHY_PORT_CONFIG
,
1806 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
1807 * @hw: pointer to the HW structure
1809 * Success returns 0, Failure returns 1
1811 * A downshift is detected by querying the PHY link health.
1814 e1000_check_downshift_generic(struct e1000_hw
*hw
)
1816 struct e1000_phy_info
*phy
= &hw
->phy
;
1818 u16 phy_data
, offset
, mask
;
1820 DEBUGFUNC("e1000_check_downshift_generic");
1822 switch (phy
->type
) {
1824 case e1000_phy_gg82563
:
1825 offset
= M88E1000_PHY_SPEC_STATUS
;
1826 mask
= M88E1000_PSSR_DOWNSHIFT
;
1828 case e1000_phy_igp_2
:
1830 case e1000_phy_igp_3
:
1831 offset
= IGP01E1000_PHY_LINK_HEALTH
;
1832 mask
= IGP01E1000_PLHR_SS_DOWNGRADE
;
1835 /* speed downshift not supported */
1836 phy
->speed_downgraded
= false;
1837 ret_val
= E1000_SUCCESS
;
1841 ret_val
= phy
->ops
.read_reg(hw
, offset
, &phy_data
);
1844 phy
->speed_downgraded
= (phy_data
& mask
) ? true : false;
1851 * e1000_check_polarity_m88 - Checks the polarity.
1852 * @hw: pointer to the HW structure
1854 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1856 * Polarity is determined based on the PHY specific status register.
1859 e1000_check_polarity_m88(struct e1000_hw
*hw
)
1861 struct e1000_phy_info
*phy
= &hw
->phy
;
1865 DEBUGFUNC("e1000_check_polarity_m88");
1867 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &data
);
1870 phy
->cable_polarity
= (data
& M88E1000_PSSR_REV_POLARITY
)
1871 ? e1000_rev_polarity_reversed
1872 : e1000_rev_polarity_normal
;
1878 * e1000_check_polarity_igp - Checks the polarity.
1879 * @hw: pointer to the HW structure
1881 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1883 * Polarity is determined based on the PHY port status register, and the
1884 * current speed (since there is no polarity at 100Mbps).
1887 e1000_check_polarity_igp(struct e1000_hw
*hw
)
1889 struct e1000_phy_info
*phy
= &hw
->phy
;
1891 u16 data
, offset
, mask
;
1893 DEBUGFUNC("e1000_check_polarity_igp");
1896 * Polarity is determined based on the speed of
1899 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
1903 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1904 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1905 offset
= IGP01E1000_PHY_PCS_INIT_REG
;
1906 mask
= IGP01E1000_PHY_POLARITY_MASK
;
1909 * This really only applies to 10Mbps since
1910 * there is no polarity for 100Mbps (always 0).
1912 offset
= IGP01E1000_PHY_PORT_STATUS
;
1913 mask
= IGP01E1000_PSSR_POLARITY_REVERSED
;
1916 ret_val
= phy
->ops
.read_reg(hw
, offset
, &data
);
1919 phy
->cable_polarity
= (data
& mask
)
1920 ? e1000_rev_polarity_reversed
1921 : e1000_rev_polarity_normal
;
1928 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1929 * @hw: pointer to the HW structure
1931 * Polarity is determined on the polarity reversal feature being enabled.
1934 e1000_check_polarity_ife(struct e1000_hw
*hw
)
1936 struct e1000_phy_info
*phy
= &hw
->phy
;
1938 u16 phy_data
, offset
, mask
;
1940 DEBUGFUNC("e1000_check_polarity_ife");
1943 * Polarity is determined based on the reversal feature being enabled.
1945 if (phy
->polarity_correction
) {
1946 offset
= IFE_PHY_EXTENDED_STATUS_CONTROL
;
1947 mask
= IFE_PESC_POLARITY_REVERSED
;
1949 offset
= IFE_PHY_SPECIAL_CONTROL
;
1950 mask
= IFE_PSC_FORCE_POLARITY
;
1953 ret_val
= phy
->ops
.read_reg(hw
, offset
, &phy_data
);
1956 phy
->cable_polarity
= (phy_data
& mask
)
1957 ? e1000_rev_polarity_reversed
1958 : e1000_rev_polarity_normal
;
1963 * e1000_wait_autoneg_generic - Wait for auto-neg completion
1964 * @hw: pointer to the HW structure
1966 * Waits for auto-negotiation to complete or for the auto-negotiation time
1967 * limit to expire, which ever happens first.
1970 e1000_wait_autoneg_generic(struct e1000_hw
*hw
)
1972 s32 ret_val
= E1000_SUCCESS
;
1975 DEBUGFUNC("e1000_wait_autoneg_generic");
1977 if (!(hw
->phy
.ops
.read_reg
))
1978 return (E1000_SUCCESS
);
1980 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1981 for (i
= PHY_AUTO_NEG_LIMIT
; i
> 0; i
--) {
1982 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
, &phy_status
);
1985 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
, &phy_status
);
1988 if (phy_status
& MII_SR_AUTONEG_COMPLETE
)
1994 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2001 * e1000_phy_has_link_generic - Polls PHY for link
2002 * @hw: pointer to the HW structure
2003 * @iterations: number of times to poll for link
2004 * @usec_interval: delay between polling attempts
2005 * @success: pointer to whether polling was successful or not
2007 * Polls the PHY status register for link, 'iterations' number of times.
2010 e1000_phy_has_link_generic(struct e1000_hw
*hw
, u32 iterations
,
2011 u32 usec_interval
, bool *success
)
2013 s32 ret_val
= E1000_SUCCESS
;
2016 DEBUGFUNC("e1000_phy_has_link_generic");
2018 if (!(hw
->phy
.ops
.read_reg
))
2019 return (E1000_SUCCESS
);
2021 for (i
= 0; i
< iterations
; i
++) {
2023 * Some PHYs require the PHY_STATUS register to be read
2024 * twice due to the link bit being sticky. No harm doing
2025 * it across the board.
2027 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
, &phy_status
);
2030 * If the first read fails, another entity may have
2031 * ownership of the resources, wait and try again to
2032 * see if they have relinquished the resources yet.
2034 usec_delay(usec_interval
);
2036 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
, &phy_status
);
2039 if (phy_status
& MII_SR_LINK_STATUS
)
2041 if (usec_interval
>= 1000)
2042 msec_delay_irq(usec_interval
/1000);
2044 usec_delay(usec_interval
);
2047 *success
= (i
< iterations
) ? true : false;
2053 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2054 * @hw: pointer to the HW structure
2056 * Reads the PHY specific status register to retrieve the cable length
2057 * information. The cable length is determined by averaging the minimum and
2058 * maximum values to get the "average" cable length. The m88 PHY has four
2059 * possible cable length values, which are:
2060 * Register Value Cable Length
2064 * 3 110 - 140 meters
2068 e1000_get_cable_length_m88(struct e1000_hw
*hw
)
2070 struct e1000_phy_info
*phy
= &hw
->phy
;
2072 u16 phy_data
, index
;
2074 DEBUGFUNC("e1000_get_cable_length_m88");
2076 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
2080 index
= (phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
2081 M88E1000_PSSR_CABLE_LENGTH_SHIFT
;
2082 if (index
>= M88E1000_CABLE_LENGTH_TABLE_SIZE
- 1) {
2083 ret_val
= -E1000_ERR_PHY
;
2087 phy
->min_cable_length
= e1000_m88_cable_length_table
[index
];
2088 phy
->max_cable_length
= e1000_m88_cable_length_table
[index
+ 1];
2090 phy
->cable_length
= (phy
->min_cable_length
+
2091 phy
->max_cable_length
) / 2;
2098 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2099 * @hw: pointer to the HW structure
2101 * The automatic gain control (agc) normalizes the amplitude of the
2102 * received signal, adjusting for the attenuation produced by the
2103 * cable. By reading the AGC registers, which represent the
2104 * combination of coarse and fine gain value, the value can be put
2105 * into a lookup table to obtain the approximate cable length
2109 e1000_get_cable_length_igp_2(struct e1000_hw
*hw
)
2111 struct e1000_phy_info
*phy
= &hw
->phy
;
2112 s32 ret_val
= E1000_SUCCESS
;
2113 u16 phy_data
, i
, agc_value
= 0;
2114 u16 cur_agc_index
, max_agc_index
= 0;
2115 u16 min_agc_index
= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
- 1;
2116 u16 agc_reg_array
[IGP02E1000_PHY_CHANNEL_NUM
] =
2117 {IGP02E1000_PHY_AGC_A
,
2118 IGP02E1000_PHY_AGC_B
,
2119 IGP02E1000_PHY_AGC_C
,
2120 IGP02E1000_PHY_AGC_D
};
2122 DEBUGFUNC("e1000_get_cable_length_igp_2");
2124 /* Read the AGC registers for all channels */
2125 for (i
= 0; i
< IGP02E1000_PHY_CHANNEL_NUM
; i
++) {
2126 ret_val
= phy
->ops
.read_reg(hw
, agc_reg_array
[i
], &phy_data
);
2131 * Getting bits 15:9, which represent the combination of
2132 * coarse and fine gain values. The result is a number
2133 * that can be put into the lookup table to obtain the
2134 * approximate cable length.
2136 cur_agc_index
= (phy_data
>> IGP02E1000_AGC_LENGTH_SHIFT
) &
2137 IGP02E1000_AGC_LENGTH_MASK
;
2139 /* Array index bound check. */
2140 if ((cur_agc_index
>= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
) ||
2141 (cur_agc_index
== 0)) {
2142 ret_val
= -E1000_ERR_PHY
;
2146 /* Remove min & max AGC values from calculation. */
2147 if (e1000_igp_2_cable_length_table
[min_agc_index
] >
2148 e1000_igp_2_cable_length_table
[cur_agc_index
])
2149 min_agc_index
= cur_agc_index
;
2150 if (e1000_igp_2_cable_length_table
[max_agc_index
] <
2151 e1000_igp_2_cable_length_table
[cur_agc_index
])
2152 max_agc_index
= cur_agc_index
;
2154 agc_value
+= e1000_igp_2_cable_length_table
[cur_agc_index
];
2157 agc_value
-= (e1000_igp_2_cable_length_table
[min_agc_index
] +
2158 e1000_igp_2_cable_length_table
[max_agc_index
]);
2159 agc_value
/= (IGP02E1000_PHY_CHANNEL_NUM
- 2);
2161 /* Calculate cable length with the error range of +/- 10 meters. */
2162 phy
->min_cable_length
= ((agc_value
- IGP02E1000_AGC_RANGE
) > 0) ?
2163 (agc_value
- IGP02E1000_AGC_RANGE
) : 0;
2164 phy
->max_cable_length
= agc_value
+ IGP02E1000_AGC_RANGE
;
2166 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
2173 * e1000_get_phy_info_m88 - Retrieve PHY information
2174 * @hw: pointer to the HW structure
2176 * Valid for only copper links. Read the PHY status register (sticky read)
2177 * to verify that link is up. Read the PHY special control register to
2178 * determine the polarity and 10base-T extended distance. Read the PHY
2179 * special status register to determine MDI/MDIx and current speed. If
2180 * speed is 1000, then determine cable length, local and remote receiver.
2183 e1000_get_phy_info_m88(struct e1000_hw
*hw
)
2185 struct e1000_phy_info
*phy
= &hw
->phy
;
2190 DEBUGFUNC("e1000_get_phy_info_m88");
2192 if (phy
->media_type
!= e1000_media_type_copper
) {
2193 DEBUGOUT("Phy info is only valid for copper media\n");
2194 ret_val
= -E1000_ERR_CONFIG
;
2198 ret_val
= e1000_phy_has_link_generic(hw
, 1, 0, &link
);
2203 DEBUGOUT("Phy info is only valid if link is up\n");
2204 ret_val
= -E1000_ERR_CONFIG
;
2208 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
2212 phy
->polarity_correction
= (phy_data
& M88E1000_PSCR_POLARITY_REVERSAL
)
2215 ret_val
= e1000_check_polarity_m88(hw
);
2219 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
2223 phy
->is_mdix
= (phy_data
& M88E1000_PSSR_MDIX
) ? true : false;
2225 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
) {
2226 ret_val
= hw
->phy
.ops
.get_cable_length(hw
);
2230 ret_val
= phy
->ops
.read_reg(hw
, PHY_1000T_STATUS
, &phy_data
);
2234 phy
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
)
2235 ? e1000_1000t_rx_status_ok
2236 : e1000_1000t_rx_status_not_ok
;
2238 phy
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
)
2239 ? e1000_1000t_rx_status_ok
2240 : e1000_1000t_rx_status_not_ok
;
2242 /* Set values to "undefined" */
2243 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
2244 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
2245 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
2253 * e1000_get_phy_info_igp - Retrieve igp PHY information
2254 * @hw: pointer to the HW structure
2256 * Read PHY status to determine if link is up. If link is up, then
2257 * set/determine 10base-T extended distance and polarity correction. Read
2258 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2259 * determine on the cable length, local and remote receiver.
2262 e1000_get_phy_info_igp(struct e1000_hw
*hw
)
2264 struct e1000_phy_info
*phy
= &hw
->phy
;
2269 DEBUGFUNC("e1000_get_phy_info_igp");
2271 ret_val
= e1000_phy_has_link_generic(hw
, 1, 0, &link
);
2276 DEBUGOUT("Phy info is only valid if link is up\n");
2277 ret_val
= -E1000_ERR_CONFIG
;
2281 phy
->polarity_correction
= true;
2283 ret_val
= e1000_check_polarity_igp(hw
);
2287 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
2291 phy
->is_mdix
= (data
& IGP01E1000_PSSR_MDIX
) ? true : false;
2293 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
2294 IGP01E1000_PSSR_SPEED_1000MBPS
) {
2295 ret_val
= phy
->ops
.get_cable_length(hw
);
2299 ret_val
= phy
->ops
.read_reg(hw
, PHY_1000T_STATUS
, &data
);
2303 phy
->local_rx
= (data
& SR_1000T_LOCAL_RX_STATUS
)
2304 ? e1000_1000t_rx_status_ok
2305 : e1000_1000t_rx_status_not_ok
;
2307 phy
->remote_rx
= (data
& SR_1000T_REMOTE_RX_STATUS
)
2308 ? e1000_1000t_rx_status_ok
2309 : e1000_1000t_rx_status_not_ok
;
2311 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
2312 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
2313 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
2321 * e1000_phy_sw_reset_generic - PHY software reset
2322 * @hw: pointer to the HW structure
2324 * Does a software reset of the PHY by reading the PHY control register and
2325 * setting/write the control register reset bit to the PHY.
2328 e1000_phy_sw_reset_generic(struct e1000_hw
*hw
)
2330 s32 ret_val
= E1000_SUCCESS
;
2333 DEBUGFUNC("e1000_phy_sw_reset_generic");
2335 if (!(hw
->phy
.ops
.read_reg
))
2338 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_CONTROL
, &phy_ctrl
);
2342 phy_ctrl
|= MII_CR_RESET
;
2343 ret_val
= hw
->phy
.ops
.write_reg(hw
, PHY_CONTROL
, phy_ctrl
);
2354 * e1000_phy_hw_reset_generic - PHY hardware reset
2355 * @hw: pointer to the HW structure
2357 * Verify the reset block is not blocking us from resetting. Acquire
2358 * semaphore (if necessary) and read/set/write the device control reset
2359 * bit in the PHY. Wait the appropriate delay time for the device to
2360 * reset and release the semaphore (if necessary).
2363 e1000_phy_hw_reset_generic(struct e1000_hw
*hw
)
2365 struct e1000_phy_info
*phy
= &hw
->phy
;
2366 s32 ret_val
= E1000_SUCCESS
;
2369 DEBUGFUNC("e1000_phy_hw_reset_generic");
2371 ret_val
= phy
->ops
.check_reset_block(hw
);
2373 ret_val
= E1000_SUCCESS
;
2377 ret_val
= phy
->ops
.acquire(hw
);
2381 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
2382 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
| E1000_CTRL_PHY_RST
);
2383 E1000_WRITE_FLUSH(hw
);
2385 usec_delay(phy
->reset_delay_us
);
2387 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
);
2388 E1000_WRITE_FLUSH(hw
);
2392 phy
->ops
.release(hw
);
2394 ret_val
= phy
->ops
.get_cfg_done(hw
);
2401 * e1000_get_cfg_done_generic - Generic configuration done
2402 * @hw: pointer to the HW structure
2404 * Generic function to wait 10 milli-seconds for configuration to complete
2405 * and return success.
2408 e1000_get_cfg_done_generic(struct e1000_hw
*hw
)
2410 DEBUGFUNC("e1000_get_cfg_done_generic");
2411 UNREFERENCED_1PARAMETER(hw
);
2415 return (E1000_SUCCESS
);
2419 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2420 * @hw: pointer to the HW structure
2422 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2425 e1000_phy_init_script_igp3(struct e1000_hw
*hw
)
2427 DEBUGOUT("Running IGP 3 PHY init script\n");
2429 /* PHY init IGP 3 */
2430 /* Enable rise/fall, 10-mode work in class-A */
2431 (void) hw
->phy
.ops
.write_reg(hw
, 0x2F5B, 0x9018);
2432 /* Remove all caps from Replica path filter */
2433 (void) hw
->phy
.ops
.write_reg(hw
, 0x2F52, 0x0000);
2434 /* Bias trimming for ADC, AFE and Driver (Default) */
2435 (void) hw
->phy
.ops
.write_reg(hw
, 0x2FB1, 0x8B24);
2436 /* Increase Hybrid poly bias */
2437 (void) hw
->phy
.ops
.write_reg(hw
, 0x2FB2, 0xF8F0);
2438 /* Add 4% to Tx amplitude in Gig mode */
2439 (void) hw
->phy
.ops
.write_reg(hw
, 0x2010, 0x10B0);
2440 /* Disable trimming (TTT) */
2441 (void) hw
->phy
.ops
.write_reg(hw
, 0x2011, 0x0000);
2442 /* Poly DC correction to 94.6% + 2% for all channels */
2443 (void) hw
->phy
.ops
.write_reg(hw
, 0x20DD, 0x249A);
2444 /* ABS DC correction to 95.9% */
2445 (void) hw
->phy
.ops
.write_reg(hw
, 0x20DE, 0x00D3);
2446 /* BG temp curve trim */
2447 (void) hw
->phy
.ops
.write_reg(hw
, 0x28B4, 0x04CE);
2448 /* Increasing ADC OPAMP stage 1 currents to max */
2449 (void) hw
->phy
.ops
.write_reg(hw
, 0x2F70, 0x29E4);
2450 /* Force 1000 ( required for enabling PHY regs configuration) */
2451 (void) hw
->phy
.ops
.write_reg(hw
, 0x0000, 0x0140);
2452 /* Set upd_freq to 6 */
2453 (void) hw
->phy
.ops
.write_reg(hw
, 0x1F30, 0x1606);
2455 (void) hw
->phy
.ops
.write_reg(hw
, 0x1F31, 0xB814);
2456 /* Disable adaptive fixed FFE (Default) */
2457 (void) hw
->phy
.ops
.write_reg(hw
, 0x1F35, 0x002A);
2458 /* Enable FFE hysteresis */
2459 (void) hw
->phy
.ops
.write_reg(hw
, 0x1F3E, 0x0067);
2460 /* Fixed FFE for short cable lengths */
2461 (void) hw
->phy
.ops
.write_reg(hw
, 0x1F54, 0x0065);
2462 /* Fixed FFE for medium cable lengths */
2463 (void) hw
->phy
.ops
.write_reg(hw
, 0x1F55, 0x002A);
2464 /* Fixed FFE for long cable lengths */
2465 (void) hw
->phy
.ops
.write_reg(hw
, 0x1F56, 0x002A);
2466 /* Enable Adaptive Clip Threshold */
2467 (void) hw
->phy
.ops
.write_reg(hw
, 0x1F72, 0x3FB0);
2468 /* AHT reset limit to 1 */
2469 (void) hw
->phy
.ops
.write_reg(hw
, 0x1F76, 0xC0FF);
2470 /* Set AHT master delay to 127 msec */
2471 (void) hw
->phy
.ops
.write_reg(hw
, 0x1F77, 0x1DEC);
2472 /* Set scan bits for AHT */
2473 (void) hw
->phy
.ops
.write_reg(hw
, 0x1F78, 0xF9EF);
2474 /* Set AHT Preset bits */
2475 (void) hw
->phy
.ops
.write_reg(hw
, 0x1F79, 0x0210);
2476 /* Change integ_factor of channel A to 3 */
2477 (void) hw
->phy
.ops
.write_reg(hw
, 0x1895, 0x0003);
2478 /* Change prop_factor of channels BCD to 8 */
2479 (void) hw
->phy
.ops
.write_reg(hw
, 0x1796, 0x0008);
2480 /* Change cg_icount + enable integbp for channels BCD */
2481 (void) hw
->phy
.ops
.write_reg(hw
, 0x1798, 0xD008);
2483 * Change cg_icount + enable integbp + change prop_factor_master
2484 * to 8 for channel A
2486 (void) hw
->phy
.ops
.write_reg(hw
, 0x1898, 0xD918);
2487 /* Disable AHT in Slave mode on channel A */
2488 (void) hw
->phy
.ops
.write_reg(hw
, 0x187A, 0x0800);
2490 * Enable LPLU and disable AN to 1000 in non-D0a states,
2493 (void) hw
->phy
.ops
.write_reg(hw
, 0x0019, 0x008D);
2494 /* Enable restart AN on an1000_dis change */
2495 (void) hw
->phy
.ops
.write_reg(hw
, 0x001B, 0x2080);
2496 /* Enable wh_fifo read clock in 10/100 modes */
2497 (void) hw
->phy
.ops
.write_reg(hw
, 0x0014, 0x0045);
2498 /* Restart AN, Speed selection is 1000 */
2499 (void) hw
->phy
.ops
.write_reg(hw
, 0x0000, 0x1340);
2501 return (E1000_SUCCESS
);
2505 * e1000_get_phy_type_from_id - Get PHY type from id
2506 * @phy_id: phy_id read from the phy
2508 * Returns the phy type from the id.
2511 e1000_get_phy_type_from_id(u32 phy_id
)
2513 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
2516 case M88E1000_I_PHY_ID
:
2517 case M88E1000_E_PHY_ID
:
2518 case M88E1111_I_PHY_ID
:
2519 case M88E1011_I_PHY_ID
:
2520 phy_type
= e1000_phy_m88
;
2522 case IGP01E1000_I_PHY_ID
: /* IGP 1 & 2 share this */
2523 phy_type
= e1000_phy_igp_2
;
2525 case GG82563_E_PHY_ID
:
2526 phy_type
= e1000_phy_gg82563
;
2528 case IGP03E1000_E_PHY_ID
:
2529 phy_type
= e1000_phy_igp_3
;
2532 case IFE_PLUS_E_PHY_ID
:
2533 case IFE_C_E_PHY_ID
:
2534 phy_type
= e1000_phy_ife
;
2536 case I82580_I_PHY_ID
:
2537 phy_type
= e1000_phy_82580
;
2540 phy_type
= e1000_phy_unknown
;
2547 * e1000_determine_phy_address - Determines PHY address.
2548 * @hw: pointer to the HW structure
2550 * This uses a trial and error method to loop through possible PHY
2551 * addresses. It tests each by reading the PHY ID registers and
2552 * checking for a match.
2555 e1000_determine_phy_address(struct e1000_hw
*hw
)
2557 s32 ret_val
= -E1000_ERR_PHY_TYPE
;
2560 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
2562 hw
->phy
.id
= phy_type
;
2564 for (phy_addr
= 0; phy_addr
< E1000_MAX_PHY_ADDR
; phy_addr
++) {
2565 hw
->phy
.addr
= phy_addr
;
2569 (void) e1000_get_phy_id(hw
);
2570 phy_type
= e1000_get_phy_type_from_id(hw
->phy
.id
);
2573 * If phy_type is valid, break - we found our
2576 if (phy_type
!= e1000_phy_unknown
) {
2577 ret_val
= E1000_SUCCESS
;
2589 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2590 * @hw: pointer to the HW structure
2592 * In the case of a PHY power down to save power, or to turn off link during a
2593 * driver unload, or wake on lan is not enabled, restore the link to previous
2597 e1000_power_up_phy_copper(struct e1000_hw
*hw
)
2601 /* The PHY will retain its settings across a power down/up cycle */
2602 (void) hw
->phy
.ops
.read_reg(hw
, PHY_CONTROL
, &mii_reg
);
2603 mii_reg
&= ~MII_CR_POWER_DOWN
;
2604 (void) hw
->phy
.ops
.write_reg(hw
, PHY_CONTROL
, mii_reg
);
2608 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2609 * @hw: pointer to the HW structure
2611 * In the case of a PHY power down to save power, or to turn off link during a
2612 * driver unload, or wake on lan is not enabled, restore the link to previous
2616 e1000_power_down_phy_copper(struct e1000_hw
*hw
)
2620 /* The PHY will retain its settings across a power down/up cycle */
2621 (void) hw
->phy
.ops
.read_reg(hw
, PHY_CONTROL
, &mii_reg
);
2622 mii_reg
|= MII_CR_POWER_DOWN
;
2623 (void) hw
->phy
.ops
.write_reg(hw
, PHY_CONTROL
, mii_reg
);
2628 * e1000_check_polarity_82577 - Checks the polarity.
2629 * @hw: pointer to the HW structure
2631 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2633 * Polarity is determined based on the PHY specific status register.
2636 e1000_check_polarity_82577(struct e1000_hw
*hw
)
2638 struct e1000_phy_info
*phy
= &hw
->phy
;
2642 DEBUGFUNC("e1000_check_polarity_82577");
2644 ret_val
= phy
->ops
.read_reg(hw
, I82577_PHY_STATUS_2
, &data
);
2647 phy
->cable_polarity
= (data
& I82577_PHY_STATUS2_REV_POLARITY
)
2648 ? e1000_rev_polarity_reversed
2649 : e1000_rev_polarity_normal
;
2655 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
2656 * @hw: pointer to the HW structure
2658 * Calls the PHY setup function to force speed and duplex. Clears the
2659 * auto-crossover to force MDI manually. Waits for link and returns
2660 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2663 e1000_phy_force_speed_duplex_82577(struct e1000_hw
*hw
)
2665 struct e1000_phy_info
*phy
= &hw
->phy
;
2670 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
2672 ret_val
= phy
->ops
.read_reg(hw
, PHY_CONTROL
, &phy_data
);
2676 e1000_phy_force_speed_duplex_setup(hw
, &phy_data
);
2678 ret_val
= phy
->ops
.write_reg(hw
, PHY_CONTROL
, phy_data
);
2683 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI
2684 * forced whenever speed and duplex are forced.
2686 ret_val
= phy
->ops
.read_reg(hw
, I82577_PHY_CTRL_2
, &phy_data
);
2690 phy_data
&= ~I82577_PHY_CTRL2_AUTO_MDIX
;
2691 phy_data
&= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX
;
2693 ret_val
= phy
->ops
.write_reg(hw
, I82577_PHY_CTRL_2
, phy_data
);
2697 DEBUGOUT1("I82577_PHY_CTRL_2: %X\n", phy_data
);
2701 if (phy
->autoneg_wait_to_complete
) {
2702 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
2704 ret_val
= e1000_phy_has_link_generic(hw
,
2712 DEBUGOUT("Link taking longer than expected.\n");
2715 ret_val
= e1000_phy_has_link_generic(hw
,
2728 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
2729 * @hw: pointer to the HW structure
2731 * Read PHY status to determine if link is up. If link is up, then
2732 * set/determine 10base-T extended distance and polarity correction. Read
2733 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2734 * determine on the cable length, local and remote receiver.
2737 e1000_get_phy_info_82577(struct e1000_hw
*hw
)
2739 struct e1000_phy_info
*phy
= &hw
->phy
;
2744 DEBUGFUNC("e1000_get_phy_info_82577");
2746 ret_val
= e1000_phy_has_link_generic(hw
, 1, 0, &link
);
2751 DEBUGOUT("Phy info is only valid if link is up\n");
2752 ret_val
= -E1000_ERR_CONFIG
;
2756 phy
->polarity_correction
= true;
2758 ret_val
= e1000_check_polarity_82577(hw
);
2762 ret_val
= phy
->ops
.read_reg(hw
, I82577_PHY_STATUS_2
, &data
);
2766 phy
->is_mdix
= (data
& I82577_PHY_STATUS2_MDIX
) ? true : false;
2768 if ((data
& I82577_PHY_STATUS2_SPEED_MASK
) ==
2769 I82577_PHY_STATUS2_SPEED_1000MBPS
) {
2770 ret_val
= hw
->phy
.ops
.get_cable_length(hw
);
2774 ret_val
= phy
->ops
.read_reg(hw
, PHY_1000T_STATUS
, &data
);
2778 phy
->local_rx
= (data
& SR_1000T_LOCAL_RX_STATUS
)
2779 ? e1000_1000t_rx_status_ok
2780 : e1000_1000t_rx_status_not_ok
;
2782 phy
->remote_rx
= (data
& SR_1000T_REMOTE_RX_STATUS
)
2783 ? e1000_1000t_rx_status_ok
2784 : e1000_1000t_rx_status_not_ok
;
2786 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
2787 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
2788 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
2796 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
2797 * @hw: pointer to the HW structure
2799 * Reads the diagnostic status register and verifies result is valid before
2800 * placing it in the phy_cable_length field.
2803 e1000_get_cable_length_82577(struct e1000_hw
*hw
)
2805 struct e1000_phy_info
*phy
= &hw
->phy
;
2807 u16 phy_data
, length
;
2809 DEBUGFUNC("e1000_get_cable_length_82577");
2811 ret_val
= phy
->ops
.read_reg(hw
, I82577_PHY_DIAG_STATUS
, &phy_data
);
2815 length
= (phy_data
& I82577_DSTATUS_CABLE_LENGTH
) >>
2816 I82577_DSTATUS_CABLE_LENGTH_SHIFT
;
2818 if (length
== E1000_CABLE_LENGTH_UNDEFINED
)
2819 ret_val
= -E1000_ERR_PHY
;
2821 phy
->cable_length
= length
;