usr/src/uts/common/io/e1000g/e1000_hw.h

   1 /*
   2  * This file is provided under a CDDLv1 license.  When using or
   3  * redistributing this file, you may do so under this license.
   4  * In redistributing this file this license must be included
   5  * and no other modification of this header file is permitted.
   6  *
   7  * CDDL LICENSE SUMMARY
   8  *
   9  * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
  10  *
  11  * The contents of this file are subject to the terms of Version
  12  * 1.0 of the Common Development and Distribution License (the "License").
  13  *
  14  * You should have received a copy of the License with this software.
  15  * You can obtain a copy of the License at
  16  *      http://www.opensolaris.org/os/licensing.
  17  * See the License for the specific language governing permissions
  18  * and limitations under the License.
  19  */
  20
  21 /*
  22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms of the CDDLv1.
  24  */
  25
  26 /*
  27  * Copyright (c) 2001-2010, Intel Corporation
  28  * All rights reserved.
  29  *
  30  * Redistribution and use in source and binary forms, with or without
  31  * modification, are permitted provided that the following conditions are met:
  32  *
  33  *  1. Redistributions of source code must retain the above copyright notice,
  34  *     this list of conditions and the following disclaimer.
  35  *
  36  *  2. Redistributions in binary form must reproduce the above copyright
  37  *     notice, this list of conditions and the following disclaimer in the
  38  *     documentation and/or other materials provided with the distribution.
  39  *
  40  *  3. Neither the name of the Intel Corporation nor the names of its
  41  *     contributors may be used to endorse or promote products derived from
  42  *     this software without specific prior written permission.
  43  *
  44  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  45  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  46  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  47  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  48  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  54  * POSSIBILITY OF SUCH DAMAGE.
  55  */
  56
  57 #ifndef _E1000_HW_H_
  58 #define _E1000_HW_H_
  59
  60 #ifdef __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 #include "e1000_osdep.h"
  65 #include "e1000_regs.h"
  66 #include "e1000_defines.h"
  67
  68 struct e1000_hw;
  69
  70 #define E1000_DEV_ID_82542                      0x1000
  71 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  72 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  73 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  74 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  75 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  76 #define E1000_DEV_ID_82544GC_LOM                0x100D
  77 #define E1000_DEV_ID_82540EM                    0x100E
  78 #define E1000_DEV_ID_82540EM_LOM                0x1015
  79 #define E1000_DEV_ID_82540EP_LOM                0x1016
  80 #define E1000_DEV_ID_82540EP                    0x1017
  81 #define E1000_DEV_ID_82540EP_LP                 0x101E
  82 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  83 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  84 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  85 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  86 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  87 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  88 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  89 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  90 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  91 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  92 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  93 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  94 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  95 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  96 #define E1000_DEV_ID_82541EI                    0x1013
  97 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  98 #define E1000_DEV_ID_82541ER_LOM                0x1014
  99 #define E1000_DEV_ID_82541ER                    0x1078
 100 #define E1000_DEV_ID_82541GI                    0x1076
 101 #define E1000_DEV_ID_82541GI_LF                 0x107C
 102 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
 103 #define E1000_DEV_ID_82547EI                    0x1019
 104 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
 105 #define E1000_DEV_ID_82547GI                    0x1075
 106 #define E1000_DEV_ID_82571EB_COPPER             0x105E
 107 #define E1000_DEV_ID_82571EB_FIBER              0x105F
 108 #define E1000_DEV_ID_82571EB_SERDES             0x1060
 109 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
 110 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
 111 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
 112 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
 113 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
 114 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
 115 #define E1000_DEV_ID_82572EI_COPPER             0x107D
 116 #define E1000_DEV_ID_82572EI_FIBER              0x107E
 117 #define E1000_DEV_ID_82572EI_SERDES             0x107F
 118 #define E1000_DEV_ID_82572EI                    0x10B9
 119 #define E1000_DEV_ID_82573E                     0x108B
 120 #define E1000_DEV_ID_82573E_IAMT                0x108C
 121 #define E1000_DEV_ID_82573L                     0x109A
 122 #define E1000_DEV_ID_82574L                     0x10D3
 123 #define E1000_DEV_ID_82574LA                    0x10F6
 124 #define E1000_DEV_ID_82583V                     0x150C
 125 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
 126 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 127 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 128 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 129 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 130 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 131 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 132 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 133 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 134 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 135 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 136 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
 137 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
 138 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
 139 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 140 #define E1000_DEV_ID_ICH9_BM                    0x10E5
 141 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 142 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 143 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 144 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 145 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
 146 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
 147 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
 148 #define E1000_DEV_ID_ICH10_HANKSVILLE           0xF0FE
 149 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
 150 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
 151 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
 152 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
 153 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
 154 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 155 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 156 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 157
 158 #define E1000_REVISION_0        0
 159 #define E1000_REVISION_1        1
 160 #define E1000_REVISION_2        2
 161 #define E1000_REVISION_3        3
 162 #define E1000_REVISION_4        4
 163
 164 #define E1000_FUNC_0    0
 165 #define E1000_FUNC_1    1
 166
 167 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 168 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 169
 170 /* Maximum size of the MTA register table in all supported adapters */
 171 #define MAX_MTA_REG 128
 172
 173 enum e1000_mac_type {
 174         e1000_undefined = 0,
 175         e1000_82542,
 176         e1000_82543,
 177         e1000_82544,
 178         e1000_82540,
 179         e1000_82545,
 180         e1000_82545_rev_3,
 181         e1000_82546,
 182         e1000_82546_rev_3,
 183         e1000_82541,
 184         e1000_82541_rev_2,
 185         e1000_82547,
 186         e1000_82547_rev_2,
 187         e1000_82571,
 188         e1000_82572,
 189         e1000_82573,
 190         e1000_82574,
 191         e1000_82583,
 192         e1000_80003es2lan,
 193         e1000_ich8lan,
 194         e1000_ich9lan,
 195         e1000_ich10lan,
 196         e1000_pchlan,
 197         e1000_pch2lan,
 198         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
 199 };
 200
 201 enum e1000_media_type {
 202         e1000_media_type_unknown = 0,
 203         e1000_media_type_copper = 1,
 204         e1000_media_type_fiber = 2,
 205         e1000_media_type_internal_serdes = 3,
 206         e1000_num_media_types
 207 };
 208
 209 enum e1000_nvm_type {
 210         e1000_nvm_unknown = 0,
 211         e1000_nvm_none,
 212         e1000_nvm_eeprom_spi,
 213         e1000_nvm_eeprom_microwire,
 214         e1000_nvm_flash_hw,
 215         e1000_nvm_flash_sw
 216 };
 217
 218 enum e1000_nvm_override {
 219         e1000_nvm_override_none = 0,
 220         e1000_nvm_override_spi_small,
 221         e1000_nvm_override_spi_large,
 222         e1000_nvm_override_microwire_small,
 223         e1000_nvm_override_microwire_large
 224 };
 225
 226 enum e1000_phy_type {
 227         e1000_phy_unknown = 0,
 228         e1000_phy_none,
 229         e1000_phy_m88,
 230         e1000_phy_igp,
 231         e1000_phy_igp_2,
 232         e1000_phy_gg82563,
 233         e1000_phy_igp_3,
 234         e1000_phy_ife,
 235         e1000_phy_bm,
 236         e1000_phy_82578,
 237         e1000_phy_82577,
 238         e1000_phy_82579
 239 };
 240
 241 enum e1000_bus_type {
 242         e1000_bus_type_unknown = 0,
 243         e1000_bus_type_pci,
 244         e1000_bus_type_pcix,
 245         e1000_bus_type_pci_express,
 246         e1000_bus_type_reserved
 247 };
 248
 249 enum e1000_bus_speed {
 250         e1000_bus_speed_unknown = 0,
 251         e1000_bus_speed_33,
 252         e1000_bus_speed_66,
 253         e1000_bus_speed_100,
 254         e1000_bus_speed_120,
 255         e1000_bus_speed_133,
 256         e1000_bus_speed_2500,
 257         e1000_bus_speed_5000,
 258         e1000_bus_speed_reserved
 259 };
 260
 261 enum e1000_bus_width {
 262         e1000_bus_width_unknown = 0,
 263         e1000_bus_width_pcie_x1,
 264         e1000_bus_width_pcie_x2,
 265         e1000_bus_width_pcie_x4 = 4,
 266         e1000_bus_width_pcie_x8 = 8,
 267         e1000_bus_width_32,
 268         e1000_bus_width_64,
 269         e1000_bus_width_reserved
 270 };
 271
 272 enum e1000_1000t_rx_status {
 273         e1000_1000t_rx_status_not_ok = 0,
 274         e1000_1000t_rx_status_ok,
 275         e1000_1000t_rx_status_undefined = 0xFF
 276 };
 277
 278 enum e1000_rev_polarity {
 279         e1000_rev_polarity_normal = 0,
 280         e1000_rev_polarity_reversed,
 281         e1000_rev_polarity_undefined = 0xFF
 282 };
 283
 284 enum e1000_fc_mode {
 285         e1000_fc_none = 0,
 286         e1000_fc_rx_pause,
 287         e1000_fc_tx_pause,
 288         e1000_fc_full,
 289         e1000_fc_default = 0xFF
 290 };
 291
 292 enum e1000_ffe_config {
 293         e1000_ffe_config_enabled = 0,
 294         e1000_ffe_config_active,
 295         e1000_ffe_config_blocked
 296 };
 297
 298 enum e1000_dsp_config {
 299         e1000_dsp_config_disabled = 0,
 300         e1000_dsp_config_enabled,
 301         e1000_dsp_config_activated,
 302         e1000_dsp_config_undefined = 0xFF
 303 };
 304
 305 enum e1000_ms_type {
 306         e1000_ms_hw_default = 0,
 307         e1000_ms_force_master,
 308         e1000_ms_force_slave,
 309         e1000_ms_auto
 310 };
 311
 312 enum e1000_smart_speed {
 313         e1000_smart_speed_default = 0,
 314         e1000_smart_speed_on,
 315         e1000_smart_speed_off
 316 };
 317
 318 enum e1000_serdes_link_state {
 319         e1000_serdes_link_down = 0,
 320         e1000_serdes_link_autoneg_progress,
 321         e1000_serdes_link_autoneg_complete,
 322         e1000_serdes_link_forced_up
 323 };
 324
 325 /* Receive Descriptor */
 326 struct e1000_rx_desc {
 327         __le64 buffer_addr;     /* Address of the descriptor's data buffer */
 328         __le16 length;          /* Length of data DMAed into data buffer */
 329         __le16 csum;            /* Packet checksum */
 330         u8 status;              /* Descriptor status */
 331         u8 errors;              /* Descriptor Errors */
 332         __le16 special;
 333 };
 334
 335 /* Receive Descriptor - Extended */
 336 union e1000_rx_desc_extended {
 337         struct {
 338                 __le64 buffer_addr;
 339                 __le64 reserved;
 340         } read;
 341         struct {
 342                 struct {
 343                         __le32 mrq;             /* Multiple Rx Queues */
 344                         union {
 345                                 __le32 rss;     /* RSS Hash */
 346                                 struct {
 347                                         __le16 ip_id;  /* IP id */
 348                                         __le16 csum;   /* Packet Checksum */
 349                                 } csum_ip;
 350                         } hi_dword;
 351                 } lower;
 352                 struct {
 353                         __le32 status_error;    /* ext status/error */
 354                         __le16 length;
 355                         __le16 vlan;            /* VLAN tag */
 356                 } upper;
 357         } wb;  /* writeback */
 358 };
 359
 360 #define MAX_PS_BUFFERS 4
 361 /* Receive Descriptor - Packet Split */
 362 union e1000_rx_desc_packet_split {
 363         struct {
 364                 /* one buffer for protocol header(s), three data buffers */
 365                 __le64 buffer_addr[MAX_PS_BUFFERS];
 366         } read;
 367         struct {
 368                 struct {
 369                         __le32 mrq;             /* Multiple Rx Queues */
 370                         union {
 371                                 __le32 rss;     /* RSS Hash */
 372                                 struct {
 373                                         __le16 ip_id;   /* IP id */
 374                                         __le16 csum;    /* Packet Checksum */
 375                                 } csum_ip;
 376                         } hi_dword;
 377                 } lower;
 378                 struct {
 379                         __le32 status_error;    /* ext status/error */
 380                         __le16 length0;         /* length of buffer 0 */
 381                         __le16 vlan;            /* VLAN tag */
 382                 } middle;
 383                 struct {
 384                         __le16 header_status;
 385                         __le16 length[3];       /* length of buffers 1-3 */
 386                 } upper;
 387                 __le64 reserved;
 388         } wb; /* writeback */
 389 };
 390
 391 /* Transmit Descriptor */
 392 struct e1000_tx_desc {
 393         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 394         union {
 395                 __le32 data;
 396                 struct {
 397                         __le16 length;  /* Data buffer length */
 398                         u8 cso;         /* Checksum offset */
 399                         u8 cmd;         /* Descriptor control */
 400                 } flags;
 401         } lower;
 402         union {
 403                 __le32 data;
 404                 struct {
 405                         u8 status;      /* Descriptor status */
 406                         u8 css;         /* Checksum start */
 407                         __le16 special;
 408                 } fields;
 409         } upper;
 410 };
 411
 412 /* Offload Context Descriptor */
 413 struct e1000_context_desc {
 414         union {
 415                 __le32 ip_config;
 416                 struct {
 417                         u8 ipcss;       /* IP checksum start */
 418                         u8 ipcso;       /* IP checksum offset */
 419                         __le16 ipcse;   /* IP checksum end */
 420                 } ip_fields;
 421         } lower_setup;
 422         union {
 423                 __le32 tcp_config;
 424                 struct {
 425                         u8 tucss;       /* TCP checksum start */
 426                         u8 tucso;       /* TCP checksum offset */
 427                         __le16 tucse;   /* TCP checksum end */
 428                 } tcp_fields;
 429         } upper_setup;
 430         __le32 cmd_and_length;
 431         union {
 432                 __le32 data;
 433                 struct {
 434                         u8 status;      /* Descriptor status */
 435                         u8 hdr_len;     /* Header length */
 436                         __le16 mss;     /* Maximum segment size */
 437                 } fields;
 438         } tcp_seg_setup;
 439 };
 440
 441 /* Offload data descriptor */
 442 struct e1000_data_desc {
 443         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 444         union {
 445                 __le32 data;
 446                 struct {
 447                         __le16 length;    /* Data buffer length */
 448                         u8 typ_len_ext;
 449                         u8 cmd;
 450                 } flags;
 451         } lower;
 452         union {
 453                 __le32 data;
 454                 struct {
 455                         u8 status;      /* Descriptor status */
 456                         u8 popts;       /* Packet Options */
 457                         __le16 special;
 458                 } fields;
 459         } upper;
 460 };
 461
 462 /* Statistics counters collected by the MAC */
 463 struct e1000_hw_stats {
 464         u64 crcerrs;
 465         u64 algnerrc;
 466         u64 symerrs;
 467         u64 rxerrc;
 468         u64 mpc;
 469         u64 scc;
 470         u64 ecol;
 471         u64 mcc;
 472         u64 latecol;
 473         u64 colc;
 474         u64 dc;
 475         u64 tncrs;
 476         u64 sec;
 477         u64 cexterr;
 478         u64 rlec;
 479         u64 xonrxc;
 480         u64 xontxc;
 481         u64 xoffrxc;
 482         u64 xofftxc;
 483         u64 fcruc;
 484         u64 prc64;
 485         u64 prc127;
 486         u64 prc255;
 487         u64 prc511;
 488         u64 prc1023;
 489         u64 prc1522;
 490         u64 gprc;
 491         u64 bprc;
 492         u64 mprc;
 493         u64 gptc;
 494         u64 gorc;
 495         u64 gotc;
 496         u64 rnbc;
 497         u64 ruc;
 498         u64 rfc;
 499         u64 roc;
 500         u64 rjc;
 501         u64 mgprc;
 502         u64 mgpdc;
 503         u64 mgptc;
 504         u64 tor;
 505         u64 tot;
 506         u64 tpr;
 507         u64 tpt;
 508         u64 ptc64;
 509         u64 ptc127;
 510         u64 ptc255;
 511         u64 ptc511;
 512         u64 ptc1023;
 513         u64 ptc1522;
 514         u64 mptc;
 515         u64 bptc;
 516         u64 tsctc;
 517         u64 tsctfc;
 518         u64 iac;
 519         u64 icrxptc;
 520         u64 icrxatc;
 521         u64 ictxptc;
 522         u64 ictxatc;
 523         u64 ictxqec;
 524         u64 ictxqmtc;
 525         u64 icrxdmtc;
 526         u64 icrxoc;
 527         u64 cbtmpc;
 528         u64 htdpmc;
 529         u64 cbrdpc;
 530         u64 cbrmpc;
 531         u64 rpthc;
 532         u64 hgptc;
 533         u64 htcbdpc;
 534         u64 hgorc;
 535         u64 hgotc;
 536         u64 lenerrs;
 537         u64 scvpc;
 538         u64 hrmpc;
 539         u64 doosync;
 540 };
 541
 542 struct e1000_phy_stats {
 543         u32 idle_errors;
 544         u32 receive_errors;
 545 };
 546
 547 struct e1000_host_mng_dhcp_cookie {
 548         u32 signature;
 549         u8 status;
 550         u8 reserved0;
 551         u16 vlan_id;
 552         u32 reserved1;
 553         u16 reserved2;
 554         u8 reserved3;
 555         u8 checksum;
 556 };
 557
 558 /* Host Interface "Rev 1" */
 559 struct e1000_host_command_header {
 560         u8 command_id;
 561         u8 command_length;
 562         u8 command_options;
 563         u8 checksum;
 564 };
 565
 566 #define E1000_HI_MAX_DATA_LENGTH        252
 567 struct e1000_host_command_info {
 568         struct e1000_host_command_header command_header;
 569         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 570 };
 571
 572 /* Host Interface "Rev 2" */
 573 struct e1000_host_mng_command_header {
 574         u8 command_id;
 575         u8 checksum;
 576         u16 reserved1;
 577         u16 reserved2;
 578         u16 command_length;
 579 };
 580
 581 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 582 struct e1000_host_mng_command_info {
 583         struct e1000_host_mng_command_header command_header;
 584         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 585 };
 586
 587 #include "e1000_mac.h"
 588 #include "e1000_phy.h"
 589 #include "e1000_nvm.h"
 590 #include "e1000_manage.h"
 591
 592 struct e1000_mac_operations {
 593         /* Function pointers for the MAC. */
 594         s32 (*init_params)(struct e1000_hw *);
 595         s32 (*id_led_init)(struct e1000_hw *);
 596         s32 (*blink_led)(struct e1000_hw *);
 597         s32 (*check_for_link)(struct e1000_hw *);
 598         bool (*check_mng_mode)(struct e1000_hw *hw);
 599         s32 (*cleanup_led)(struct e1000_hw *);
 600         void (*clear_hw_cntrs)(struct e1000_hw *);
 601         void (*clear_vfta)(struct e1000_hw *);
 602         s32 (*get_bus_info)(struct e1000_hw *);
 603         void (*set_lan_id)(struct e1000_hw *);
 604         s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 605         s32 (*led_on)(struct e1000_hw *);
 606         s32 (*led_off)(struct e1000_hw *);
 607         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 608         s32 (*reset_hw)(struct e1000_hw *);
 609         s32 (*init_hw)(struct e1000_hw *);
 610         s32 (*setup_link)(struct e1000_hw *);
 611         s32 (*setup_physical_interface)(struct e1000_hw *);
 612         s32 (*setup_led)(struct e1000_hw *);
 613         void (*write_vfta)(struct e1000_hw *, u32, u32);
 614         void (*mta_set)(struct e1000_hw *, u32);
 615         void (*config_collision_dist)(struct e1000_hw *);
 616         void (*rar_set)(struct e1000_hw *, u8 *, u32);
 617         s32 (*read_mac_addr)(struct e1000_hw *);
 618         s32 (*validate_mdi_setting)(struct e1000_hw *);
 619         s32 (*mng_host_if_write)(struct e1000_hw *, u8 *, u16, u16, u8 *);
 620         s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
 621             struct e1000_host_mng_command_header *);
 622         s32 (*mng_enable_host_if)(struct e1000_hw *);
 623         s32 (*wait_autoneg)(struct e1000_hw *);
 624 };
 625
 626 struct e1000_phy_operations {
 627         s32 (*init_params)(struct e1000_hw *);
 628         s32 (*acquire)(struct e1000_hw *);
 629         s32  (*cfg_on_link_up)(struct e1000_hw *);
 630         s32 (*check_polarity)(struct e1000_hw *);
 631         s32 (*check_reset_block)(struct e1000_hw *);
 632         s32 (*commit)(struct e1000_hw *);
 633         s32 (*force_speed_duplex)(struct e1000_hw *);
 634         s32 (*get_cfg_done)(struct e1000_hw *hw);
 635         s32 (*get_cable_length)(struct e1000_hw *);
 636         s32 (*get_info)(struct e1000_hw *);
 637         s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
 638         s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 639         void (*release)(struct e1000_hw *);
 640         s32 (*reset)(struct e1000_hw *);
 641         s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
 642         s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
 643         s32 (*write_reg)(struct e1000_hw *, u32, u16);
 644         s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
 645         void (*power_up)(struct e1000_hw *);
 646         void (*power_down)(struct e1000_hw *);
 647 };
 648
 649 struct e1000_nvm_operations {
 650         s32 (*init_params)(struct e1000_hw *);
 651         s32 (*acquire)(struct e1000_hw *);
 652         s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
 653         void (*release)(struct e1000_hw *);
 654         void (*reload)(struct e1000_hw *);
 655         s32 (*update)(struct e1000_hw *);
 656         s32 (*valid_led_default)(struct e1000_hw *, u16 *);
 657         s32 (*validate)(struct e1000_hw *);
 658         s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
 659 };
 660
 661 struct e1000_mac_info {
 662         struct e1000_mac_operations ops;
 663         u8 addr[6];
 664         u8 perm_addr[6];
 665
 666         enum e1000_mac_type type;
 667
 668         u32 collision_delta;
 669         u32 ledctl_default;
 670         u32 ledctl_mode1;
 671         u32 ledctl_mode2;
 672         u32 mc_filter_type;
 673         u32 tx_packet_delta;
 674         u32 txcw;
 675
 676         u16 current_ifs_val;
 677         u16 ifs_max_val;
 678         u16 ifs_min_val;
 679         u16 ifs_ratio;
 680         u16 ifs_step_size;
 681         u16 mta_reg_count;
 682         u32 mta_shadow[MAX_MTA_REG];
 683         u16 rar_entry_count;
 684
 685         u8 forced_speed_duplex;
 686
 687         bool adaptive_ifs;
 688         bool has_fwsm;
 689         bool arc_subsystem_valid;
 690         bool asf_firmware_present;
 691         bool autoneg;
 692         bool autoneg_failed;
 693         bool get_link_status;
 694         bool in_ifs_mode;
 695         bool report_tx_early;
 696         enum e1000_serdes_link_state serdes_link_state;
 697         bool serdes_has_link;
 698         bool tx_pkt_filtering;
 699 };
 700
 701 struct e1000_phy_info {
 702         struct e1000_phy_operations ops;
 703         enum e1000_phy_type type;
 704
 705         enum e1000_1000t_rx_status local_rx;
 706         enum e1000_1000t_rx_status remote_rx;
 707         enum e1000_ms_type ms_type;
 708         enum e1000_ms_type original_ms_type;
 709         enum e1000_rev_polarity cable_polarity;
 710         enum e1000_smart_speed smart_speed;
 711
 712         u32 addr;
 713         u32 id;
 714         u32 reset_delay_us;     /* in usec */
 715         u32 revision;
 716
 717         enum e1000_media_type media_type;
 718
 719         u16 autoneg_advertised;
 720         u16 autoneg_mask;
 721         u16 cable_length;
 722         u16 max_cable_length;
 723         u16 min_cable_length;
 724
 725         u8 mdix;
 726
 727         bool disable_polarity_correction;
 728         bool is_mdix;
 729         bool polarity_correction;
 730         bool reset_disable;
 731         bool speed_downgraded;
 732         bool autoneg_wait_to_complete;
 733 };
 734
 735 struct e1000_nvm_info {
 736         struct e1000_nvm_operations ops;
 737         enum e1000_nvm_type type;
 738         enum e1000_nvm_override override;
 739
 740         u32 flash_bank_size;
 741         u32 flash_base_addr;
 742
 743         u16 word_size;
 744         u16 delay_usec;
 745         u16 address_bits;
 746         u16 opcode_bits;
 747         u16 page_size;
 748 };
 749
 750 struct e1000_bus_info {
 751         enum e1000_bus_type type;
 752         enum e1000_bus_speed speed;
 753         enum e1000_bus_width width;
 754
 755         u16 func;
 756         u16 pci_cmd_word;
 757 };
 758
 759 struct e1000_fc_info {
 760         u32 high_water;         /* Flow control high-water mark */
 761         u32 low_water;          /* Flow control low-water mark */
 762         u16 pause_time;         /* Flow control pause timer */
 763         u16 refresh_time;       /* Flow control refresh timer */
 764         bool send_xon;          /* Flow control send XON */
 765         bool strict_ieee;       /* Strict IEEE mode */
 766         enum e1000_fc_mode current_mode; /* FC mode in effect */
 767         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
 768 };
 769
 770 struct e1000_dev_spec_82541 {
 771         enum e1000_dsp_config dsp_config;
 772         enum e1000_ffe_config ffe_config;
 773         u32 tx_fifo_head;
 774         u32 tx_fifo_start;
 775         u32 tx_fifo_size;
 776         u16 dsp_reset_counter;
 777         u16 spd_default;
 778         bool phy_init_script;
 779         bool ttl_workaround;
 780 };
 781
 782 struct e1000_dev_spec_82542 {
 783         bool dma_fairness;
 784 };
 785
 786 struct e1000_dev_spec_82543 {
 787         u32  tbi_compatibility;
 788         bool dma_fairness;
 789         bool init_phy_disabled;
 790 };
 791
 792 struct e1000_dev_spec_82571 {
 793         bool laa_is_present;
 794         u32 smb_counter;
 795 };
 796
 797 struct e1000_dev_spec_80003es2lan {
 798         bool  mdic_wa_enable;
 799 };
 800
 801 struct e1000_shadow_ram {
 802         u16  value;
 803         bool modified;
 804 };
 805
 806 #define E1000_SHADOW_RAM_WORDS          2048
 807
 808 struct e1000_dev_spec_ich8lan {
 809         bool kmrn_lock_loss_workaround_enabled;
 810         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 811         E1000_MUTEX nvm_mutex;
 812         E1000_MUTEX swflag_mutex;
 813         bool nvm_k1_enabled;
 814         bool eee_disable;
 815 };
 816
 817 struct e1000_hw {
 818         void *back;
 819
 820         u8 *hw_addr;
 821         u8 *flash_address;
 822         unsigned long io_base;
 823
 824         struct e1000_mac_info mac;
 825         struct e1000_fc_info fc;
 826         struct e1000_phy_info phy;
 827         struct e1000_nvm_info nvm;
 828         struct e1000_bus_info bus;
 829         struct e1000_host_mng_dhcp_cookie mng_cookie;
 830
 831         union {
 832                 struct e1000_dev_spec_82541     _82541;
 833                 struct e1000_dev_spec_82542     _82542;
 834                 struct e1000_dev_spec_82543     _82543;
 835                 struct e1000_dev_spec_82571     _82571;
 836                 struct e1000_dev_spec_80003es2lan _80003es2lan;
 837                 struct e1000_dev_spec_ich8lan   ich8lan;
 838         } dev_spec;
 839
 840         u16 device_id;
 841         u16 subsystem_vendor_id;
 842         u16 subsystem_device_id;
 843         u16 vendor_id;
 844
 845         u8 revision_id;
 846 };
 847
 848 #include "e1000_82541.h"
 849 #include "e1000_82543.h"
 850 #include "e1000_82571.h"
 851 #include "e1000_80003es2lan.h"
 852 #include "e1000_ich8lan.h"
 853
 854 /* These functions must be implemented by drivers */
 855 void e1000_pci_clear_mwi(struct e1000_hw *hw);
 856 void e1000_pci_set_mwi(struct e1000_hw *hw);
 857 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 858 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 859 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 860 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 861
 862 #ifdef __cplusplus
 863 }
 864 #endif
 865
 866 #endif  /* _E1000_HW_H_ */