usr/src/uts/common/io/e1000g/e1000_defines.h

   1 /*
   2  * This file is provided under a CDDLv1 license.  When using or
   3  * redistributing this file, you may do so under this license.
   4  * In redistributing this file this license must be included
   5  * and no other modification of this header file is permitted.
   6  *
   7  * CDDL LICENSE SUMMARY
   8  *
   9  * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
  10  *
  11  * The contents of this file are subject to the terms of Version
  12  * 1.0 of the Common Development and Distribution License (the "License").
  13  *
  14  * You should have received a copy of the License with this software.
  15  * You can obtain a copy of the License at
  16  *      http://www.opensolaris.org/os/licensing.
  17  * See the License for the specific language governing permissions
  18  * and limitations under the License.
  19  */
  20
  21 /*
  22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms of the CDDLv1.
  24  */
  25
  26 /*
  27  * Copyright (c) 2001-2010, Intel Corporation
  28  * All rights reserved.
  29  *
  30  * Redistribution and use in source and binary forms, with or without
  31  * modification, are permitted provided that the following conditions are met:
  32  *
  33  *  1. Redistributions of source code must retain the above copyright notice,
  34  *     this list of conditions and the following disclaimer.
  35  *
  36  *  2. Redistributions in binary form must reproduce the above copyright
  37  *     notice, this list of conditions and the following disclaimer in the
  38  *     documentation and/or other materials provided with the distribution.
  39  *
  40  *  3. Neither the name of the Intel Corporation nor the names of its
  41  *     contributors may be used to endorse or promote products derived from
  42  *     this software without specific prior written permission.
  43  *
  44  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  45  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  46  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  47  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  48  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  54  * POSSIBILITY OF SUCH DAMAGE.
  55  */
  56
  57 #ifndef _E1000_DEFINES_H_
  58 #define _E1000_DEFINES_H_
  59
  60 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
  61 #define REQ_TX_DESCRIPTOR_MULTIPLE      8
  62 #define REQ_RX_DESCRIPTOR_MULTIPLE      8
  63
  64 /* Definitions for power management and wakeup registers */
  65 /* Wake Up Control */
  66 #define E1000_WUC_APME          0x00000001 /* APM Enable */
  67 #define E1000_WUC_PME_EN        0x00000002 /* PME Enable */
  68 #define E1000_WUC_PME_STATUS    0x00000004 /* PME Status */
  69 #define E1000_WUC_APMPME        0x00000008 /* Assert PME on APM Wakeup */
  70 #define E1000_WUC_LSCWE         0x00000010 /* Link Status wake up enable */
  71 #define E1000_WUC_LSCWO         0x00000020 /* Link Status wake up override */
  72 #define E1000_WUC_SPM           0x80000000 /* Enable SPM */
  73 #define E1000_WUC_PHY_WAKE      0x00000100 /* if PHY supports wakeup */
  74
  75 /* Wake Up Filter Control */
  76 #define E1000_WUFC_LNKC 0x00000001      /* Link Status Change Wakeup Enable */
  77 #define E1000_WUFC_MAG  0x00000002      /* Magic Packet Wakeup Enable */
  78 #define E1000_WUFC_EX   0x00000004      /* Directed Exact Wakeup Enable */
  79 #define E1000_WUFC_MC   0x00000008      /* Directed Multicast Wakeup Enable */
  80 #define E1000_WUFC_BC   0x00000010      /* Broadcast Wakeup Enable */
  81 #define E1000_WUFC_ARP  0x00000020      /* ARP Request Packet Wakeup Enable */
  82 #define E1000_WUFC_IPV4 0x00000040      /* Directed IPv4 Packet Wakeup Enable */
  83 #define E1000_WUFC_IPV6 0x00000080      /* Directed IPv6 Packet Wakeup Enable */
  84 #define E1000_WUFC_IGNORE_TCO_PHY 0x00000800 /* Ignore WakeOn TCO packets */
  85 #define E1000_WUFC_FLX0_PHY     0x00001000 /* Flexible Filter 0 Enable */
  86 #define E1000_WUFC_FLX1_PHY     0x00002000 /* Flexible Filter 1 Enable */
  87 #define E1000_WUFC_FLX2_PHY     0x00004000 /* Flexible Filter 2 Enable */
  88 #define E1000_WUFC_FLX3_PHY     0x00008000 /* Flexible Filter 3 Enable */
  89 #define E1000_WUFC_FLX4_PHY     0x00000200 /* Flexible Filter 4 Enable */
  90 #define E1000_WUFC_FLX5_PHY     0x00000400 /* Flexible Filter 5 Enable */
  91 #define E1000_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
  92 #define E1000_WUFC_FLX0 0x00010000      /* Flexible Filter 0 Enable */
  93 #define E1000_WUFC_FLX1 0x00020000      /* Flexible Filter 1 Enable */
  94 #define E1000_WUFC_FLX2 0x00040000      /* Flexible Filter 2 Enable */
  95 #define E1000_WUFC_FLX3 0x00080000      /* Flexible Filter 3 Enable */
  96 #define E1000_WUFC_FLX4 0x00100000      /* Flexible Filter 4 Enable */
  97 #define E1000_WUFC_FLX5 0x00200000      /* Flexible Filter 5 Enable */
  98 /* Mask for all wakeup filters */
  99 #define E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF
 100 #define E1000_WUFC_FLX_OFFSET_PHY 12 /* Offset to the Flexible Filters bits */
 101 /* Mask for 4 flexible filters */
 102 #define E1000_WUFC_FLX_FILTERS_PHY_4    0x0000F000
 103 /* Mask for 6 wakeup filters */
 104 #define E1000_WUFC_ALL_FILTERS_PHY_6    0x0000F6FF
 105 /* Mask for 6 flexible filters */
 106 #define E1000_WUFC_FLX_FILTERS_PHY_6    0x0000F600
 107 #define E1000_WUFC_ALL_FILTERS  0x000F00FF /* Mask for all wakeup filters */
 108 /* Mask for all 6 wakeup filters */
 109 #define E1000_WUFC_ALL_FILTERS_6        0x003F00FF
 110 /* Offset to the Flexible Filters bits */
 111 #define E1000_WUFC_FLX_OFFSET   16
 112 /* Mask for the 4 flexible filters */
 113 #define E1000_WUFC_FLX_FILTERS  0x000F0000
 114 /* Mask for 6 flexible filters */
 115 #define E1000_WUFC_FLX_FILTERS_6  0x003F0000
 116
 117 /* Wake Up Status */
 118 #define E1000_WUS_LNKC                  E1000_WUFC_LNKC
 119 #define E1000_WUS_MAG                   E1000_WUFC_MAG
 120 #define E1000_WUS_EX                    E1000_WUFC_EX
 121 #define E1000_WUS_MC                    E1000_WUFC_MC
 122 #define E1000_WUS_BC                    E1000_WUFC_BC
 123 #define E1000_WUS_ARP                   E1000_WUFC_ARP
 124 #define E1000_WUS_IPV4                  E1000_WUFC_IPV4
 125 #define E1000_WUS_IPV6                  E1000_WUFC_IPV6
 126 #define E1000_WUS_FLX0_PHY              E1000_WUFC_FLX0_PHY
 127 #define E1000_WUS_FLX1_PHY              E1000_WUFC_FLX1_PHY
 128 #define E1000_WUS_FLX2_PHY              E1000_WUFC_FLX2_PHY
 129 #define E1000_WUS_FLX3_PHY              E1000_WUFC_FLX3_PHY
 130 #define E1000_WUS_FLX4_PHY              E1000_WUFC_FLX4_PHY
 131 #define E1000_WUS_FLX5_PHY              E1000_WUFC_FLX5_PHY
 132
 133 #define E1000_WUS_FLX_FILTERS_PHY_4     E1000_WUFC_FLX_FILTERS_PHY_4
 134 #define E1000_WUS_FLX0                  E1000_WUFC_FLX0
 135 #define E1000_WUS_FLX1                  E1000_WUFC_FLX1
 136 #define E1000_WUS_FLX2                  E1000_WUFC_FLX2
 137 #define E1000_WUS_FLX3                  E1000_WUFC_FLX3
 138 #define E1000_WUS_FLX4                  E1000_WUFC_FLX4
 139 #define E1000_WUS_FLX5                  E1000_WUFC_FLX5
 140
 141 #define E1000_WUS_FLX_FILTERS           E1000_WUFC_FLX_FILTERS
 142 #define E1000_WUS_FLX_FILTERS_6         E1000_WUFC_FLX_FILTERS_6
 143 #define E1000_WUS_FLX_FILTERS_PHY_6     E1000_WUFC_FLX_FILTERS_PHY_6
 144
 145 /* Wake Up Packet Length */
 146 #define E1000_WUPL_LENGTH_MASK  0x0FFF  /* Only the lower 12 bits are valid */
 147
 148 /* Four Flexible Filters are supported */
 149 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
 150 /* Six Flexible Filters are supported */
 151 #define E1000_FLEXIBLE_FILTER_COUNT_MAX_6   6
 152
 153 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
 154 #define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
 155
 156 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
 157 #define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6
 158 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
 159 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
 160
 161 /* Extended Device Control */
 162 #define E1000_CTRL_EXT_GPI0_EN  0x00000001  /* Maps SDP4 to GPI0 */
 163 #define E1000_CTRL_EXT_GPI1_EN  0x00000002  /* Maps SDP5 to GPI1 */
 164 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
 165 #define E1000_CTRL_EXT_GPI2_EN  0x00000004  /* Maps SDP6 to GPI2 */
 166 #define E1000_CTRL_EXT_GPI3_EN  0x00000008  /* Maps SDP7 to GPI3 */
 167 /* Reserved (bits 4,5) in >= 82575 */
 168 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */
 169 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */
 170 #define E1000_CTRL_EXT_PHY_INT  E1000_CTRL_EXT_SDP5_DATA
 171 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */
 172 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
 173 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
 174 #define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
 175 #define E1000_CTRL_EXT_SDP5_DIR  0x00000200 /* Direction of SDP5 0=in 1=out */
 176 #define E1000_CTRL_EXT_SDP6_DIR  0x00000400 /* Direction of SDP6 0=in 1=out */
 177 #define E1000_CTRL_EXT_SDP3_DIR  0x00000800 /* Direction of SDP3 0=in 1=out */
 178 #define E1000_CTRL_EXT_ASDCHK   0x00001000  /* Initiate an ASD sequence */
 179 #define E1000_CTRL_EXT_EE_RST   0x00002000  /* Reinitialize from EEPROM */
 180 #define E1000_CTRL_EXT_IPS      0x00004000  /* Invert Power State */
 181 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000  /* Speed Select Bypass */
 182 #define E1000_CTRL_EXT_RO_DIS   0x00020000  /* Relaxed Ordering disable */
 183 /* DMA Dynamic Clock Gating */
 184 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN   0x00080000
 185 #define E1000_CTRL_EXT_LINK_MODE_MASK   0x00C00000
 186 #define E1000_CTRL_EXT_LINK_MODE_GMII   0x00000000
 187 #define E1000_CTRL_EXT_LINK_MODE_TBI    0x00C00000
 188 #define E1000_CTRL_EXT_LINK_MODE_KMRN   0x00000000
 189 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES    0x00C00000
 190 #define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES    0x00800000
 191 #define E1000_CTRL_EXT_LINK_MODE_SGMII  0x00800000
 192 #define E1000_CTRL_EXT_EIAME            0x01000000
 193 #define E1000_CTRL_EXT_IRCA             0x00000001
 194 #define E1000_CTRL_EXT_WR_WMARK_MASK    0x03000000
 195 #define E1000_CTRL_EXT_WR_WMARK_256     0x00000000
 196 #define E1000_CTRL_EXT_WR_WMARK_320     0x01000000
 197 #define E1000_CTRL_EXT_WR_WMARK_384     0x02000000
 198 #define E1000_CTRL_EXT_WR_WMARK_448     0x03000000
 199 #define E1000_CTRL_EXT_CANC     0x04000000 /* Int delay cancellation */
 200 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
 201 /* IAME enable bit (27) was removed in >= 82575 */
 202 #define E1000_CTRL_EXT_IAME     0x08000000 /* Int acknowledge Auto-mask */
 203 /* packet buffer parity error detection enabled */
 204 #define E1000_CRTL_EXT_PB_PAREN         0x01000000
 205 /* descriptor FIFO parity error detection enable */
 206 #define E1000_CTRL_EXT_DF_PAREN         0x02000000
 207 #define E1000_CTRL_EXT_GHOST_PAREN      0x40000000
 208 #define E1000_CTRL_EXT_PBA_CLR          0x80000000      /* PBA Clear */
 209 #define E1000_CTRL_EXT_LSECCK           0x00001000
 210 #define E1000_CTRL_EXT_PHYPDEN          0x00100000
 211 #define E1000_I2CCMD_REG_ADDR_SHIFT     16
 212 #define E1000_I2CCMD_REG_ADDR           0x00FF0000
 213 #define E1000_I2CCMD_PHY_ADDR_SHIFT     24
 214 #define E1000_I2CCMD_PHY_ADDR           0x07000000
 215 #define E1000_I2CCMD_OPCODE_READ        0x08000000
 216 #define E1000_I2CCMD_OPCODE_WRITE       0x00000000
 217 #define E1000_I2CCMD_RESET              0x10000000
 218 #define E1000_I2CCMD_READY              0x20000000
 219 #define E1000_I2CCMD_INTERRUPT_ENA      0x40000000
 220 #define E1000_I2CCMD_ERROR              0x80000000
 221 #define E1000_MAX_SGMII_PHY_REG_ADDR    255
 222 #define E1000_I2CCMD_PHY_TIMEOUT        200
 223
 224 /* Receive Descriptor bit definitions */
 225 #define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
 226 #define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
 227 #define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
 228 #define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
 229 #define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
 230 #define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
 231 #define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
 232 #define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
 233 #define E1000_RXD_STAT_CRCV     0x100   /* Speculative CRC Valid */
 234 #define E1000_RXD_STAT_IPIDV    0x200   /* IP identification valid */
 235 #define E1000_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
 236 #define E1000_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
 237 #define E1000_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
 238 #define E1000_RXD_ERR_CE        0x01    /* CRC Error */
 239 #define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
 240 #define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
 241 #define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
 242 #define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
 243 #define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
 244 #define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
 245 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
 246 #define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
 247 #define E1000_RXD_SPC_PRI_SHIFT 13
 248 #define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
 249 #define E1000_RXD_SPC_CFI_SHIFT 12
 250
 251 #define E1000_RXDEXT_STATERR_CE         0x01000000
 252 #define E1000_RXDEXT_STATERR_SE         0x02000000
 253 #define E1000_RXDEXT_STATERR_SEQ        0x04000000
 254 #define E1000_RXDEXT_STATERR_CXE        0x10000000
 255 #define E1000_RXDEXT_STATERR_TCPE       0x20000000
 256 #define E1000_RXDEXT_STATERR_IPE        0x40000000
 257 #define E1000_RXDEXT_STATERR_RXE        0x80000000
 258
 259 #define E1000_RXDEXT_LSECH                      0x01000000
 260 #define E1000_RXDEXT_LSECE_MASK                 0x60000000
 261 #define E1000_RXDEXT_LSECE_NO_ERROR             0x00000000
 262 #define E1000_RXDEXT_LSECE_NO_SA_MATCH          0x20000000
 263 #define E1000_RXDEXT_LSECE_REPLAY_DETECT        0x40000000
 264 #define E1000_RXDEXT_LSECE_BAD_SIG              0x60000000
 265
 266 /* mask to determine if packets should be dropped due to frame errors */
 267 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
 268     E1000_RXD_ERR_CE  | \
 269     E1000_RXD_ERR_SE  | \
 270     E1000_RXD_ERR_SEQ | \
 271     E1000_RXD_ERR_CXE | \
 272     E1000_RXD_ERR_RXE)
 273
 274 /* Same mask, but for extended and packet split descriptors */
 275 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
 276     E1000_RXDEXT_STATERR_CE  | \
 277     E1000_RXDEXT_STATERR_SE  | \
 278     E1000_RXDEXT_STATERR_SEQ | \
 279     E1000_RXDEXT_STATERR_CXE | \
 280     E1000_RXDEXT_STATERR_RXE)
 281
 282 #define E1000_MRQC_ENABLE_MASK                  0x00000007
 283 #define E1000_MRQC_ENABLE_RSS_2Q                0x00000001
 284 #define E1000_MRQC_ENABLE_RSS_INT               0x00000004
 285 #define E1000_MRQC_RSS_FIELD_MASK               0xFFFF0000
 286 #define E1000_MRQC_RSS_FIELD_IPV4_TCP           0x00010000
 287 #define E1000_MRQC_RSS_FIELD_IPV4               0x00020000
 288 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX        0x00040000
 289 #define E1000_MRQC_RSS_FIELD_IPV6_EX            0x00080000
 290 #define E1000_MRQC_RSS_FIELD_IPV6               0x00100000
 291 #define E1000_MRQC_RSS_FIELD_IPV6_TCP           0x00200000
 292
 293 #define E1000_RXDPS_HDRSTAT_HDRSP               0x00008000
 294 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK         0x000003FF
 295
 296 /* Management Control */
 297 #define E1000_MANC_SMBUS_EN     0x00000001 /* SMBus Enabled - RO */
 298 #define E1000_MANC_ASF_EN       0x00000002 /* ASF Enabled - RO */
 299 #define E1000_MANC_R_ON_FORCE   0x00000004 /* Reset on Force TCO - RO */
 300 #define E1000_MANC_RMCP_EN      0x00000100 /* Enable RCMP 026Fh Filtering */
 301 #define E1000_MANC_0298_EN      0x00000200 /* Enable RCMP 0298h Filtering */
 302 #define E1000_MANC_IPV4_EN      0x00000400 /* Enable IPv4 */
 303 #define E1000_MANC_IPV6_EN      0x00000800 /* Enable IPv6 */
 304 #define E1000_MANC_SNAP_EN      0x00001000 /* Accept LLC/SNAP */
 305 #define E1000_MANC_ARP_EN       0x00002000 /* Enable ARP Request Filtering */
 306 /* Enable Neighbor Discovery Filtering */
 307 #define E1000_MANC_NEIGHBOR_EN  0x00004000
 308 #define E1000_MANC_ARP_RES_EN   0x00008000 /* Enable ARP response Filtering */
 309 #define E1000_MANC_TCO_RESET    0x00010000 /* TCO Reset Occurred */
 310 #define E1000_MANC_RCV_TCO_EN   0x00020000 /* Receive TCO Packets Enabled */
 311 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
 312 #define E1000_MANC_RCV_ALL      0x00080000 /* Receive All Enabled */
 313 #define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
 314 /* Enable MAC address filtering */
 315 #define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
 316 /* Enable MNG packets to host memory */
 317 #define E1000_MANC_EN_MNG2HOST          0x00200000
 318 /* Enable IP address filtering */
 319 #define E1000_MANC_EN_IP_ADDR_FILTER    0x00400000
 320 #define E1000_MANC_EN_XSUM_FILTER       0x00800000 /* Enable cksum filtering */
 321 #define E1000_MANC_BR_EN        0x01000000      /* Enable broadcast filtering */
 322 #define E1000_MANC_SMB_REQ      0x01000000      /* SMBus Request */
 323 #define E1000_MANC_SMB_GNT      0x02000000      /* SMBus Grant */
 324 #define E1000_MANC_SMB_CLK_IN   0x04000000      /* SMBus Clock In */
 325 #define E1000_MANC_SMB_DATA_IN  0x08000000      /* SMBus Data In */
 326 #define E1000_MANC_SMB_DATA_OUT 0x10000000      /* SMBus Data Out */
 327 #define E1000_MANC_SMB_CLK_OUT  0x20000000      /* SMBus Clock Out */
 328
 329 #define E1000_MANC_SMB_DATA_OUT_SHIFT   28      /* SMBus Data Out Shift */
 330 #define E1000_MANC_SMB_CLK_OUT_SHIFT    29      /* SMBus Clock Out Shift */
 331
 332 /* Receive Control */
 333 #define E1000_RCTL_RST          0x00000001      /* Software reset */
 334 #define E1000_RCTL_EN           0x00000002      /* enable */
 335 #define E1000_RCTL_SBP          0x00000004      /* store bad packet */
 336 #define E1000_RCTL_UPE          0x00000008      /* unicast promisc enable */
 337 #define E1000_RCTL_MPE          0x00000010      /* multicast promisc enable */
 338 #define E1000_RCTL_LPE          0x00000020      /* long packet enable */
 339 #define E1000_RCTL_LBM_NO       0x00000000      /* no loopback mode */
 340 #define E1000_RCTL_LBM_MAC      0x00000040      /* MAC loopback mode */
 341 #define E1000_RCTL_LBM_SLP      0x00000080      /* serial link loopback mode */
 342 #define E1000_RCTL_LBM_TCVR     0x000000C0      /* tcvr loopback mode */
 343 #define E1000_RCTL_DTYP_MASK    0x00000C00      /* Descriptor type mask */
 344 #define E1000_RCTL_DTYP_PS      0x00000400      /* Packet Split descriptor */
 345 #define E1000_RCTL_RDMTS_HALF   0x00000000      /* rx desc min thresh size */
 346 #define E1000_RCTL_RDMTS_QUAT   0x00000100      /* rx desc min thresh size */
 347 #define E1000_RCTL_RDMTS_EIGTH  0x00000200      /* rx desc min thresh size */
 348 #define E1000_RCTL_MO_SHIFT     12              /* multicast offset shift */
 349 #define E1000_RCTL_MO_0         0x00000000      /* multicast offset 11:0 */
 350 #define E1000_RCTL_MO_1         0x00001000      /* multicast offset 12:1 */
 351 #define E1000_RCTL_MO_2         0x00002000      /* multicast offset 13:2 */
 352 #define E1000_RCTL_MO_3         0x00003000      /* multicast offset 15:4 */
 353 #define E1000_RCTL_MDR          0x00004000      /* multicast desc ring 0 */
 354 #define E1000_RCTL_BAM          0x00008000      /* broadcast enable */
 355 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
 356 #define E1000_RCTL_SZ_2048      0x00000000      /* rx buffer size 2048 */
 357 #define E1000_RCTL_SZ_1024      0x00010000      /* rx buffer size 1024 */
 358 #define E1000_RCTL_SZ_512       0x00020000      /* rx buffer size 512 */
 359 #define E1000_RCTL_SZ_256       0x00030000      /* rx buffer size 256 */
 360 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
 361 #define E1000_RCTL_SZ_16384     0x00010000      /* rx buffer size 16384 */
 362 #define E1000_RCTL_SZ_8192      0x00020000      /* rx buffer size 8192 */
 363 #define E1000_RCTL_SZ_4096      0x00030000      /* rx buffer size 4096 */
 364 #define E1000_RCTL_VFE          0x00040000      /* vlan filter enable */
 365 #define E1000_RCTL_CFIEN        0x00080000      /* canonical form enable */
 366 #define E1000_RCTL_CFI          0x00100000      /* canonical form indicator */
 367 #define E1000_RCTL_DPF          0x00400000      /* discard pause frames */
 368 #define E1000_RCTL_PMCF         0x00800000      /* pass MAC control frames */
 369 #define E1000_RCTL_BSEX         0x02000000      /* Buffer size extension */
 370 #define E1000_RCTL_SECRC        0x04000000      /* Strip Ethernet CRC */
 371 #define E1000_RCTL_FLXBUF_MASK  0x78000000      /* Flexible buffer size */
 372 #define E1000_RCTL_FLXBUF_SHIFT 27              /* Flexible buffer shift */
 373
 374 /*
 375  * Use byte values for the following shift parameters
 376  * Usage:
 377  *      psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
 378  *              E1000_PSRCTL_BSIZE0_MASK) |
 379  *              ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
 380  *              E1000_PSRCTL_BSIZE1_MASK) |
 381  *              ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
 382  *              E1000_PSRCTL_BSIZE2_MASK) |
 383  *              ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
 384  *              E1000_PSRCTL_BSIZE3_MASK))
 385  * where value0 = [128..16256], default=256
 386  *      value1 = [1024..64512], default=4096
 387  *      value2 = [0..64512],    default=4096
 388  *      value3 = [0..64512],    default=0
 389  */
 390
 391 #define E1000_PSRCTL_BSIZE0_MASK        0x0000007F
 392 #define E1000_PSRCTL_BSIZE1_MASK        0x00003F00
 393 #define E1000_PSRCTL_BSIZE2_MASK        0x003F0000
 394 #define E1000_PSRCTL_BSIZE3_MASK        0x3F000000
 395
 396 #define E1000_PSRCTL_BSIZE0_SHIFT       7       /* Shift _right_ 7 */
 397 #define E1000_PSRCTL_BSIZE1_SHIFT       2       /* Shift _right_ 2 */
 398 #define E1000_PSRCTL_BSIZE2_SHIFT       6       /* Shift _left_ 6 */
 399 #define E1000_PSRCTL_BSIZE3_SHIFT       14      /* Shift _left_ 14 */
 400
 401 /* SWFW_SYNC Definitions */
 402 #define E1000_SWFW_EEP_SM       0x01
 403 #define E1000_SWFW_PHY0_SM      0x02
 404 #define E1000_SWFW_PHY1_SM      0x04
 405 #define E1000_SWFW_CSR_SM       0x08
 406
 407 /* FACTPS Definitions */
 408 #define E1000_FACTPS_LFS        0x40000000      /* LAN Function Select */
 409 /* Device Control */
 410 #define E1000_CTRL_FD   0x00000001      /* Full duplex.0=half; 1=full */
 411 #define E1000_CTRL_BEM  0x00000002      /* Endian Mode.0=little,1=big */
 412 #define E1000_CTRL_PRIOR 0x00000004     /* Priority on PCI. 0=rx,1=fair */
 413 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /* Block new Master reqs */
 414 #define E1000_CTRL_LRST 0x00000008      /* Link reset. 0=normal,1=reset */
 415 #define E1000_CTRL_TME  0x00000010      /* Test mode. 0=normal,1=test */
 416 #define E1000_CTRL_SLE  0x00000020      /* Serial Link on 0=dis,1=en */
 417 #define E1000_CTRL_ASDE 0x00000020      /* Auto-speed detect enable */
 418 #define E1000_CTRL_SLU  0x00000040      /* Set link up (Force Link) */
 419 #define E1000_CTRL_ILOS 0x00000080      /* Invert Loss-Of Signal */
 420 #define E1000_CTRL_SPD_SEL      0x00000300 /* Speed Select Mask */
 421 #define E1000_CTRL_SPD_10       0x00000000 /* Force 10Mb */
 422 #define E1000_CTRL_SPD_100      0x00000100 /* Force 100Mb */
 423 #define E1000_CTRL_SPD_1000     0x00000200 /* Force 1Gb */
 424 #define E1000_CTRL_BEM32        0x00000400 /* Big Endian 32 mode */
 425 #define E1000_CTRL_FRCSPD       0x00000800 /* Force Speed */
 426 #define E1000_CTRL_FRCDPX       0x00001000 /* Force Duplex */
 427 #define E1000_CTRL_D_UD_EN      0x00002000 /* Dock/Undock enable */
 428 /* Defined polarity of Dock/Undock indication in SDP[0] */
 429 #define E1000_CTRL_D_UD_POLARITY        0x00004000
 430 /* Reset both PHY ports, through PHYRST_N pin */
 431 #define E1000_CTRL_FORCE_PHY_RESET      0x00008000
 432 /* enable link status from external LINK_0 and LINK_1 pins */
 433 #define E1000_CTRL_EXT_LINK_EN          0x00010000
 434 #define E1000_CTRL_LANPHYPC_OVERRIDE    0x00010000 /* SW control of LANPHYPC */
 435 #define E1000_CTRL_LANPHYPC_VALUE       0x00020000 /* SW value of LANPHYPC */
 436 #define E1000_CTRL_SWDPIN0      0x00040000 /* SWDPIN 0 value */
 437 #define E1000_CTRL_SWDPIN1      0x00080000 /* SWDPIN 1 value */
 438 #define E1000_CTRL_SWDPIN2      0x00100000 /* SWDPIN 2 value */
 439 #define E1000_CTRL_SWDPIN3      0x00200000 /* SWDPIN 3 value */
 440 #define E1000_CTRL_SWDPIO0      0x00400000 /* SWDPIN 0 Input or output */
 441 #define E1000_CTRL_SWDPIO1      0x00800000 /* SWDPIN 1 input or output */
 442 #define E1000_CTRL_SWDPIO2      0x01000000 /* SWDPIN 2 input or output */
 443 #define E1000_CTRL_SWDPIO3      0x02000000 /* SWDPIN 3 input or output */
 444 #define E1000_CTRL_RST          0x04000000 /* Global reset */
 445 #define E1000_CTRL_RFCE         0x08000000 /* Receive Flow Control enable */
 446 #define E1000_CTRL_TFCE         0x10000000 /* Transmit flow control enable */
 447 #define E1000_CTRL_RTE          0x20000000 /* Routing tag enable */
 448 #define E1000_CTRL_VME          0x40000000 /* IEEE VLAN mode enable */
 449 #define E1000_CTRL_PHY_RST      0x80000000 /* PHY Reset */
 450 /* Initiate an interrupt to ME */
 451 #define E1000_CTRL_SW2FW_INT    0x02000000
 452 #define E1000_CTRL_I2C_ENA      0x02000000 /* I2C enable */
 453
 454 /*
 455  * Bit definitions for the Management Data IO (MDIO) and Management Data
 456  * Clock (MDC) pins in the Device Control Register.
 457  */
 458 #define E1000_CTRL_PHY_RESET_DIR        E1000_CTRL_SWDPIO0
 459 #define E1000_CTRL_PHY_RESET            E1000_CTRL_SWDPIN0
 460 #define E1000_CTRL_MDIO_DIR             E1000_CTRL_SWDPIO2
 461 #define E1000_CTRL_MDIO                 E1000_CTRL_SWDPIN2
 462 #define E1000_CTRL_MDC_DIR              E1000_CTRL_SWDPIO3
 463 #define E1000_CTRL_MDC                  E1000_CTRL_SWDPIN3
 464 #define E1000_CTRL_PHY_RESET_DIR4       E1000_CTRL_EXT_SDP4_DIR
 465 #define E1000_CTRL_PHY_RESET4           E1000_CTRL_EXT_SDP4_DATA
 466
 467 #define E1000_CONNSW_ENRGSRC            0x4
 468 #define E1000_PCS_CFG_PCS_EN            8
 469 #define E1000_PCS_LCTL_FLV_LINK_UP      1
 470 #define E1000_PCS_LCTL_FSV_10           0
 471 #define E1000_PCS_LCTL_FSV_100          2
 472 #define E1000_PCS_LCTL_FSV_1000         4
 473 #define E1000_PCS_LCTL_FDV_FULL         8
 474 #define E1000_PCS_LCTL_FSD              0x10
 475 #define E1000_PCS_LCTL_FORCE_LINK       0x20
 476 #define E1000_PCS_LCTL_LOW_LINK_LATCH   0x40
 477 #define E1000_PCS_LCTL_FORCE_FCTRL      0x80
 478 #define E1000_PCS_LCTL_AN_ENABLE        0x10000
 479 #define E1000_PCS_LCTL_AN_RESTART       0x20000
 480 #define E1000_PCS_LCTL_AN_TIMEOUT       0x40000
 481 #define E1000_PCS_LCTL_AN_SGMII_BYPASS  0x80000
 482 #define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000
 483 #define E1000_PCS_LCTL_FAST_LINK_TIMER  0x1000000
 484 #define E1000_PCS_LCTL_LINK_OK_FIX      0x2000000
 485 #define E1000_PCS_LCTL_CRS_ON_NI        0x4000000
 486 #define E1000_ENABLE_SERDES_LOOPBACK    0x0410
 487
 488 #define E1000_PCS_LSTS_LINK_OK          1
 489 #define E1000_PCS_LSTS_SPEED_10         0
 490 #define E1000_PCS_LSTS_SPEED_100        2
 491 #define E1000_PCS_LSTS_SPEED_1000       4
 492 #define E1000_PCS_LSTS_DUPLEX_FULL      8
 493 #define E1000_PCS_LSTS_SYNK_OK          0x10
 494 #define E1000_PCS_LSTS_AN_COMPLETE      0x10000
 495 #define E1000_PCS_LSTS_AN_PAGE_RX       0x20000
 496 #define E1000_PCS_LSTS_AN_TIMED_OUT     0x40000
 497 #define E1000_PCS_LSTS_AN_REMOTE_FAULT  0x80000
 498 #define E1000_PCS_LSTS_AN_ERROR_RWS     0x100000
 499
 500 /* Device Status */
 501 #define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
 502 #define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
 503 #define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
 504 #define E1000_STATUS_FUNC_SHIFT 2
 505 #define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
 506 #define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
 507 #define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
 508 #define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
 509 #define E1000_STATUS_SPEED_MASK 0x000000C0
 510 #define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
 511 #define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
 512 #define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
 513 #define E1000_STATUS_LAN_INIT_DONE 0x00000200   /* Lan Init Completion by NVM */
 514 #define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
 515 #define E1000_STATUS_PHYRA      0x00000400      /* PHY Reset Asserted */
 516 /* Change in Dock/Undock state. Clear on write '0'. */
 517 #define E1000_STATUS_DOCK_CI    0x00000800
 518 /* Master request status */
 519 #define E1000_STATUS_GIO_MASTER_ENABLE  0x00080000
 520 #define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
 521 #define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
 522 #define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
 523 #define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
 524 #define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
 525 #define E1000_STATUS_BMC_SKU_0  0x00100000      /* BMC USB redirect disabled */
 526 #define E1000_STATUS_BMC_SKU_1  0x00200000      /* BMC SRAM disabled */
 527 #define E1000_STATUS_BMC_SKU_2  0x00400000      /* BMC SDRAM disabled */
 528 #define E1000_STATUS_BMC_CRYPTO 0x00800000      /* BMC crypto disabled */
 529 /* BMC external code execution disabled */
 530 #define E1000_STATUS_BMC_LITE     0x01000000
 531 #define E1000_STATUS_RGMII_ENABLE 0x02000000    /* RGMII disabled */
 532 #define E1000_STATUS_FUSE_8       0x04000000
 533 #define E1000_STATUS_FUSE_9       0x08000000
 534 #define E1000_STATUS_SERDES0_DIS  0x10000000    /* SERDES disabled on port 0 */
 535 #define E1000_STATUS_SERDES1_DIS  0x20000000    /* SERDES disabled on port 1 */
 536
 537 /* Constants used to interpret the masked PCI-X bus speed. */
 538 /* PCI-X bus speed 50-66 MHz */
 539 #define E1000_STATUS_PCIX_SPEED_66  0x00000000
 540 /* PCI-X bus speed 66-100 MHz */
 541 #define E1000_STATUS_PCIX_SPEED_100 0x00004000
 542 /* PCI-X bus speed 100-133 MHz */
 543 #define E1000_STATUS_PCIX_SPEED_133 0x00008000
 544
 545 #define SPEED_10        10
 546 #define SPEED_100       100
 547 #define SPEED_1000      1000
 548 #define HALF_DUPLEX     1
 549 #define FULL_DUPLEX     2
 550
 551 #define PHY_FORCE_TIME  20
 552
 553 #define ADVERTISE_10_HALF       0x0001
 554 #define ADVERTISE_10_FULL       0x0002
 555 #define ADVERTISE_100_HALF      0x0004
 556 #define ADVERTISE_100_FULL      0x0008
 557 #define ADVERTISE_1000_HALF     0x0010  /* Not used, just FYI */
 558 #define ADVERTISE_1000_FULL     0x0020
 559
 560 /* 1000/H is not supported, nor spec-compliant. */
 561 #define E1000_ALL_SPEED_DUPLEX  (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
 562                                 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
 563                                                 ADVERTISE_1000_FULL)
 564 #define E1000_ALL_NOT_GIG       (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
 565                                 ADVERTISE_100_HALF | ADVERTISE_100_FULL)
 566 #define E1000_ALL_100_SPEED     (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
 567 #define E1000_ALL_10_SPEED      (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
 568 #define E1000_ALL_FULL_DUPLEX   (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
 569                                                 ADVERTISE_1000_FULL)
 570 #define E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
 571
 572 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
 573
 574 /* LED Control */
 575 #define E1000_PHY_LED0_MODE_MASK        0x00000007
 576 #define E1000_PHY_LED0_IVRT             0x00000008
 577 #define E1000_PHY_LED0_BLINK            0x00000010
 578 #define E1000_PHY_LED0_MASK             0x0000001F
 579
 580 #define E1000_LEDCTL_LED0_MODE_MASK     0x0000000F
 581 #define E1000_LEDCTL_LED0_MODE_SHIFT    0
 582 #define E1000_LEDCTL_LED0_BLINK_RATE    0x00000020
 583 #define E1000_LEDCTL_LED0_IVRT          0x00000040
 584 #define E1000_LEDCTL_LED0_BLINK         0x00000080
 585 #define E1000_LEDCTL_LED1_MODE_MASK     0x00000F00
 586 #define E1000_LEDCTL_LED1_MODE_SHIFT    8
 587 #define E1000_LEDCTL_LED1_BLINK_RATE    0x00002000
 588 #define E1000_LEDCTL_LED1_IVRT          0x00004000
 589 #define E1000_LEDCTL_LED1_BLINK         0x00008000
 590 #define E1000_LEDCTL_LED2_MODE_MASK     0x000F0000
 591 #define E1000_LEDCTL_LED2_MODE_SHIFT    16
 592 #define E1000_LEDCTL_LED2_BLINK_RATE    0x00200000
 593 #define E1000_LEDCTL_LED2_IVRT          0x00400000
 594 #define E1000_LEDCTL_LED2_BLINK         0x00800000
 595 #define E1000_LEDCTL_LED3_MODE_MASK     0x0F000000
 596 #define E1000_LEDCTL_LED3_MODE_SHIFT    24
 597 #define E1000_LEDCTL_LED3_BLINK_RATE    0x20000000
 598 #define E1000_LEDCTL_LED3_IVRT          0x40000000
 599 #define E1000_LEDCTL_LED3_BLINK         0x80000000
 600
 601 #define E1000_LEDCTL_MODE_LINK_10_1000  0x0
 602 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
 603 #define E1000_LEDCTL_MODE_LINK_UP       0x2
 604 #define E1000_LEDCTL_MODE_ACTIVITY      0x3
 605 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
 606 #define E1000_LEDCTL_MODE_LINK_10       0x5
 607 #define E1000_LEDCTL_MODE_LINK_100      0x6
 608 #define E1000_LEDCTL_MODE_LINK_1000     0x7
 609 #define E1000_LEDCTL_MODE_PCIX_MODE     0x8
 610 #define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
 611 #define E1000_LEDCTL_MODE_COLLISION     0xA
 612 #define E1000_LEDCTL_MODE_BUS_SPEED     0xB
 613 #define E1000_LEDCTL_MODE_BUS_SIZE      0xC
 614 #define E1000_LEDCTL_MODE_PAUSED        0xD
 615 #define E1000_LEDCTL_MODE_LED_ON        0xE
 616 #define E1000_LEDCTL_MODE_LED_OFF       0xF
 617
 618 /* Transmit Descriptor bit definitions */
 619 #define E1000_TXD_DTYP_D        0x00100000      /* Data Descriptor */
 620 #define E1000_TXD_DTYP_C        0x00000000      /* Context Descriptor */
 621 #define E1000_TXD_POPTS_SHIFT   8               /* POPTS shift */
 622 #define E1000_TXD_POPTS_IXSM    0x01            /* Insert IP checksum */
 623 #define E1000_TXD_POPTS_TXSM    0x02            /* Insert TCP/UDP checksum */
 624 #define E1000_TXD_CMD_EOP       0x01000000      /* End of Packet */
 625 #define E1000_TXD_CMD_IFCS      0x02000000      /* Insert FCS (Ethernet CRC) */
 626 #define E1000_TXD_CMD_IC        0x04000000      /* Insert Checksum */
 627 #define E1000_TXD_CMD_RS        0x08000000      /* Report Status */
 628 #define E1000_TXD_CMD_RPS       0x10000000      /* Report Packet Sent */
 629 /* Descriptor extension (0 = legacy) */
 630 #define E1000_TXD_CMD_DEXT      0x20000000
 631 #define E1000_TXD_CMD_VLE       0x40000000      /* Add VLAN tag */
 632 #define E1000_TXD_CMD_IDE       0x80000000      /* Enable Tidv register */
 633 #define E1000_TXD_STAT_DD       0x00000001      /* Descriptor Done */
 634 #define E1000_TXD_STAT_EC       0x00000002      /* Excess Collisions */
 635 #define E1000_TXD_STAT_LC       0x00000004      /* Late Collisions */
 636 #define E1000_TXD_STAT_TU       0x00000008      /* Transmit underrun */
 637 #define E1000_TXD_CMD_TCP       0x01000000      /* TCP packet */
 638 #define E1000_TXD_CMD_IP        0x02000000      /* IP packet */
 639 #define E1000_TXD_CMD_TSE       0x04000000      /* TCP Seg enable */
 640 #define E1000_TXD_STAT_TC       0x00000004      /* Tx Underrun */
 641 /* Extended desc bits for Linksec and timesync */
 642 #define E1000_TXD_CMD_LINKSEC   0x10000000      /* Apply LinkSec on packet */
 643 #define E1000_TXD_EXTCMD_TSTAMP 0x00000010      /* IEEE1588 Timestamp packet */
 644
 645 /* Transmit Control */
 646 #define E1000_TCTL_RST  0x00000001      /* software reset */
 647 #define E1000_TCTL_EN   0x00000002      /* enable tx */
 648 #define E1000_TCTL_BCE  0x00000004      /* busy check enable */
 649 #define E1000_TCTL_PSP  0x00000008      /* pad short packets */
 650 #define E1000_TCTL_CT   0x00000ff0      /* collision threshold */
 651 #define E1000_TCTL_COLD 0x003ff000      /* collision distance */
 652 #define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
 653 #define E1000_TCTL_PBE  0x00800000      /* Packet Burst Enable */
 654 #define E1000_TCTL_RTLC 0x01000000      /* Re-transmit on late collision */
 655 #define E1000_TCTL_NRTU 0x02000000      /* No Re-transmit on underrun */
 656 #define E1000_TCTL_MULR 0x10000000      /* Multiple request support */
 657
 658 /* Transmit Arbitration Count */
 659 #define E1000_TARC0_ENABLE      0x00000400      /* Enable Tx Queue 0 */
 660
 661 /* SerDes Control */
 662 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
 663
 664 /* Receive Checksum Control */
 665 #define E1000_RXCSUM_PCSS_MASK  0x000000FF      /* Packet Checksum Start */
 666 #define E1000_RXCSUM_IPOFL      0x00000100      /* IPv4 checksum offload */
 667 #define E1000_RXCSUM_TUOFL      0x00000200      /* TCP / UDP checksum offload */
 668 #define E1000_RXCSUM_IPV6OFL    0x00000400      /* IPv6 checksum offload */
 669 #define E1000_RXCSUM_CRCOFL     0x00000800      /* CRC32 offload enable */
 670 #define E1000_RXCSUM_IPPCSE     0x00001000      /* IP payload checksum enable */
 671 #define E1000_RXCSUM_PCSD       0x00002000      /* packet checksum disabled */
 672
 673 /* Header split receive */
 674 #define E1000_RFCTL_ISCSI_DIS           0x00000001
 675 #define E1000_RFCTL_ISCSI_DWC_MASK      0x0000003E
 676 #define E1000_RFCTL_ISCSI_DWC_SHIFT     1
 677 #define E1000_RFCTL_NFSW_DIS            0x00000040
 678 #define E1000_RFCTL_NFSR_DIS            0x00000080
 679 #define E1000_RFCTL_NFS_VER_MASK        0x00000300
 680 #define E1000_RFCTL_NFS_VER_SHIFT       8
 681 #define E1000_RFCTL_IPV6_DIS            0x00000400
 682 #define E1000_RFCTL_IPV6_XSUM_DIS       0x00000800
 683 #define E1000_RFCTL_ACK_DIS             0x00001000
 684 #define E1000_RFCTL_ACKD_DIS            0x00002000
 685 #define E1000_RFCTL_IPFRSP_DIS          0x00004000
 686 #define E1000_RFCTL_EXTEN               0x00008000
 687 #define E1000_RFCTL_IPV6_EX_DIS         0x00010000
 688 #define E1000_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
 689 #define E1000_RFCTL_LEF                 0x00040000
 690
 691 /* Collision related configuration parameters */
 692 #define E1000_COLLISION_THRESHOLD       15
 693 #define E1000_CT_SHIFT                  4
 694 #define E1000_COLLISION_DISTANCE        63
 695 #define E1000_COLD_SHIFT                12
 696
 697 /* Default values for the transmit IPG register */
 698 #define DEFAULT_82542_TIPG_IPGT         10
 699 #define DEFAULT_82543_TIPG_IPGT_FIBER   9
 700 #define DEFAULT_82543_TIPG_IPGT_COPPER  8
 701
 702 #define E1000_TIPG_IPGT_MASK    0x000003FF
 703 #define E1000_TIPG_IPGR1_MASK   0x000FFC00
 704 #define E1000_TIPG_IPGR2_MASK   0x3FF00000
 705
 706 #define DEFAULT_82542_TIPG_IPGR1        2
 707 #define DEFAULT_82543_TIPG_IPGR1        8
 708 #define E1000_TIPG_IPGR1_SHIFT          10
 709
 710 #define DEFAULT_82542_TIPG_IPGR2        10
 711 #define DEFAULT_82543_TIPG_IPGR2        6
 712 #define DEFAULT_80003ES2LAN_TIPG_IPGR2  7
 713 #define E1000_TIPG_IPGR2_SHIFT          20
 714
 715 /* Ethertype field values */
 716 #define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
 717
 718 #define ETHERNET_FCS_SIZE       4
 719 #define MAX_JUMBO_FRAME_SIZE    0x3F00
 720
 721 /* Extended Configuration Control and Size */
 722 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP     0x00000020
 723 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE      0x00000001
 724 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE      0x00000008
 725 #define E1000_EXTCNF_CTRL_SWFLAG                0x00000020
 726 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG          0x00000080
 727 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK  0x00FF0000
 728 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
 729 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK  0x0FFF0000
 730 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
 731
 732 #define E1000_PHY_CTRL_SPD_EN           0x00000001
 733 #define E1000_PHY_CTRL_D0A_LPLU         0x00000002
 734 #define E1000_PHY_CTRL_NOND0A_LPLU      0x00000004
 735 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
 736 #define E1000_PHY_CTRL_GBE_DISABLE      0x00000040
 737
 738 #define E1000_KABGTXD_BGSQLBIAS         0x00050000
 739
 740 /* PBA constants */
 741 #define E1000_PBA_6K    0x0006  /* 6KB */
 742 #define E1000_PBA_8K    0x0008  /* 8KB */
 743 #define E1000_PBA_10K   0x000A  /* 10KB */
 744 #define E1000_PBA_12K   0x000C  /* 12KB */
 745 #define E1000_PBA_14K   0x000E  /* 14KB */
 746 #define E1000_PBA_16K   0x0010  /* 16KB */
 747 #define E1000_PBA_18K   0x0012
 748 #define E1000_PBA_20K   0x0014
 749 #define E1000_PBA_22K   0x0016
 750 #define E1000_PBA_24K   0x0018
 751 #define E1000_PBA_26K   0x001A
 752 #define E1000_PBA_30K   0x001E
 753 #define E1000_PBA_32K   0x0020
 754 #define E1000_PBA_34K   0x0022
 755 #define E1000_PBA_35K   0x0023
 756 #define E1000_PBA_38K   0x0026
 757 #define E1000_PBA_40K   0x0028
 758 #define E1000_PBA_48K   0x0030  /* 48KB */
 759 #define E1000_PBA_64K   0x0040  /* 64KB */
 760
 761 #define E1000_PBS_16K   E1000_PBA_16K
 762 #define E1000_PBS_24K   E1000_PBA_24K
 763
 764 #define IFS_MAX         80
 765 #define IFS_MIN         40
 766 #define IFS_RATIO       4
 767 #define IFS_STEP        10
 768 #define MIN_NUM_XMITS   1000
 769
 770 /* SW Semaphore Register */
 771 #define E1000_SWSM_SMBI         0x00000001      /* Driver Semaphore bit */
 772 #define E1000_SWSM_SWESMBI      0x00000002      /* FW Semaphore bit */
 773 #define E1000_SWSM_WMNG         0x00000004      /* Wake MNG Clock */
 774 #define E1000_SWSM_DRV_LOAD     0x00000008      /* Driver Loaded Bit */
 775
 776 /* Secondary driver semaphore bit */
 777 #define E1000_SWSM2_LOCK        0x00000002
 778
 779 /* Interrupt Cause Read */
 780 #define E1000_ICR_TXDW          0x00000001      /* Transmit desc written back */
 781 #define E1000_ICR_TXQE          0x00000002      /* Transmit Queue empty */
 782 #define E1000_ICR_LSC           0x00000004      /* Link Status Change */
 783 #define E1000_ICR_RXSEQ         0x00000008      /* rx sequence error */
 784 #define E1000_ICR_RXDMT0        0x00000010      /* rx desc min. threshold (0) */
 785 #define E1000_ICR_RXO           0x00000040      /* rx overrun */
 786 #define E1000_ICR_RXT0          0x00000080      /* rx timer intr (ring 0) */
 787 #define E1000_ICR_VMMB          0x00000100      /* VM MB event */
 788 #define E1000_ICR_MDAC          0x00000200      /* MDIO access complete */
 789 #define E1000_ICR_RXCFG         0x00000400      /* Rx /c/ ordered set */
 790 #define E1000_ICR_GPI_EN0       0x00000800      /* GP Int 0 */
 791 #define E1000_ICR_GPI_EN1       0x00001000      /* GP Int 1 */
 792 #define E1000_ICR_GPI_EN2       0x00002000      /* GP Int 2 */
 793 #define E1000_ICR_GPI_EN3       0x00004000      /* GP Int 3 */
 794 #define E1000_ICR_TXD_LOW       0x00008000
 795 #define E1000_ICR_SRPD          0x00010000
 796 #define E1000_ICR_ACK           0x00020000      /* Receive Ack frame */
 797 #define E1000_ICR_MNG           0x00040000      /* Manageability event */
 798 #define E1000_ICR_DOCK          0x00080000      /* Dock/Undock */
 799 /* If this bit asserted, the driver should claim the interrupt */
 800 #define E1000_ICR_INT_ASSERTED  0x80000000
 801 /* Q0 Rx desc FIFO parity error */
 802 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000
 803 /* Q0 Tx desc FIFO parity error */
 804 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000
 805 /* host arb read buffer parity err */
 806 #define E1000_ICR_HOST_ARB_PAR  0x00400000
 807 /* packet buffer parity error */
 808 #define E1000_ICR_PB_PAR        0x00800000
 809 /* Q1 Rx desc FIFO parity error */
 810 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000
 811 /* Q1 Tx desc FIFO parity error */
 812 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000
 813 /* all parity error bits */
 814 #define E1000_ICR_ALL_PARITY    0x03F00000
 815 /* FW changed the status of DISSW bit in the FWSM */
 816 #define E1000_ICR_DSW           0x00000020
 817 /* LAN connected device generates an interrupt */
 818 #define E1000_ICR_PHYINT        0x00001000
 819 /* NIC DMA out of sync */
 820 #define E1000_ICR_DOUTSYNC      0x10000000
 821 /* ME hardware reset occurs */
 822 #define E1000_ICR_EPRST         0x00100000
 823 #define E1000_ICR_RXQ0          0x00100000      /* Rx Queue 0 Interrupt */
 824 #define E1000_ICR_RXQ1          0x00200000      /* Rx Queue 1 Interrupt */
 825 #define E1000_ICR_TXQ0          0x00400000      /* Tx Queue 0 Interrupt */
 826 #define E1000_ICR_TXQ1          0x00800000      /* Tx Queue 1 Interrupt */
 827 #define E1000_ICR_OTHER         0x01000000      /* Other Interrupts */
 828
 829 /* PBA ECC Register */
 830 #define E1000_PBA_ECC_COUNTER_MASK      0xFFF00000 /* ECC counter mask */
 831 #define E1000_PBA_ECC_COUNTER_SHIFT     20      /* ECC counter shift value */
 832 /* Enable ECC error correction */
 833 #define E1000_PBA_ECC_CORR_EN           0x00000001
 834 #define E1000_PBA_ECC_STAT_CLR          0x00000002 /* Clear ECC error counter */
 835 /* Enable ICR bit 5 on ECC error */
 836 #define E1000_PBA_ECC_INT_EN            0x00000004
 837
 838 /*
 839  * This defines the bits that are set in the Interrupt Mask
 840  * Set/Read Register.  Each bit is documented below:
 841  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 842  *   o RXSEQ  = Receive Sequence Error
 843  */
 844 #define POLL_IMS_ENABLE_MASK    ( \
 845     E1000_IMS_RXDMT0 | \
 846     E1000_IMS_RXSEQ)
 847
 848 /*
 849  * This defines the bits that are set in the Interrupt Mask
 850  * Set/Read Register.  Each bit is documented below:
 851  *   o RXT0   = Receiver Timer Interrupt (ring 0)
 852  *   o TXDW   = Transmit Descriptor Written Back
 853  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 854  *   o RXSEQ  = Receive Sequence Error
 855  *   o LSC    = Link Status Change
 856  */
 857 #define IMS_ENABLE_MASK ( \
 858     E1000_IMS_RXT0   | \
 859     E1000_IMS_TXDW   | \
 860     E1000_IMS_RXDMT0 | \
 861     E1000_IMS_RXSEQ  | \
 862     E1000_IMS_LSC)
 863
 864 /* Interrupt Mask Set */
 865 #define E1000_IMS_TXDW          E1000_ICR_TXDW  /* Tx desc written back */
 866 #define E1000_IMS_TXQE          E1000_ICR_TXQE  /* Transmit Queue empty */
 867 #define E1000_IMS_LSC           E1000_ICR_LSC   /* Link Status Change */
 868 #define E1000_IMS_VMMB          E1000_ICR_VMMB  /* Mail box activity */
 869 #define E1000_IMS_RXSEQ         E1000_ICR_RXSEQ /* rx sequence error */
 870 #define E1000_IMS_RXDMT0        E1000_ICR_RXDMT0 /* rx desc min. threshold */
 871 #define E1000_IMS_RXO           E1000_ICR_RXO   /* rx overrun */
 872 #define E1000_IMS_RXT0          E1000_ICR_RXT0  /* rx timer intr */
 873 #define E1000_IMS_MDAC          E1000_ICR_MDAC  /* MDIO access complete */
 874 #define E1000_IMS_RXCFG         E1000_ICR_RXCFG /* Rx /c/ ordered set */
 875 #define E1000_IMS_GPI_EN0       E1000_ICR_GPI_EN0       /* GP Int 0 */
 876 #define E1000_IMS_GPI_EN1       E1000_ICR_GPI_EN1       /* GP Int 1 */
 877 #define E1000_IMS_GPI_EN2       E1000_ICR_GPI_EN2       /* GP Int 2 */
 878 #define E1000_IMS_GPI_EN3       E1000_ICR_GPI_EN3       /* GP Int 3 */
 879 #define E1000_IMS_TXD_LOW       E1000_ICR_TXD_LOW
 880 #define E1000_IMS_SRPD          E1000_ICR_SRPD
 881 #define E1000_IMS_ACK           E1000_ICR_ACK   /* Receive Ack frame */
 882 #define E1000_IMS_MNG           E1000_ICR_MNG   /* Manageability event */
 883 #define E1000_IMS_DOCK          E1000_ICR_DOCK  /* Dock/Undock */
 884 /* Q0 Rx desc FIFO parity error */
 885 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
 886 /* Q0 Tx desc FIFO parity error */
 887 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
 888 /* host arb read buffer parity error */
 889 #define E1000_IMS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR
 890 /* packet buffer parity error */
 891 #define E1000_IMS_PB_PAR        E1000_ICR_PB_PAR
 892 /* Q1 Rx desc FIFO parity error */
 893 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
 894 /* Q1 Tx desc FIFO parity error */
 895 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
 896 #define E1000_IMS_DSW           E1000_ICR_DSW
 897 #define E1000_IMS_PHYINT        E1000_ICR_PHYINT
 898 #define E1000_IMS_DOUTSYNC      E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
 899 #define E1000_IMS_EPRST         E1000_ICR_EPRST
 900 #define E1000_IMS_RXQ0          E1000_ICR_RXQ0  /* Rx Queue 0 Interrupt */
 901 #define E1000_IMS_RXQ1          E1000_ICR_RXQ1  /* Rx Queue 1 Interrupt */
 902 #define E1000_IMS_TXQ0          E1000_ICR_TXQ0  /* Tx Queue 0 Interrupt */
 903 #define E1000_IMS_TXQ1          E1000_ICR_TXQ1  /* Tx Queue 1 Interrupt */
 904 #define E1000_IMS_OTHER         E1000_ICR_OTHER /* Other Interrupts */
 905
 906 /* Interrupt Cause Set */
 907 #define E1000_ICS_TXDW          E1000_ICR_TXDW  /* Tx desc written back */
 908 #define E1000_ICS_TXQE          E1000_ICR_TXQE  /* Transmit Queue empty */
 909 #define E1000_ICS_LSC           E1000_ICR_LSC   /* Link Status Change */
 910 #define E1000_ICS_RXSEQ         E1000_ICR_RXSEQ /* rx sequence error */
 911 #define E1000_ICS_RXDMT0        E1000_ICR_RXDMT0 /* rx desc min. threshold */
 912 #define E1000_ICS_RXO           E1000_ICR_RXO   /* rx overrun */
 913 #define E1000_ICS_RXT0          E1000_ICR_RXT0  /* rx timer intr */
 914 #define E1000_ICS_MDAC          E1000_ICR_MDAC  /* MDIO access complete */
 915 #define E1000_ICS_RXCFG         E1000_ICR_RXCFG /* Rx /c/ ordered set */
 916 #define E1000_ICS_GPI_EN0       E1000_ICR_GPI_EN0 /* GP Int 0 */
 917 #define E1000_ICS_GPI_EN1       E1000_ICR_GPI_EN1 /* GP Int 1 */
 918 #define E1000_ICS_GPI_EN2       E1000_ICR_GPI_EN2 /* GP Int 2 */
 919 #define E1000_ICS_GPI_EN3       E1000_ICR_GPI_EN3 /* GP Int 3 */
 920 #define E1000_ICS_TXD_LOW       E1000_ICR_TXD_LOW
 921 #define E1000_ICS_SRPD          E1000_ICR_SRPD
 922 #define E1000_ICS_ACK           E1000_ICR_ACK   /* Receive Ack frame */
 923 #define E1000_ICS_MNG           E1000_ICR_MNG   /* Manageability event */
 924 #define E1000_ICS_DOCK          E1000_ICR_DOCK  /* Dock/Undock */
 925 /* Q0 Rx desc FIFO parity error */
 926 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
 927 /* Q0 Tx desc FIFO parity error */
 928 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
 929 /* host arb read buffer parity error */
 930 #define E1000_ICS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR
 931 /* packet buffer parity error */
 932 #define E1000_ICS_PB_PAR        E1000_ICR_PB_PAR
 933 /* Q1 Rx desc FIFO parity error */
 934 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
 935 /* Q1 Tx desc FIFO parity error */
 936 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
 937 #define E1000_ICS_DSW           E1000_ICR_DSW
 938 #define E1000_ICS_DOUTSYNC      E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
 939 #define E1000_ICS_PHYINT        E1000_ICR_PHYINT
 940 #define E1000_ICS_EPRST         E1000_ICR_EPRST
 941
 942 /* Transmit Descriptor Control */
 943 #define E1000_TXDCTL_PTHRESH    0x0000003F      /* TXDCTL Prefetch Threshold */
 944 #define E1000_TXDCTL_HTHRESH    0x00003F00      /* TXDCTL Host Threshold */
 945 #define E1000_TXDCTL_WTHRESH    0x003F0000      /* TXDCTL Writeback Threshold */
 946 #define E1000_TXDCTL_GRAN       0x01000000      /* TXDCTL Granularity */
 947 #define E1000_TXDCTL_LWTHRESH   0xFE000000      /* TXDCTL Low Threshold */
 948 #define E1000_TXDCTL_FULL_TX_DESC_WB    0x01010000      /* GRAN=1, WTHRESH=1 */
 949 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F    /* GRAN=1, PTHRESH=31 */
 950 /* Enable the counting of descriptors still to be processed. */
 951 #define E1000_TXDCTL_COUNT_DESC 0x00400000
 952
 953 /* Flow Control Constants */
 954 #define FLOW_CONTROL_ADDRESS_LOW        0x00C28001
 955 #define FLOW_CONTROL_ADDRESS_HIGH       0x00000100
 956 #define FLOW_CONTROL_TYPE               0x8808
 957
 958 /* 802.1q VLAN Packet Size */
 959 #define VLAN_TAG_SIZE                   4 /* 802.3ac tag (not DMA'd) */
 960 #define E1000_VLAN_FILTER_TBL_SIZE      128 /* VLAN Filter Table (4096 bits) */
 961
 962 /* Receive Address */
 963 /*
 964  * Number of high/low register pairs in the RAR. The RAR (Receive Address
 965  * Registers) holds the directed and multicast addresses that we monitor.
 966  * Technically, we have 16 spots.  However, we reserve one of these spots
 967  * (RAR[15]) for our directed address used by controllers with
 968  * manageability enabled, allowing us room for 15 multicast addresses.
 969  */
 970 #define E1000_RAR_ENTRIES       15
 971 #define E1000_RAH_AV            0x80000000      /* Receive descriptor valid */
 972 #define E1000_RAL_MAC_ADDR_LEN  4
 973 #define E1000_RAH_MAC_ADDR_LEN  2
 974 #define E1000_RAH_POOL_MASK     0x03FC0000
 975 #define E1000_RAH_POOL_1        0x00040000
 976
 977 /* Error Codes */
 978 #define E1000_SUCCESS           0
 979 #define E1000_ERR_NVM           1
 980 #define E1000_ERR_PHY           2
 981 #define E1000_ERR_CONFIG        3
 982 #define E1000_ERR_PARAM         4
 983 #define E1000_ERR_MAC_INIT      5
 984 #define E1000_ERR_PHY_TYPE      6
 985 #define E1000_ERR_RESET         9
 986 #define E1000_ERR_MASTER_REQUESTS_PENDING       10
 987 #define E1000_ERR_HOST_INTERFACE_COMMAND        11
 988 #define E1000_BLK_PHY_RESET     12
 989 #define E1000_ERR_SWFW_SYNC     13
 990 #define E1000_NOT_IMPLEMENTED   14
 991 #define E1000_ERR_MBX           15
 992
 993 /* Loop limit on how long we wait for auto-negotiation to complete */
 994 #define FIBER_LINK_UP_LIMIT     50
 995 #define COPPER_LINK_UP_LIMIT    10
 996 #define PHY_AUTO_NEG_LIMIT      45
 997 #define PHY_FORCE_LIMIT         20
 998 /* Number of 100 microseconds we wait for PCI Express master disable */
 999 #define MASTER_DISABLE_TIMEOUT  800
1000 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
1001 #define PHY_CFG_TIMEOUT         100
1002 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
1003 #define MDIO_OWNERSHIP_TIMEOUT  10
1004 /* Number of milliseconds for NVM auto read done after MAC reset. */
1005 #define AUTO_READ_DONE_TIMEOUT  10
1006
1007 /* Flow Control */
1008 #define E1000_FCRTH_RTH         0x0000FFF8 /* Mask Bits[15:3] for RTH */
1009 #define E1000_FCRTH_XFCE        0x80000000 /* External Flow Control Enable */
1010 #define E1000_FCRTL_RTL         0x0000FFF8 /* Mask Bits[15:3] for RTL */
1011 #define E1000_FCRTL_XONE        0x80000000 /* Enable XON frame transmission */
1012
1013 /* Transmit Configuration Word */
1014 #define E1000_TXCW_FD           0x00000020 /* TXCW full duplex */
1015 #define E1000_TXCW_HD           0x00000040 /* TXCW half duplex */
1016 #define E1000_TXCW_PAUSE        0x00000080 /* TXCW sym pause request */
1017 #define E1000_TXCW_ASM_DIR      0x00000100 /* TXCW astm pause direction */
1018 #define E1000_TXCW_PAUSE_MASK   0x00000180 /* TXCW pause request mask */
1019 #define E1000_TXCW_RF           0x00003000 /* TXCW remote fault */
1020 #define E1000_TXCW_NP           0x00008000 /* TXCW next page */
1021 #define E1000_TXCW_CW           0x0000ffff /* TxConfigWord mask */
1022 #define E1000_TXCW_TXC          0x40000000 /* Transmit Config control */
1023 #define E1000_TXCW_ANE          0x80000000 /* Auto-neg enable */
1024
1025 /* Receive Configuration Word */
1026 #define E1000_RXCW_CW           0x0000ffff /* RxConfigWord mask */
1027 #define E1000_RXCW_NC           0x04000000 /* Receive config no carrier */
1028 #define E1000_RXCW_IV           0x08000000 /* Receive config invalid */
1029 #define E1000_RXCW_CC           0x10000000 /* Receive config change */
1030 #define E1000_RXCW_C            0x20000000 /* Receive config */
1031 #define E1000_RXCW_SYNCH        0x40000000 /* Receive config synch */
1032 #define E1000_RXCW_ANC          0x80000000 /* Auto-neg complete */
1033
1034 /* PCI Express Control */
1035 #define E1000_GCR_RXD_NO_SNOOP          0x00000001
1036 #define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
1037 #define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
1038 #define E1000_GCR_TXD_NO_SNOOP          0x00000008
1039 #define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
1040 #define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
1041 #define E1000_GCR_CMPL_TMOUT_MASK       0x0000F000
1042 #define E1000_GCR_CMPL_TMOUT_10ms       0x00001000
1043 #define E1000_GCR_CMPL_TMOUT_RESEND     0x00010000
1044 #define E1000_GCR_CAP_VER2              0x00040000
1045
1046 #define PCIE_NO_SNOOP_ALL       (E1000_GCR_RXD_NO_SNOOP | \
1047                                 E1000_GCR_RXDSCW_NO_SNOOP | \
1048                                 E1000_GCR_RXDSCR_NO_SNOOP | \
1049                                 E1000_GCR_TXD_NO_SNOOP  | \
1050                                 E1000_GCR_TXDSCW_NO_SNOOP | \
1051                                 E1000_GCR_TXDSCR_NO_SNOOP)
1052
1053 /* PHY Control Register */
1054 #define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
1055 #define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
1056 #define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
1057 #define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
1058 #define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
1059 #define MII_CR_POWER_DOWN       0x0800  /* Power down */
1060 #define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
1061 #define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
1062 #define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
1063 #define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
1064 #define MII_CR_SPEED_1000       0x0040
1065 #define MII_CR_SPEED_100        0x2000
1066 #define MII_CR_SPEED_10         0x0000
1067
1068 /* PHY Status Register */
1069 #define MII_SR_EXTENDED_CAPS    0x0001  /* Extended register capabilities */
1070 #define MII_SR_JABBER_DETECT    0x0002  /* Jabber Detected */
1071 #define MII_SR_LINK_STATUS      0x0004  /* Link Status 1 = link */
1072 #define MII_SR_AUTONEG_CAPS     0x0008  /* Auto Neg Capable */
1073 #define MII_SR_REMOTE_FAULT     0x0010  /* Remote Fault Detect */
1074 #define MII_SR_AUTONEG_COMPLETE 0x0020  /* Auto Neg Complete */
1075 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
1076 #define MII_SR_EXTENDED_STATUS  0x0100  /* Ext. status info in Reg 0x0F */
1077 #define MII_SR_100T2_HD_CAPS    0x0200  /* 100T2 Half Duplex Capable */
1078 #define MII_SR_100T2_FD_CAPS    0x0400  /* 100T2 Full Duplex Capable */
1079 #define MII_SR_10T_HD_CAPS      0x0800  /* 10T   Half Duplex Capable */
1080 #define MII_SR_10T_FD_CAPS      0x1000  /* 10T   Full Duplex Capable */
1081 #define MII_SR_100X_HD_CAPS     0x2000  /* 100X  Half Duplex Capable */
1082 #define MII_SR_100X_FD_CAPS     0x4000  /* 100X  Full Duplex Capable */
1083 #define MII_SR_100T4_CAPS       0x8000  /* 100T4 Capable */
1084
1085 /* Autoneg Advertisement Register */
1086 #define NWAY_AR_SELECTOR_FIELD  0x0001  /* indicates IEEE 802.3 CSMA/CD */
1087 #define NWAY_AR_10T_HD_CAPS     0x0020  /* 10T   Half Duplex Capable */
1088 #define NWAY_AR_10T_FD_CAPS     0x0040  /* 10T   Full Duplex Capable */
1089 #define NWAY_AR_100TX_HD_CAPS   0x0080  /* 100TX Half Duplex Capable */
1090 #define NWAY_AR_100TX_FD_CAPS   0x0100  /* 100TX Full Duplex Capable */
1091 #define NWAY_AR_100T4_CAPS      0x0200  /* 100T4 Capable */
1092 #define NWAY_AR_PAUSE           0x0400  /* Pause operation desired */
1093 #define NWAY_AR_ASM_DIR         0x0800  /* Asymmetric Pause Direction bit */
1094 #define NWAY_AR_REMOTE_FAULT    0x2000  /* Remote Fault detected */
1095 #define NWAY_AR_NEXT_PAGE       0x8000  /* Next Page ability supported */
1096
1097 /* Link Partner Ability Register (Base Page) */
1098 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
1099 #define NWAY_LPAR_10T_HD_CAPS   0x0020  /* LP is 10T   Half Duplex Capable */
1100 #define NWAY_LPAR_10T_FD_CAPS   0x0040  /* LP is 10T   Full Duplex Capable */
1101 #define NWAY_LPAR_100TX_HD_CAPS 0x0080  /* LP is 100TX Half Duplex Capable */
1102 #define NWAY_LPAR_100TX_FD_CAPS 0x0100  /* LP is 100TX Full Duplex Capable */
1103 #define NWAY_LPAR_100T4_CAPS    0x0200  /* LP is 100T4 Capable */
1104 #define NWAY_LPAR_PAUSE         0x0400  /* LP Pause operation desired */
1105 #define NWAY_LPAR_ASM_DIR       0x0800  /* LP Asymmetric Pause Direction bit */
1106 #define NWAY_LPAR_REMOTE_FAULT  0x2000  /* LP has detected Remote Fault */
1107 #define NWAY_LPAR_ACKNOWLEDGE   0x4000  /* LP has rx'd link code word */
1108 #define NWAY_LPAR_NEXT_PAGE     0x8000  /* Next Page ability supported */
1109
1110 /* Autoneg Expansion Register */
1111 #define NWAY_ER_LP_NWAY_CAPS    0x0001  /* LP has Auto Neg Capability */
1112 #define NWAY_ER_PAGE_RXD        0x0002  /* LP is 10T   Half Duplex Capable */
1113 #define NWAY_ER_NEXT_PAGE_CAPS  0x0004  /* LP is 10T   Full Duplex Capable */
1114 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
1115 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
1116
1117 /* 1000BASE-T Control Register */
1118 #define CR_1000T_ASYM_PAUSE     0x0080  /* Advertise asymmetric pause bit */
1119 #define CR_1000T_HD_CAPS        0x0100  /* Advertise 1000T HD capability */
1120 #define CR_1000T_FD_CAPS        0x0200  /* Advertise 1000T FD capability  */
1121 #define CR_1000T_REPEATER_DTE   0x0400  /* 1=Repeater/switch device port */
1122                                         /* 0=DTE device */
1123 #define CR_1000T_MS_VALUE       0x0800  /* 1=Configure PHY as Master */
1124                                         /* 0=Configure PHY as Slave */
1125 #define CR_1000T_MS_ENABLE      0x1000  /* 1=Master/Slave manual config value */
1126                                         /* 0=Automatic Master/Slave config */
1127 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
1128 #define CR_1000T_TEST_MODE_1    0x2000  /* Transmit Waveform test */
1129 #define CR_1000T_TEST_MODE_2    0x4000  /* Master Transmit Jitter test */
1130 #define CR_1000T_TEST_MODE_3    0x6000  /* Slave Transmit Jitter test */
1131 #define CR_1000T_TEST_MODE_4    0x8000  /* Transmitter Distortion test */
1132
1133 /* 1000BASE-T Status Register */
1134 #define SR_1000T_IDLE_ERROR_CNT 0x00FF  /* Num idle errors since last read */
1135 #define SR_1000T_ASYM_PAUSE_DIR 0x0100  /* LP asymmetric pause direction bit */
1136 #define SR_1000T_LP_HD_CAPS     0x0400  /* LP is 1000T HD capable */
1137 #define SR_1000T_LP_FD_CAPS     0x0800  /* LP is 1000T FD capable */
1138 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1139 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1140 #define SR_1000T_MS_CONFIG_RES  0x4000  /* 1=Local Tx is Master, 0=Slave */
1141 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1142
1143 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT   5
1144
1145 /* PHY 1000 MII Register/Bit Definitions */
1146 /* PHY Registers defined by IEEE */
1147 #define PHY_CONTROL             0x00    /* Control Register */
1148 #define PHY_STATUS              0x01    /* Status Register */
1149 #define PHY_ID1                 0x02    /* Phy Id Reg (word 1) */
1150 #define PHY_ID2                 0x03    /* Phy Id Reg (word 2) */
1151 #define PHY_AUTONEG_ADV         0x04    /* Autoneg Advertisement */
1152 #define PHY_LP_ABILITY          0x05    /* Link Partner Ability (Base Page) */
1153 #define PHY_AUTONEG_EXP         0x06    /* Autoneg Expansion Reg */
1154 #define PHY_NEXT_PAGE_TX        0x07    /* Next Page Tx */
1155 #define PHY_LP_NEXT_PAGE        0x08    /* Link Partner Next Page */
1156 #define PHY_1000T_CTRL          0x09    /* 1000Base-T Control Reg */
1157 #define PHY_1000T_STATUS        0x0A    /* 1000Base-T Status Reg */
1158 #define PHY_EXT_STATUS          0x0F    /* Extended Status Reg */
1159
1160 #define PHY_CONTROL_LB          0x4000  /* PHY Loopback bit */
1161
1162 /* NVM Control */
1163 #define E1000_EECD_SK           0x00000001 /* NVM Clock */
1164 #define E1000_EECD_CS           0x00000002 /* NVM Chip Select */
1165 #define E1000_EECD_DI           0x00000004 /* NVM Data In */
1166 #define E1000_EECD_DO           0x00000008 /* NVM Data Out */
1167 #define E1000_EECD_FWE_MASK     0x00000030
1168 #define E1000_EECD_FWE_DIS      0x00000010 /* Disable FLASH writes */
1169 #define E1000_EECD_FWE_EN       0x00000020 /* Enable FLASH writes */
1170 #define E1000_EECD_FWE_SHIFT    4
1171 #define E1000_EECD_REQ          0x00000040 /* NVM Access Request */
1172 #define E1000_EECD_GNT          0x00000080 /* NVM Access Grant */
1173 #define E1000_EECD_PRES         0x00000100 /* NVM Present */
1174 #define E1000_EECD_SIZE         0x00000200 /* NVM Size (0=64 word 1=256 word) */
1175 /* NVM Addressing bits based on type 0=small, 1=large */
1176 #define E1000_EECD_ADDR_BITS    0x00000400
1177 #define E1000_EECD_TYPE         0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1178 #ifndef E1000_NVM_GRANT_ATTEMPTS
1179 #define E1000_NVM_GRANT_ATTEMPTS        1000 /* NVM # attempts to gain grant */
1180 #endif
1181 #define E1000_EECD_AUTO_RD      0x00000200 /* NVM Auto Read done */
1182 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1183 #define E1000_EECD_SIZE_EX_SHIFT        11
1184 #define E1000_EECD_NVADDS       0x00018000 /* NVM Address Size */
1185 #define E1000_EECD_SELSHAD      0x00020000 /* Select Shadow RAM */
1186 #define E1000_EECD_INITSRAM     0x00040000 /* Initialize Shadow RAM */
1187 #define E1000_EECD_FLUPD        0x00080000 /* Update FLASH */
1188 #define E1000_EECD_AUPDEN       0x00100000 /* Enable Autonomous FLASH update */
1189 #define E1000_EECD_SHADV        0x00200000 /* Shadow RAM Data Valid */
1190 #define E1000_EECD_SEC1VAL      0x00400000 /* Sector One Valid */
1191 #define E1000_EECD_SECVAL_SHIFT         22
1192 #define E1000_EECD_SEC1VAL_VALID_MASK   (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
1193
1194 #define E1000_NVM_SWDPIN0       0x0001  /* SWDPIN 0 NVM Value */
1195 #define E1000_NVM_LED_LOGIC     0x0020  /* Led Logic Word */
1196 /* Offset to data in NVM read/write regs */
1197 #define E1000_NVM_RW_REG_DATA   16
1198 #define E1000_NVM_RW_REG_DONE   2 /* Offset to READ/WRITE done bit */
1199 #define E1000_NVM_RW_REG_START  1 /* Start operation */
1200 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1201 #define E1000_NVM_POLL_WRITE    1 /* Flag for polling for write complete */
1202 #define E1000_NVM_POLL_READ     0 /* Flag for polling for read complete */
1203 #define E1000_FLASH_UPDATES     2000
1204
1205 /* NVM Word Offsets */
1206 #define NVM_COMPAT                      0x0003
1207 #define NVM_ID_LED_SETTINGS             0x0004
1208 #define NVM_VERSION                     0x0005
1209 /* SERDES output amplitude */
1210 #define NVM_SERDES_AMPLITUDE            0x0006
1211 #define NVM_PHY_CLASS_WORD              0x0007
1212 #define NVM_INIT_CONTROL1_REG           0x000A
1213 #define NVM_INIT_CONTROL2_REG           0x000F
1214 #define NVM_SWDEF_PINS_CTRL_PORT_1      0x0010
1215 #define NVM_INIT_CONTROL3_PORT_B        0x0014
1216 #define NVM_INIT_3GIO_3                 0x001A
1217 #define NVM_SWDEF_PINS_CTRL_PORT_0      0x0020
1218 #define NVM_INIT_CONTROL3_PORT_A        0x0024
1219 #define NVM_CFG                         0x0012
1220 #define NVM_FLASH_VERSION               0x0032
1221 #define NVM_ALT_MAC_ADDR_PTR            0x0037
1222 #define NVM_CHECKSUM_REG                0x003F
1223
1224 /* MNG config cycle done */
1225 #define E1000_NVM_CFG_DONE_PORT_0       0x040000
1226 /* ...for second port */
1227 #define E1000_NVM_CFG_DONE_PORT_1       0x080000
1228
1229 /* Mask bits for fields in Word 0x0f of the NVM */
1230 #define NVM_WORD0F_PAUSE_MASK           0x3000
1231 #define NVM_WORD0F_PAUSE                0x1000
1232 #define NVM_WORD0F_ASM_DIR              0x2000
1233 #define NVM_WORD0F_ANE                  0x0800
1234 #define NVM_WORD0F_SWPDIO_EXT_MASK      0x00F0
1235 #define NVM_WORD0F_LPLU                 0x0001
1236
1237 /* Mask bits for fields in Word 0x1a of the NVM */
1238 #define NVM_WORD1A_ASPM_MASK    0x000C
1239
1240 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
1241 #define NVM_SUM                 0xBABA
1242
1243 #define NVM_MAC_ADDR_OFFSET             0
1244 #define NVM_PBA_OFFSET_0                8
1245 #define NVM_PBA_OFFSET_1                9
1246 #define NVM_RESERVED_WORD               0xFFFF
1247 #define NVM_PHY_CLASS_A                 0x8000
1248 #define NVM_SERDES_AMPLITUDE_MASK       0x000F
1249 #define NVM_SIZE_MASK                   0x1C00
1250 #define NVM_SIZE_SHIFT                  10
1251 #define NVM_WORD_SIZE_BASE_SHIFT        6
1252 #define NVM_SWDPIO_EXT_SHIFT            4
1253
1254 /* NVM Commands - Microwire */
1255 #define NVM_READ_OPCODE_MICROWIRE       0x6     /* NVM read opcode */
1256 #define NVM_WRITE_OPCODE_MICROWIRE      0x5     /* NVM write opcode */
1257 #define NVM_ERASE_OPCODE_MICROWIRE      0x7     /* NVM erase opcode */
1258 #define NVM_EWEN_OPCODE_MICROWIRE       0x13    /* NVM erase/write enable */
1259 #define NVM_EWDS_OPCODE_MICROWIRE       0x10    /* NVM erase/write disable */
1260
1261 /* NVM Commands - SPI */
1262 #define NVM_MAX_RETRY_SPI       5000    /* Max wait of 5ms, for RDY signal */
1263 #define NVM_READ_OPCODE_SPI     0x03    /* NVM read opcode */
1264 #define NVM_WRITE_OPCODE_SPI    0x02    /* NVM write opcode */
1265 #define NVM_A8_OPCODE_SPI       0x08    /* opcode bit-3 = address bit-8 */
1266 #define NVM_WREN_OPCODE_SPI     0x06    /* NVM set Write Enable latch */
1267 #define NVM_WRDI_OPCODE_SPI     0x04    /* NVM reset Write Enable latch */
1268 #define NVM_RDSR_OPCODE_SPI     0x05    /* NVM read Status register */
1269 #define NVM_WRSR_OPCODE_SPI     0x01    /* NVM write Status register */
1270
1271 /* SPI NVM Status Register */
1272 #define NVM_STATUS_RDY_SPI      0x01
1273 #define NVM_STATUS_WEN_SPI      0x02
1274 #define NVM_STATUS_BP0_SPI      0x04
1275 #define NVM_STATUS_BP1_SPI      0x08
1276 #define NVM_STATUS_WPEN_SPI     0x80
1277
1278 /* Word definitions for ID LED Settings */
1279 #define ID_LED_RESERVED_0000    0x0000
1280 #define ID_LED_RESERVED_FFFF    0xFFFF
1281 #define ID_LED_DEFAULT          ((ID_LED_OFF1_ON2 << 12) | \
1282                                 (ID_LED_OFF1_OFF2 <<  8) | \
1283                                 (ID_LED_DEF1_DEF2 <<  4) | \
1284                                 (ID_LED_DEF1_DEF2))
1285 #define ID_LED_DEF1_DEF2        0x1
1286 #define ID_LED_DEF1_ON2         0x2
1287 #define ID_LED_DEF1_OFF2        0x3
1288 #define ID_LED_ON1_DEF2         0x4
1289 #define ID_LED_ON1_ON2          0x5
1290 #define ID_LED_ON1_OFF2         0x6
1291 #define ID_LED_OFF1_DEF2        0x7
1292 #define ID_LED_OFF1_ON2         0x8
1293 #define ID_LED_OFF1_OFF2        0x9
1294
1295 #define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
1296 #define IGP_ACTIVITY_LED_ENABLE 0x0300
1297 #define IGP_LED3_MODE           0x07000000
1298
1299 /* PCI/PCI-X/PCI-EX Config space */
1300 #define PCIX_COMMAND_REGISTER           0xE6
1301 #define PCIX_STATUS_REGISTER_LO         0xE8
1302 #define PCIX_STATUS_REGISTER_HI         0xEA
1303 #define PCI_HEADER_TYPE_REGISTER        0x0E
1304 #define PCIE_LINK_STATUS                0x12
1305 #define PCIE_DEVICE_CONTROL2            0x28
1306
1307 #define PCIX_COMMAND_MMRBC_MASK         0x000C
1308 #define PCIX_COMMAND_MMRBC_SHIFT        0x2
1309 #define PCIX_STATUS_HI_MMRBC_MASK       0x0060
1310 #define PCIX_STATUS_HI_MMRBC_SHIFT      0x5
1311 #define PCIX_STATUS_HI_MMRBC_4K         0x3
1312 #define PCIX_STATUS_HI_MMRBC_2K         0x2
1313 #define PCIX_STATUS_LO_FUNC_MASK        0x7
1314 #define PCI_HEADER_TYPE_MULTIFUNC       0x80
1315 #define PCIE_LINK_WIDTH_MASK            0x3F0
1316 #define PCIE_LINK_WIDTH_SHIFT           4
1317 #define PCIE_DEVICE_CONTROL2_16ms       0x0005
1318
1319 #ifndef ETH_ADDR_LEN
1320 #define ETH_ADDR_LEN            6
1321 #endif
1322
1323 #define PHY_REVISION_MASK       0xFFFFFFF0
1324 #define MAX_PHY_REG_ADDRESS     0x1F    /* 5 bit address bus (0-0x1F) */
1325 #define MAX_PHY_MULTI_PAGE_REG  0xF
1326
1327 /* Bit definitions for valid PHY IDs. */
1328 /*
1329  * I = Integrated
1330  * E = External
1331  */
1332 #define M88E1000_E_PHY_ID       0x01410C50
1333 #define M88E1000_I_PHY_ID       0x01410C30
1334 #define M88E1011_I_PHY_ID       0x01410C20
1335 #define IGP01E1000_I_PHY_ID     0x02A80380
1336 #define M88E1011_I_REV_4        0x04
1337 #define M88E1111_I_PHY_ID       0x01410CC0
1338 #define GG82563_E_PHY_ID        0x01410CA0
1339 #define IGP03E1000_E_PHY_ID     0x02A80390
1340 #define IFE_E_PHY_ID            0x02A80330
1341 #define IFE_PLUS_E_PHY_ID       0x02A80320
1342 #define IFE_C_E_PHY_ID          0x02A80310
1343 #define BME1000_E_PHY_ID        0x01410CB0
1344 #define BME1000_E_PHY_ID_R2     0x01410CB1
1345 #define I82577_E_PHY_ID         0x01540050
1346 #define I82578_E_PHY_ID         0x004DD040
1347 #define I82579_E_PHY_ID         0x01540090
1348 #define M88_VENDOR              0x0141
1349
1350 /* M88E1000 Specific Registers */
1351 #define M88E1000_PHY_SPEC_CTRL  0x10    /* PHY Specific Control Register */
1352 #define M88E1000_PHY_SPEC_STATUS 0x11   /* PHY Specific Status Register */
1353 #define M88E1000_INT_ENABLE     0x12    /* Interrupt Enable Register */
1354 #define M88E1000_INT_STATUS     0x13    /* Interrupt Status Register */
1355 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1356 #define M88E1000_RX_ERR_CNTR    0x15    /* Receive Error Counter */
1357
1358 #define M88E1000_PHY_EXT_CTRL   0x1A    /* PHY extend control register */
1359 #define M88E1000_PHY_PAGE_SELECT 0x1D   /* Reg 29 for page number setting */
1360 #define M88E1000_PHY_GEN_CONTROL 0x1E   /* Its meaning depends on reg 29 */
1361 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1362 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1363
1364 /* M88E1000 PHY Specific Control Register */
1365 #define M88E1000_PSCR_JABBER_DISABLE    0x0001 /* 1=Jabber Function disabled */
1366 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
1367 #define M88E1000_PSCR_SQE_TEST          0x0004 /* 1=SQE Test enabled */
1368 /* 1=CLK125 low, 0=CLK125 toggling */
1369 #define M88E1000_PSCR_CLK125_DISABLE    0x0010
1370 #define M88E1000_PSCR_MDI_MANUAL_MODE   0x0000 /* MDI Crossover Mode bits 6:5 */
1371                                                 /* Manual MDI configuration */
1372 #define M88E1000_PSCR_MDIX_MANUAL_MODE  0x0020 /* Manual MDIX configuration */
1373 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1374 #define M88E1000_PSCR_AUTO_X_1000T      0x0040
1375 /* Auto crossover enabled all speeds */
1376 #define M88E1000_PSCR_AUTO_X_MODE       0x0060
1377 /*
1378  * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
1379  * 0=Normal 10BASE-T Rx Threshold
1380  */
1381 #define M88E1000_PSCR_EN_10BT_EXT_DIST  0x0080
1382 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
1383 #define M88E1000_PSCR_MII_5BIT_ENABLE   0x0100
1384 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200  /* 1=Scrambler disable */
1385 #define M88E1000_PSCR_FORCE_LINK_GOOD   0x0400  /* 1=Force link good */
1386 #define M88E1000_PSCR_ASSERT_CRS_ON_TX  0x0800  /* 1=Assert CRS on Tx */
1387
1388 /* M88E1000 PHY Specific Status Register */
1389 #define M88E1000_PSSR_JABBER            0x0001  /* 1=Jabber */
1390 #define M88E1000_PSSR_REV_POLARITY      0x0002  /* 1=Polarity reversed */
1391 #define M88E1000_PSSR_DOWNSHIFT         0x0020  /* 1=Downshifted */
1392 #define M88E1000_PSSR_MDIX              0x0040  /* 1=MDIX; 0=MDI */
1393 /*
1394  * 0 = <50M
1395  * 1 = 50-80M
1396  * 2 = 80-110M
1397  * 3 = 110-140M
1398  * 4 = >140M
1399  */
1400 #define M88E1000_PSSR_CABLE_LENGTH      0x0380
1401 #define M88E1000_PSSR_LINK              0x0400  /* 1=Link up, 0=Link down */
1402 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800  /* 1=Speed & Duplex resolved */
1403 #define M88E1000_PSSR_PAGE_RCVD         0x1000  /* 1=Page received */
1404 #define M88E1000_PSSR_DPLX              0x2000  /* 1=Duplex 0=Half Duplex */
1405 #define M88E1000_PSSR_SPEED             0xC000  /* Speed, bits 14:15 */
1406 #define M88E1000_PSSR_10MBS             0x0000  /* 00=10Mbs */
1407 #define M88E1000_PSSR_100MBS            0x4000  /* 01=100Mbs */
1408 #define M88E1000_PSSR_1000MBS           0x8000  /* 10=1000Mbs */
1409
1410 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1411
1412 /* M88E1000 Extended PHY Specific Control Register */
1413 #define M88E1000_EPSCR_FIBER_LOOPBACK   0x4000  /* 1=Fiber loopback */
1414 /*
1415  * 1 = Lost lock detect enabled.
1416  * Will assert lost lock and bring
1417  * link down if idle not seen
1418  * within 1ms in 1000BASE-T
1419  */
1420 #define M88E1000_EPSCR_DOWN_NO_IDLE     0x8000
1421 /*
1422  * Number of times we will attempt to autonegotiate before downshifting if we
1423  * are the master
1424  */
1425 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK    0x0C00
1426 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X      0x0000
1427 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X      0x0400
1428 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X      0x0800
1429 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X      0x0C00
1430 /*
1431  * Number of times we will attempt to autonegotiate before downshifting if we
1432  * are the slave
1433  */
1434 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK     0x0300
1435 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS      0x0000
1436 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X       0x0100
1437 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X       0x0200
1438 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X       0x0300
1439 #define M88E1000_EPSCR_TX_CLK_2_5       0x0060  /* 2.5 MHz TX_CLK */
1440 #define M88E1000_EPSCR_TX_CLK_25        0x0070  /* 25  MHz TX_CLK */
1441 #define M88E1000_EPSCR_TX_CLK_0         0x0000  /* NO  TX_CLK */
1442
1443 /* M88EC018 Rev 2 specific DownShift settings */
1444 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK   0x0E00
1445 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X     0x0000
1446 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X     0x0200
1447 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X     0x0400
1448 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X     0x0600
1449 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X     0x0800
1450 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X     0x0A00
1451 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X     0x0C00
1452 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X     0x0E00
1453
1454 #define I82578_EPSCR_DOWNSHIFT_ENABLE           0x0020
1455 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK     0x001C
1456
1457 /* BME1000 PHY Specific Control Register */
1458 #define BME1000_PSCR_ENABLE_DOWNSHIFT   0x0800  /* 1 = enable downshift */
1459
1460 /*
1461  * Bits...
1462  * 15-5: page
1463  * 4-0: register offset
1464  */
1465 #define GG82563_PAGE_SHIFT      5
1466 #define GG82563_REG(page, reg)  \
1467         (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1468 #define GG82563_MIN_ALT_REG     30
1469
1470 /* GG82563 Specific Registers */
1471 #define GG82563_PHY_SPEC_CTRL           \
1472         GG82563_REG(0, 16)      /* PHY Specific Control */
1473 #define GG82563_PHY_SPEC_STATUS         \
1474         GG82563_REG(0, 17)      /* PHY Specific Status */
1475 #define GG82563_PHY_INT_ENABLE          \
1476         GG82563_REG(0, 18)      /* Interrupt Enable */
1477 #define GG82563_PHY_SPEC_STATUS_2       \
1478         GG82563_REG(0, 19)      /* PHY Specific Status 2 */
1479 #define GG82563_PHY_RX_ERR_CNTR         \
1480         GG82563_REG(0, 21)      /* Receive Error Counter */
1481 #define GG82563_PHY_PAGE_SELECT         \
1482         GG82563_REG(0, 22)      /* Page Select */
1483 #define GG82563_PHY_SPEC_CTRL_2         \
1484         GG82563_REG(0, 26)      /* PHY Specific Control 2 */
1485 #define GG82563_PHY_PAGE_SELECT_ALT     \
1486         GG82563_REG(0, 29)      /* Alternate Page Select */
1487 #define GG82563_PHY_TEST_CLK_CTRL       \
1488         GG82563_REG(0, 30)      /* Test Clock Control (use reg. 29 to select) */
1489
1490 #define GG82563_PHY_MAC_SPEC_CTRL       \
1491         GG82563_REG(2, 21)      /* MAC Specific Control Register */
1492 #define GG82563_PHY_MAC_SPEC_CTRL_2     \
1493         GG82563_REG(2, 26)      /* MAC Specific Control 2 */
1494
1495 #define GG82563_PHY_DSP_DISTANCE        \
1496         GG82563_REG(5, 26)      /* DSP Distance */
1497
1498 /* Page 193 - Port Control Registers */
1499 #define GG82563_PHY_KMRN_MODE_CTRL      \
1500         GG82563_REG(193, 16)    /* Kumeran Mode Control */
1501 #define GG82563_PHY_PORT_RESET          \
1502         GG82563_REG(193, 17)    /* Port Reset */
1503 #define GG82563_PHY_REVISION_ID         \
1504         GG82563_REG(193, 18)    /* Revision ID */
1505 #define GG82563_PHY_DEVICE_ID           \
1506         GG82563_REG(193, 19)    /* Device ID */
1507 #define GG82563_PHY_PWR_MGMT_CTRL       \
1508         GG82563_REG(193, 20)    /* Power Management Control */
1509 #define GG82563_PHY_RATE_ADAPT_CTRL     \
1510         GG82563_REG(193, 25)    /* Rate Adaptation Control */
1511
1512 /* Page 194 - KMRN Registers */
1513 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
1514         GG82563_REG(194, 16)    /* FIFO's Control/Status */
1515 #define GG82563_PHY_KMRN_CTRL           \
1516         GG82563_REG(194, 17)    /* Control */
1517 #define GG82563_PHY_INBAND_CTRL         \
1518         GG82563_REG(194, 18)    /* Inband Control */
1519 #define GG82563_PHY_KMRN_DIAGNOSTIC     \
1520         GG82563_REG(194, 19)    /* Diagnostic */
1521 #define GG82563_PHY_ACK_TIMEOUTS        \
1522         GG82563_REG(194, 20)    /* Acknowledge Timeouts */
1523 #define GG82563_PHY_ADV_ABILITY         \
1524         GG82563_REG(194, 21)    /* Advertised Ability */
1525 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
1526         GG82563_REG(194, 23)    /* Link Partner Advertised Ability */
1527 #define GG82563_PHY_ADV_NEXT_PAGE       \
1528         GG82563_REG(194, 24)    /* Advertised Next Page */
1529 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
1530         GG82563_REG(194, 25)    /* Link Partner Advertised Next page */
1531 #define GG82563_PHY_KMRN_MISC           \
1532         GG82563_REG(194, 26)    /* Misc. */
1533
1534 /* MDI Control */
1535 #define E1000_MDIC_DATA_MASK    0x0000FFFF
1536 #define E1000_MDIC_REG_MASK     0x001F0000
1537 #define E1000_MDIC_REG_SHIFT    16
1538 #define E1000_MDIC_PHY_MASK     0x03E00000
1539 #define E1000_MDIC_PHY_SHIFT    21
1540 #define E1000_MDIC_OP_WRITE     0x04000000
1541 #define E1000_MDIC_OP_READ      0x08000000
1542 #define E1000_MDIC_READY        0x10000000
1543 #define E1000_MDIC_INT_EN       0x20000000
1544 #define E1000_MDIC_ERROR        0x40000000
1545
1546 /* SerDes Control */
1547 #define E1000_GEN_CTL_READY     0x80000000
1548 #define E1000_GEN_CTL_ADDRESS_SHIFT     8
1549 #define E1000_GEN_POLL_TIMEOUT          640
1550
1551 #endif  /* _E1000_DEFINES_H_ */