usr/src/uts/common/io/e1000g/e1000_82540.c

   1 /*
   2  * This file is provided under a CDDLv1 license.  When using or
   3  * redistributing this file, you may do so under this license.
   4  * In redistributing this file this license must be included
   5  * and no other modification of this header file is permitted.
   6  *
   7  * CDDL LICENSE SUMMARY
   8  *
   9  * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
  10  *
  11  * The contents of this file are subject to the terms of Version
  12  * 1.0 of the Common Development and Distribution License (the "License").
  13  *
  14  * You should have received a copy of the License with this software.
  15  * You can obtain a copy of the License at
  16  *      http://www.opensolaris.org/os/licensing.
  17  * See the License for the specific language governing permissions
  18  * and limitations under the License.
  19  */
  20
  21 /*
  22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms of the CDDLv1.
  24  */
  25
  26 /*
  27  * IntelVersion: 1.57 v3-1-10-1_2009-9-18_Release14-6
  28  */
  29
  30 /*
  31  * 82540EM Gigabit Ethernet Controller
  32  * 82540EP Gigabit Ethernet Controller
  33  * 82545EM Gigabit Ethernet Controller (Copper)
  34  * 82545EM Gigabit Ethernet Controller (Fiber)
  35  * 82545GM Gigabit Ethernet Controller
  36  * 82546EB Gigabit Ethernet Controller (Copper)
  37  * 82546EB Gigabit Ethernet Controller (Fiber)
  38  * 82546GB Gigabit Ethernet Controller
  39  */
  40
  41 #include "e1000_api.h"
  42
  43 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw);
  44 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw);
  45 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw);
  46 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
  47 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
  48 static s32 e1000_init_hw_82540(struct e1000_hw *hw);
  49 static s32 e1000_reset_hw_82540(struct e1000_hw *hw);
  50 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw);
  51 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw);
  52 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw);
  53 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
  54 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
  55 static s32 e1000_read_mac_addr_82540(struct e1000_hw *hw);
  56
  57 /*
  58  * e1000_init_phy_params_82540 - Init PHY func ptrs.
  59  * @hw: pointer to the HW structure
  60  */
  61 static s32
  62 e1000_init_phy_params_82540(struct e1000_hw *hw)
  63 {
  64         struct e1000_phy_info *phy = &hw->phy;
  65         s32 ret_val = E1000_SUCCESS;
  66
  67         phy->addr = 1;
  68         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  69         phy->reset_delay_us = 10000;
  70         phy->type = e1000_phy_m88;
  71
  72         /* Function Pointers */
  73         phy->ops.check_polarity = e1000_check_polarity_m88;
  74         phy->ops.commit = e1000_phy_sw_reset_generic;
  75         phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
  76         phy->ops.get_cable_length = e1000_get_cable_length_m88;
  77         phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
  78         phy->ops.read_reg = e1000_read_phy_reg_m88;
  79         phy->ops.reset = e1000_phy_hw_reset_generic;
  80         phy->ops.write_reg = e1000_write_phy_reg_m88;
  81         phy->ops.get_info = e1000_get_phy_info_m88;
  82         phy->ops.power_up = e1000_power_up_phy_copper;
  83         phy->ops.power_down = e1000_power_down_phy_copper_82540;
  84
  85         ret_val = e1000_get_phy_id(hw);
  86         if (ret_val)
  87                 goto out;
  88
  89         /* Verify phy id */
  90         switch (hw->mac.type) {
  91         case e1000_82540:
  92         case e1000_82545:
  93         case e1000_82545_rev_3:
  94         case e1000_82546:
  95         case e1000_82546_rev_3:
  96                 if (phy->id == M88E1011_I_PHY_ID)
  97                         break;
  98                 /* Fall Through */
  99         default:
 100                 ret_val = -E1000_ERR_PHY;
 101                 goto out;
 102         }
 103
 104 out:
 105         return (ret_val);
 106 }
 107
 108 /*
 109  * e1000_init_nvm_params_82540 - Init NVM func ptrs.
 110  * @hw: pointer to the HW structure
 111  */
 112 static s32
 113 e1000_init_nvm_params_82540(struct e1000_hw *hw)
 114 {
 115         struct e1000_nvm_info *nvm = &hw->nvm;
 116         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 117
 118         DEBUGFUNC("e1000_init_nvm_params_82540");
 119
 120         nvm->type = e1000_nvm_eeprom_microwire;
 121         nvm->delay_usec = 50;
 122         nvm->opcode_bits = 3;
 123         switch (nvm->override) {
 124         case e1000_nvm_override_microwire_large:
 125                 nvm->address_bits = 8;
 126                 nvm->word_size = 256;
 127                 break;
 128         case e1000_nvm_override_microwire_small:
 129                 nvm->address_bits = 6;
 130                 nvm->word_size = 64;
 131                 break;
 132         default:
 133                 nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
 134                 nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
 135                 break;
 136         }
 137
 138         /* Function Pointers */
 139         nvm->ops.acquire = e1000_acquire_nvm_generic;
 140         nvm->ops.read = e1000_read_nvm_microwire;
 141         nvm->ops.release = e1000_release_nvm_generic;
 142         nvm->ops.update = e1000_update_nvm_checksum_generic;
 143         nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 144         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 145         nvm->ops.write = e1000_write_nvm_microwire;
 146
 147         return (E1000_SUCCESS);
 148 }
 149
 150 /*
 151  * e1000_init_mac_params_82540 - Init MAC func ptrs.
 152  * @hw: pointer to the HW structure
 153  */
 154 static s32
 155 e1000_init_mac_params_82540(struct e1000_hw *hw)
 156 {
 157         struct e1000_mac_info *mac = &hw->mac;
 158         s32 ret_val = E1000_SUCCESS;
 159
 160         DEBUGFUNC("e1000_init_mac_params_82540");
 161
 162         /* Set media type */
 163         switch (hw->device_id) {
 164         case E1000_DEV_ID_82545EM_FIBER:
 165         case E1000_DEV_ID_82545GM_FIBER:
 166         case E1000_DEV_ID_82546EB_FIBER:
 167         case E1000_DEV_ID_82546GB_FIBER:
 168                 hw->phy.media_type = e1000_media_type_fiber;
 169                 break;
 170         case E1000_DEV_ID_82545GM_SERDES:
 171         case E1000_DEV_ID_82546GB_SERDES:
 172                 hw->phy.media_type = e1000_media_type_internal_serdes;
 173                 break;
 174         default:
 175                 hw->phy.media_type = e1000_media_type_copper;
 176                 break;
 177         }
 178
 179         /* Set mta register count */
 180         mac->mta_reg_count = 128;
 181         /* Set rar entry count */
 182         mac->rar_entry_count = E1000_RAR_ENTRIES;
 183
 184         /* Function pointers */
 185
 186         /* bus type/speed/width */
 187         mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
 188         /* function id */
 189         mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
 190         /* reset */
 191         mac->ops.reset_hw = e1000_reset_hw_82540;
 192         /* hw initialization */
 193         mac->ops.init_hw = e1000_init_hw_82540;
 194         /* link setup */
 195         mac->ops.setup_link = e1000_setup_link_generic;
 196         /* physical interface setup */
 197         mac->ops.setup_physical_interface =
 198             (hw->phy.media_type == e1000_media_type_copper)
 199             ? e1000_setup_copper_link_82540
 200             : e1000_setup_fiber_serdes_link_82540;
 201         /* check for link */
 202         switch (hw->phy.media_type) {
 203         case e1000_media_type_copper:
 204                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 205                 break;
 206         case e1000_media_type_fiber:
 207                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 208                 break;
 209         case e1000_media_type_internal_serdes:
 210                 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
 211                 break;
 212         default:
 213                 ret_val = -E1000_ERR_CONFIG;
 214                 goto out;
 215         }
 216         /* link info */
 217         mac->ops.get_link_up_info =
 218             (hw->phy.media_type == e1000_media_type_copper)
 219             ? e1000_get_speed_and_duplex_copper_generic
 220             : e1000_get_speed_and_duplex_fiber_serdes_generic;
 221         /* multicast address update */
 222         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 223         /* writing VFTA */
 224         mac->ops.write_vfta = e1000_write_vfta_generic;
 225         /* clearing VFTA */
 226         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 227         /* setting MTA */
 228         mac->ops.mta_set = e1000_mta_set_generic;
 229         /* ID LED init */
 230         mac->ops.id_led_init = e1000_id_led_init_generic;
 231         /* setup LED */
 232         mac->ops.setup_led = e1000_setup_led_generic;
 233         /* read mac address */
 234         mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
 235         /* cleanup LED */
 236         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 237         /* turn on/off LED */
 238         mac->ops.led_on = e1000_led_on_generic;
 239         mac->ops.led_off = e1000_led_off_generic;
 240         /* clear hardware counters */
 241         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
 242
 243 out:
 244         return (ret_val);
 245 }
 246
 247 /*
 248  * e1000_init_function_pointers_82540 - Init func ptrs.
 249  * @hw: pointer to the HW structure
 250  *
 251  * Called to initialize all function pointers and parameters.
 252  */
 253 void
 254 e1000_init_function_pointers_82540(struct e1000_hw *hw)
 255 {
 256         DEBUGFUNC("e1000_init_function_pointers_82540");
 257
 258         hw->mac.ops.init_params = e1000_init_mac_params_82540;
 259         hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
 260         hw->phy.ops.init_params = e1000_init_phy_params_82540;
 261 }
 262
 263 /*
 264  * e1000_reset_hw_82540 - Reset hardware
 265  * @hw: pointer to the HW structure
 266  *
 267  * This resets the hardware into a known state.
 268  */
 269 static s32
 270 e1000_reset_hw_82540(struct e1000_hw *hw)
 271 {
 272         u32 ctrl, manc;
 273         s32 ret_val = E1000_SUCCESS;
 274
 275         DEBUGFUNC("e1000_reset_hw_82540");
 276
 277         DEBUGOUT("Masking off all interrupts\n");
 278         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 279
 280         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 281         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 282         E1000_WRITE_FLUSH(hw);
 283
 284         /*
 285          * Delay to allow any outstanding PCI transactions to complete
 286          * before resetting the device.
 287          */
 288         msec_delay(10);
 289
 290         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 291
 292         DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
 293         switch (hw->mac.type) {
 294         case e1000_82545_rev_3:
 295         case e1000_82546_rev_3:
 296                 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
 297                 break;
 298         default:
 299                 /*
 300                  * These controllers can't ack the 64-bit write when
 301                  * issuing the reset, so we use IO-mapping as a
 302                  * workaround to issue the reset.
 303                  */
 304                 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 305                 break;
 306         }
 307
 308         /* Wait for EEPROM reload */
 309         msec_delay(5);
 310
 311         /* Disable HW ARPs on ASF enabled adapters */
 312         manc = E1000_READ_REG(hw, E1000_MANC);
 313         manc &= ~E1000_MANC_ARP_EN;
 314         E1000_WRITE_REG(hw, E1000_MANC, manc);
 315
 316         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 317         (void) E1000_READ_REG(hw, E1000_ICR);
 318
 319         return (ret_val);
 320 }
 321
 322 /*
 323  * e1000_init_hw_82540 - Initialize hardware
 324  * @hw: pointer to the HW structure
 325  *
 326  * This inits the hardware readying it for operation.
 327  */
 328 static s32
 329 e1000_init_hw_82540(struct e1000_hw *hw)
 330 {
 331         struct e1000_mac_info *mac = &hw->mac;
 332         u32 txdctl, ctrl_ext;
 333         s32 ret_val = E1000_SUCCESS;
 334         u16 i;
 335
 336         DEBUGFUNC("e1000_init_hw_82540");
 337
 338         /* Initialize identification LED */
 339         ret_val = mac->ops.id_led_init(hw);
 340         if (ret_val) {
 341                 /* EMPTY */
 342                 DEBUGOUT("Error initializing identification LED\n");
 343                 /* This is not fatal and we should not stop init due to this */
 344         }
 345
 346         /* Disabling VLAN filtering */
 347         DEBUGOUT("Initializing the IEEE VLAN\n");
 348         if (mac->type < e1000_82545_rev_3)
 349                 E1000_WRITE_REG(hw, E1000_VET, 0);
 350
 351         mac->ops.clear_vfta(hw);
 352
 353         /* Setup the receive address. */
 354         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 355
 356         /* Zero out the Multicast HASH table */
 357         DEBUGOUT("Zeroing the MTA\n");
 358         for (i = 0; i < mac->mta_reg_count; i++) {
 359                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 360                 /*
 361                  * Avoid back to back register writes by adding the register
 362                  * read (flush).  This is to protect against some strange
 363                  * bridge configurations that may issue Memory Write Block
 364                  * (MWB) to our register space.  The *_rev_3 hardware at
 365                  * least doesn't respond correctly to every other dword in an
 366                  * MWB to our register space.
 367                  */
 368                 E1000_WRITE_FLUSH(hw);
 369         }
 370
 371         if (mac->type < e1000_82545_rev_3)
 372                 e1000_pcix_mmrbc_workaround_generic(hw);
 373
 374         /* Setup link and flow control */
 375         ret_val = mac->ops.setup_link(hw);
 376
 377         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
 378         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
 379             E1000_TXDCTL_FULL_TX_DESC_WB;
 380         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
 381
 382         /*
 383          * Clear all of the statistics registers (clear on read).  It is
 384          * important that we do this after we have tried to establish link
 385          * because the symbol error count will increment wildly if there
 386          * is no link.
 387          */
 388         e1000_clear_hw_cntrs_82540(hw);
 389
 390         if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
 391             (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
 392                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 393                 /*
 394                  * Relaxed ordering must be disabled to avoid a parity
 395                  * error crash in a PCI slot.
 396                  */
 397                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
 398                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 399         }
 400         return (ret_val);
 401 }
 402
 403 /*
 404  * e1000_setup_copper_link_82540 - Configure copper link settings
 405  * @hw: pointer to the HW structure
 406  *
 407  * Calls the appropriate function to configure the link for auto-neg or forced
 408  * speed and duplex.  Then we check for link, once link is established calls
 409  * to configure collision distance and flow control are called.  If link is
 410  * not established, we return -E1000_ERR_PHY (-2).
 411  */
 412 static s32
 413 e1000_setup_copper_link_82540(struct e1000_hw *hw)
 414 {
 415         u32 ctrl;
 416         s32 ret_val = E1000_SUCCESS;
 417         u16 data;
 418
 419         DEBUGFUNC("e1000_setup_copper_link_82540");
 420
 421         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 422         ctrl |= E1000_CTRL_SLU;
 423         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 424         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 425
 426         ret_val = e1000_set_phy_mode_82540(hw);
 427         if (ret_val)
 428                 goto out;
 429
 430         if (hw->mac.type == e1000_82545_rev_3 ||
 431             hw->mac.type == e1000_82546_rev_3) {
 432                 ret_val =
 433                     hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data);
 434                 if (ret_val)
 435                         goto out;
 436                 data |= 0x00000008;
 437                 ret_val =
 438                     hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data);
 439                 if (ret_val)
 440                         goto out;
 441         }
 442         ret_val = e1000_copper_link_setup_m88(hw);
 443         if (ret_val)
 444                 goto out;
 445
 446         ret_val = e1000_setup_copper_link_generic(hw);
 447
 448 out:
 449         return (ret_val);
 450 }
 451
 452 /*
 453  * e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
 454  * @hw: pointer to the HW structure
 455  *
 456  * Set the output amplitude to the value in the EEPROM and adjust the VCO
 457  * speed to improve Bit Error Rate (BER) performance.  Configures collision
 458  * distance and flow control for fiber and serdes links.  Upon successful
 459  * setup, poll for link.
 460  */
 461 static s32
 462 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
 463 {
 464         struct e1000_mac_info *mac = &hw->mac;
 465         s32 ret_val = E1000_SUCCESS;
 466
 467         DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
 468
 469         switch (mac->type) {
 470         case e1000_82545_rev_3:
 471         case e1000_82546_rev_3:
 472                 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
 473                         /*
 474                          * If we're on serdes media, adjust the output
 475                          * amplitude to value set in the EEPROM.
 476                          */
 477                         ret_val = e1000_adjust_serdes_amplitude_82540(hw);
 478                         if (ret_val)
 479                                 goto out;
 480                 }
 481                 /* Adjust VCO speed to improve BER performance */
 482                 ret_val = e1000_set_vco_speed_82540(hw);
 483                 if (ret_val)
 484                         goto out;
 485         default:
 486                 break;
 487         }
 488
 489         ret_val = e1000_setup_fiber_serdes_link_generic(hw);
 490
 491 out:
 492         return (ret_val);
 493 }
 494
 495 /*
 496  * e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
 497  * @hw: pointer to the HW structure
 498  *
 499  * Adjust the SERDES output amplitude based on the EEPROM settings.
 500  */
 501 static s32
 502 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
 503 {
 504         s32 ret_val = E1000_SUCCESS;
 505         u16 nvm_data;
 506
 507         DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
 508
 509         ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
 510         if (ret_val)
 511                 goto out;
 512
 513         if (nvm_data != NVM_RESERVED_WORD) {
 514                 /* Adjust serdes output amplitude only. */
 515                 nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
 516                 ret_val = hw->phy.ops.write_reg(hw,
 517                     M88E1000_PHY_EXT_CTRL,
 518                     nvm_data);
 519                 if (ret_val)
 520                         goto out;
 521         }
 522 out:
 523         return (ret_val);
 524 }
 525
 526 /*
 527  * e1000_set_vco_speed_82540 - Set VCO speed for better performance
 528  * @hw: pointer to the HW structure
 529  *
 530  * Set the VCO speed to improve Bit Error Rate (BER) performance.
 531  */
 532 static s32
 533 e1000_set_vco_speed_82540(struct e1000_hw *hw)
 534 {
 535         s32 ret_val = E1000_SUCCESS;
 536         u16 default_page = 0;
 537         u16 phy_data;
 538
 539         DEBUGFUNC("e1000_set_vco_speed_82540");
 540
 541         /* Set PHY register 30, page 5, bit 8 to 0 */
 542
 543         ret_val = hw->phy.ops.read_reg(hw,
 544             M88E1000_PHY_PAGE_SELECT,
 545             &default_page);
 546         if (ret_val)
 547                 goto out;
 548
 549         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
 550         if (ret_val)
 551                 goto out;
 552
 553         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
 554         if (ret_val)
 555                 goto out;
 556
 557         phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
 558         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
 559         if (ret_val)
 560                 goto out;
 561
 562         /* Set PHY register 30, page 4, bit 11 to 1 */
 563
 564         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
 565         if (ret_val)
 566                 goto out;
 567
 568         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
 569         if (ret_val)
 570                 goto out;
 571
 572         phy_data |= M88E1000_PHY_VCO_REG_BIT11;
 573         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
 574         if (ret_val)
 575                 goto out;
 576
 577         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
 578             default_page);
 579
 580 out:
 581         return (ret_val);
 582 }
 583
 584 /*
 585  * e1000_set_phy_mode_82540 - Set PHY to class A mode
 586  * @hw: pointer to the HW structure
 587  *
 588  * Sets the PHY to class A mode and assumes the following operations will
 589  * follow to enable the new class mode:
 590  * 1.  Do a PHY soft reset.
 591  * 2.  Restart auto-negotiation or force link.
 592  */
 593 static s32
 594 e1000_set_phy_mode_82540(struct e1000_hw *hw)
 595 {
 596         struct e1000_phy_info *phy = &hw->phy;
 597         s32 ret_val = E1000_SUCCESS;
 598         u16 nvm_data;
 599
 600         DEBUGFUNC("e1000_set_phy_mode_82540");
 601
 602         if (hw->mac.type != e1000_82545_rev_3)
 603                 goto out;
 604
 605         ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
 606         if (ret_val) {
 607                 ret_val = -E1000_ERR_PHY;
 608                 goto out;
 609         }
 610
 611         if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
 612                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
 613                     0x000B);
 614                 if (ret_val) {
 615                         ret_val = -E1000_ERR_PHY;
 616                         goto out;
 617                 }
 618                 ret_val = hw->phy.ops.write_reg(hw,
 619                     M88E1000_PHY_GEN_CONTROL,
 620                     0x8104);
 621                 if (ret_val) {
 622                         ret_val = -E1000_ERR_PHY;
 623                         goto out;
 624                 }
 625
 626                 phy->reset_disable = false;
 627         }
 628
 629 out:
 630         return (ret_val);
 631 }
 632
 633 /*
 634  * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
 635  * @hw: pointer to the HW structure
 636  *
 637  * In the case of a PHY power down to save power, or to turn off link during a
 638  * driver unload, or wake on lan is not enabled, remove the link.
 639  */
 640 static void
 641 e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
 642 {
 643         /* If the management interface is not enabled, then power down */
 644         if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
 645                 e1000_power_down_phy_copper(hw);
 646 }
 647
 648 /*
 649  * e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
 650  * @hw: pointer to the HW structure
 651  *
 652  * Clears the hardware counters by reading the counter registers.
 653  */
 654 static void
 655 e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
 656 {
 657         DEBUGFUNC("e1000_clear_hw_cntrs_82540");
 658
 659         e1000_clear_hw_cntrs_base_generic(hw);
 660
 661         (void) E1000_READ_REG(hw, E1000_PRC64);
 662         (void) E1000_READ_REG(hw, E1000_PRC127);
 663         (void) E1000_READ_REG(hw, E1000_PRC255);
 664         (void) E1000_READ_REG(hw, E1000_PRC511);
 665         (void) E1000_READ_REG(hw, E1000_PRC1023);
 666         (void) E1000_READ_REG(hw, E1000_PRC1522);
 667         (void) E1000_READ_REG(hw, E1000_PTC64);
 668         (void) E1000_READ_REG(hw, E1000_PTC127);
 669         (void) E1000_READ_REG(hw, E1000_PTC255);
 670         (void) E1000_READ_REG(hw, E1000_PTC511);
 671         (void) E1000_READ_REG(hw, E1000_PTC1023);
 672         (void) E1000_READ_REG(hw, E1000_PTC1522);
 673
 674         (void) E1000_READ_REG(hw, E1000_ALGNERRC);
 675         (void) E1000_READ_REG(hw, E1000_RXERRC);
 676         (void) E1000_READ_REG(hw, E1000_TNCRS);
 677         (void) E1000_READ_REG(hw, E1000_CEXTERR);
 678         (void) E1000_READ_REG(hw, E1000_TSCTC);
 679         (void) E1000_READ_REG(hw, E1000_TSCTFC);
 680
 681         (void) E1000_READ_REG(hw, E1000_MGTPRC);
 682         (void) E1000_READ_REG(hw, E1000_MGTPDC);
 683         (void) E1000_READ_REG(hw, E1000_MGTPTC);
 684 }
 685
 686 /*
 687  * e1000_read_mac_addr_82540 - Read device MAC address
 688  * @hw: pointer to the HW structure
 689  *
 690  * Reads the device MAC address from the EEPROM and stores the value.
 691  * Since devices with two ports use the same EEPROM, we increment the
 692  * last bit in the MAC address for the second port.
 693  *
 694  * This version is being used over generic because of customer issues
 695  * with VmWare and Virtual Box when using generic. It seems in
 696  * the emulated 82545, RAR[0] does NOT have a valid address after a
 697  * reset, this older method works and using this breaks nothing for
 698  * these legacy adapters.
 699  */
 700 s32
 701 e1000_read_mac_addr_82540(struct e1000_hw *hw)
 702 {
 703         s32  ret_val = E1000_SUCCESS;
 704         u16 offset, nvm_data, i;
 705
 706         DEBUGFUNC("e1000_read_mac_addr");
 707
 708         for (i = 0; i < ETH_ADDR_LEN; i += 2) {
 709                 offset = i >> 1;
 710                 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
 711                 if (ret_val) {
 712                         DEBUGOUT("NVM Read Error\n");
 713                         goto out;
 714                 }
 715                 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
 716                 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
 717         }
 718
 719         /* Flip last bit of mac address if we're on second port */
 720         if (hw->bus.func == E1000_FUNC_1)
 721                 hw->mac.perm_addr[5] ^= 1;
 722
 723         for (i = 0; i < ETH_ADDR_LEN; i++)
 724                 hw->mac.addr[i] = hw->mac.perm_addr[i];
 725
 726 out:
 727         return (ret_val);
 728 }