usr/src/uts/common/io/igb/e1000_osdep.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * Copyright(c) 2007-2009 Intel Corporation. All rights reserved.
   5  * The contents of this file are subject to the terms of the
   6  * Common Development and Distribution License (the "License").
   7  * You may not use this file except in compliance with the License.
   8  *
   9  * You can obtain a copy of the license at:
  10  *      http://www.opensolaris.org/os/licensing.
  11  * See the License for the specific language governing permissions
  12  * and limitations under the License.
  13  *
  14  * When using or redistributing this file, you may do so under the
  15  * License only. No other modification of this header is permitted.
  16  *
  17  * If applicable, add the following below this CDDL HEADER, with the
  18  * fields enclosed by brackets "[]" replaced with your own identifying
  19  * information: Portions Copyright [yyyy] [name of copyright owner]
  20  *
  21  * CDDL HEADER END
  22  */
  23
  24 /*
  25  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  26  * Use is subject to license terms of the CDDL.
  27  */
  28
  29 #ifndef _IGB_OSDEP_H
  30 #define _IGB_OSDEP_H
  31
  32 #ifdef __cplusplus
  33 extern "C" {
  34 #endif
  35
  36 #include <sys/types.h>
  37 #include <sys/conf.h>
  38 #include <sys/debug.h>
  39 #include <sys/stropts.h>
  40 #include <sys/stream.h>
  41 #include <sys/strlog.h>
  42 #include <sys/kmem.h>
  43 #include <sys/stat.h>
  44 #include <sys/kstat.h>
  45 #include <sys/modctl.h>
  46 #include <sys/errno.h>
  47 #include <sys/ddi.h>
  48 #include <sys/dditypes.h>
  49 #include <sys/sunddi.h>
  50 #include <sys/pci.h>
  51 #include <sys/pci_cap.h>
  52 #include <sys/atomic.h>
  53 #include <sys/note.h>
  54 #include "igb_debug.h"
  55
  56 #define usec_delay(x)           drv_usecwait(x)
  57 #define msec_delay(x)           drv_usecwait(x * 1000)
  58 #define msec_delay_irq          msec_delay
  59
  60 #ifdef IGB_DEBUG
  61 #define DEBUGOUT(S)             IGB_DEBUGLOG_0(NULL, S)
  62 #define DEBUGOUT1(S, A)         IGB_DEBUGLOG_1(NULL, S, A)
  63 #define DEBUGOUT2(S, A, B)      IGB_DEBUGLOG_2(NULL, S, A, B)
  64 #define DEBUGOUT3(S, A, B, C)   IGB_DEBUGLOG_3(NULL, S, A, B, C)
  65 #else
  66 #define DEBUGOUT(S)
  67 #define DEBUGOUT1(S, A)
  68 #define DEBUGOUT2(S, A, B)
  69 #define DEBUGOUT3(S, A, B, C)
  70 #endif
  71
  72 #define DEBUGFUNC(f)
  73
  74 #define OS_DEP(hw)              ((struct igb_osdep *)((hw)->back))
  75
  76 #define false                   B_FALSE
  77 #define true                    B_TRUE
  78 #define FALSE                   false
  79 #define TRUE                    true
  80
  81 #define CMD_MEM_WRT_INVALIDATE  0x0010  /* BIT_4 */
  82 #define PCI_COMMAND_REGISTER    0x04
  83 #define PCI_EX_CONF_CAP         0xE0
  84
  85
  86 /*
  87  * Constants used in setting flow control thresholds
  88  */
  89 #define E1000_PBA_MASK          0xffff
  90 #define E1000_PBA_SHIFT         10
  91 #define E1000_FC_HIGH_DIFF      0x1638 /* High: 5688 bytes below Rx FIFO size */
  92 #define E1000_FC_LOW_DIFF       0x1640 /* Low: 5696 bytes below Rx FIFO size */
  93 #define E1000_FC_PAUSE_TIME     0x0680 /* 858 usec */
  94
  95 /* PHY Extended Status Register */
  96 #define IEEE_ESR_1000T_HD_CAPS  0x1000  /* 1000T HD capable */
  97 #define IEEE_ESR_1000T_FD_CAPS  0x2000  /* 1000T FD capable */
  98 #define IEEE_ESR_1000X_HD_CAPS  0x4000  /* 1000X HD capable */
  99 #define IEEE_ESR_1000X_FD_CAPS  0x8000  /* 1000X FD capable */
 100
 101 /* VMDq MODE supported by hardware */
 102 #define E1000_VMDQ_OFF          0
 103 #define E1000_VMDQ_MAC          1
 104 #define E1000_VMDQ_MAC_RSS      2
 105
 106 /* VMDq based on packet destination MAC address */
 107 #define E1000_MRQC_ENABLE_VMDQ_MAC_GROUP        0x00000003
 108 /* VMDq based on packet destination MAC address and RSS */
 109 #define E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP    0x00000005
 110 /* The default queue in each VMDqs */
 111 #define E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE      0x100
 112
 113 #define E1000_WRITE_FLUSH(a)    (void) E1000_READ_REG(a, E1000_STATUS)
 114
 115 #define E1000_WRITE_REG(hw, reg, value) \
 116         ddi_put32((OS_DEP(hw))->reg_handle, \
 117             (uint32_t *)((uintptr_t)(hw)->hw_addr + reg), (value))
 118
 119 #define E1000_READ_REG(hw, reg) \
 120         ddi_get32((OS_DEP(hw))->reg_handle, \
 121             (uint32_t *)((uintptr_t)(hw)->hw_addr + reg))
 122
 123 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value)   \
 124         ddi_put32((OS_DEP(hw))->reg_handle, \
 125             (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + ((offset) << 2)), \
 126             (value))
 127
 128 #define E1000_READ_REG_ARRAY(hw, reg, offset)   \
 129         ddi_get32((OS_DEP(hw))->reg_handle, \
 130             (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + ((offset) << 2)))
 131
 132 #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value)      \
 133         E1000_WRITE_REG_ARRAY(a, reg, offset, value)
 134 #define E1000_READ_REG_ARRAY_DWORD(a, reg, offset)              \
 135         E1000_READ_REG_ARRAY(a, reg, offset)
 136
 137
 138 #define E1000_READ_FLASH_REG(hw, reg)   \
 139         ddi_get32((OS_DEP(hw))->ich_flash_handle, \
 140                 (uint32_t *)((uintptr_t)(hw)->flash_address + (reg)))
 141
 142 #define E1000_READ_FLASH_REG16(hw, reg) \
 143         ddi_get16((OS_DEP(hw))->ich_flash_handle, \
 144                 (uint16_t *)((uintptr_t)(hw)->flash_address + (reg)))
 145
 146 #define E1000_WRITE_FLASH_REG(hw, reg, value)   \
 147         ddi_put32((OS_DEP(hw))->ich_flash_handle, \
 148                 (uint32_t *)((uintptr_t)(hw)->flash_address + (reg)), (value))
 149
 150 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \
 151         ddi_put16((OS_DEP(hw))->ich_flash_handle, \
 152                 (uint16_t *)((uintptr_t)(hw)->flash_address + (reg)), (value))
 153
 154 #define UNREFERENCED_1PARAMETER(_p)             _NOTE(ARGUNUSED(_p))
 155 #define UNREFERENCED_2PARAMETER(_p, _q)         _NOTE(ARGUNUSED(_p, _q))
 156 #define UNREFERENCED_3PARAMETER(_p, _q, _r)     _NOTE(ARGUNUSED(_p, _q, _r))
 157 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) _NOTE(ARGUNUSED(_p, _q, _r, _s))
 158 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t)     \
 159         _NOTE(ARGUNUSED(_p, _q, _r, _s, _t))
 160
 161 #define __le16          u16
 162 #define __le32          u32
 163 #define __le64          u64
 164
 165 typedef int8_t          s8;
 166 typedef int16_t         s16;
 167 typedef int32_t         s32;
 168 typedef int64_t         s64;
 169 typedef uint8_t         u8;
 170 typedef uint16_t        u16;
 171 typedef uint32_t        u32;
 172 typedef uint64_t        u64;
 173 typedef boolean_t       bool;
 174
 175 /*
 176  * igb only uses the first two of the ddi_acc_handle_t, the latter end up coming
 177  * from the common code for devices that igb doesn't support. For now, we end up
 178  * bringing in those other two handles just for making life easier for sharin
 179  * code.
 180  */
 181 struct igb_osdep {
 182         ddi_acc_handle_t reg_handle;
 183         ddi_acc_handle_t cfg_handle;
 184         ddi_acc_handle_t ich_flash_handle; /* UNUSED */
 185         ddi_acc_handle_t io_reg_handle; /* UNUSED */
 186         struct igb *igb;
 187 };
 188
 189 /* Shared Code Mutex Defines */
 190 #define E1000_MUTEX                     kmutex_t
 191 #define E1000_MUTEX_INIT(mutex)         mutex_init(mutex, NULL, \
 192         MUTEX_DRIVER, NULL)
 193 #define E1000_MUTEX_DESTROY(mutex)      mutex_destroy(mutex)
 194
 195 #define E1000_MUTEX_LOCK(mutex)         mutex_enter(mutex)
 196 #define E1000_MUTEX_TRYLOCK(mutex)      mutex_tryenter(mutex)
 197 #define E1000_MUTEX_UNLOCK(mutex)       mutex_exit(mutex)
 198
 199 #ifdef __sparc  /* on SPARC, use only memory-mapped routines */
 200 #define E1000_WRITE_REG_IO      E1000_WRITE_REG
 201 #else   /* on x86, use port io routines */
 202 #define E1000_WRITE_REG_IO(a, reg, val) { \
 203         ddi_put32((OS_DEP(a))->io_reg_handle, \
 204             (uint32_t *)(a)->io_base, \
 205             reg); \
 206         ddi_put32((OS_DEP(a))->io_reg_handle, \
 207             (uint32_t *)((a)->io_base + 4), \
 208             val); \
 209 }
 210 #endif  /* __sparc */
 211
 212 #ifdef __cplusplus
 213 }
 214 #endif
 215
 216 #endif  /* _IGB_OSDEP_H */