usr/src/uts/common/io/e1000api/e1000_vf.h

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   3   Copyright (c) 2001-2010, Intel Corporation
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  10       this list of conditions and the following disclaimer.
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  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_VF_H_
  36 #define _E1000_VF_H_
  37
  38 #ifdef __cplusplus
  39 extern "C" {
  40 #endif
  41
  42 #include "e1000_osdep.h"
  43 #include "e1000_regs.h"
  44 #include "e1000_defines.h"
  45
  46 struct e1000_hw;
  47
  48 #define E1000_DEV_ID_82576_VF                 0x10CA
  49 #define E1000_DEV_ID_I350_VF                  0x1520
  50
  51 #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
  52
  53 /* Additional Descriptor Control definitions */
  54 #define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
  55 #define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */
  56
  57 /* SRRCTL bit definitions */
  58 #define E1000_SRRCTL_BSIZEPKT_SHIFT                     10 /* Shift _right_ */
  59 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK                  0x00000F00
  60 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT                 2  /* Shift _left_ */
  61 #define E1000_SRRCTL_DESCTYPE_LEGACY                    0x00000000
  62 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF                0x02000000
  63 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT                 0x04000000
  64 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS          0x0A000000
  65 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION           0x06000000
  66 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
  67 #define E1000_SRRCTL_DESCTYPE_MASK                      0x0E000000
  68 #define E1000_SRRCTL_DROP_EN                            0x80000000
  69
  70 #define E1000_SRRCTL_BSIZEPKT_MASK      0x0000007F
  71 #define E1000_SRRCTL_BSIZEHDR_MASK      0x00003F00
  72
  73 /* Interrupt Defines */
  74 #define E1000_EICR     0x01580  /* Ext. Interrupt Cause Read - R/clr */
  75 #define E1000_EITR(_n) (0x01680 + ((_n) << 2))
  76 #define E1000_EICS     0x01520  /* Ext. Interrupt Cause Set - W0 */
  77 #define E1000_EIMS     0x01524  /* Ext. Interrupt Mask Set/Read - RW */
  78 #define E1000_EIMC     0x01528  /* Ext. Interrupt Mask Clear - WO */
  79 #define E1000_EIAC     0x0152C  /* Ext. Interrupt Auto Clear - RW */
  80 #define E1000_EIAM     0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
  81 #define E1000_IVAR0    0x01700  /* Interrupt Vector Allocation (array) - RW */
  82 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
  83 #define E1000_IVAR_VALID        0x80
  84
  85 /* Receive Descriptor - Advanced */
  86 union e1000_adv_rx_desc {
  87         struct {
  88                 u64 pkt_addr;             /* Packet buffer address */
  89                 u64 hdr_addr;             /* Header buffer address */
  90         } read;
  91         struct {
  92                 struct {
  93                         union {
  94                                 u32 data;
  95                                 struct {
  96                                         /* RSS type, Packet type */
  97                                         u16 pkt_info;
  98                                         /* Split Header, header buffer len */
  99                                         u16 hdr_info;
 100                                 } hs_rss;
 101                         } lo_dword;
 102                         union {
 103                                 u32 rss;          /* RSS Hash */
 104                                 struct {
 105                                         u16 ip_id;    /* IP id */
 106                                         u16 csum;     /* Packet Checksum */
 107                                 } csum_ip;
 108                         } hi_dword;
 109                 } lower;
 110                 struct {
 111                         u32 status_error;     /* ext status/error */
 112                         u16 length;           /* Packet length */
 113                         u16 vlan;             /* VLAN tag */
 114                 } upper;
 115         } wb;  /* writeback */
 116 };
 117
 118 #define E1000_RXDADV_HDRBUFLEN_MASK      0x7FE0
 119 #define E1000_RXDADV_HDRBUFLEN_SHIFT     5
 120
 121 /* Transmit Descriptor - Advanced */
 122 union e1000_adv_tx_desc {
 123         struct {
 124                 u64 buffer_addr;    /* Address of descriptor's data buf */
 125                 u32 cmd_type_len;
 126                 u32 olinfo_status;
 127         } read;
 128         struct {
 129                 u64 rsvd;       /* Reserved */
 130                 u32 nxtseq_seed;
 131                 u32 status;
 132         } wb;
 133 };
 134
 135 /* Adv Transmit Descriptor Config Masks */
 136 #define E1000_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
 137 #define E1000_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
 138 #define E1000_ADVTXD_DCMD_EOP     0x01000000 /* End of Packet */
 139 #define E1000_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
 140 #define E1000_ADVTXD_DCMD_RS      0x08000000 /* Report Status */
 141 #define E1000_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
 142 #define E1000_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
 143 #define E1000_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
 144 #define E1000_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
 145
 146 /* Context descriptors */
 147 struct e1000_adv_tx_context_desc {
 148         u32 vlan_macip_lens;
 149         u32 seqnum_seed;
 150         u32 type_tucmd_mlhl;
 151         u32 mss_l4len_idx;
 152 };
 153
 154 #define E1000_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
 155 #define E1000_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
 156 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
 157 #define E1000_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
 158 #define E1000_ADVTXD_MSS_SHIFT      16  /* Adv ctxt MSS shift */
 159
 160 enum e1000_mac_type {
 161         e1000_undefined = 0,
 162         e1000_vfadapt,
 163         e1000_vfadapt_i350,
 164         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
 165 };
 166
 167 struct e1000_vf_stats {
 168         u64 base_gprc;
 169         u64 base_gptc;
 170         u64 base_gorc;
 171         u64 base_gotc;
 172         u64 base_mprc;
 173         u64 base_gotlbc;
 174         u64 base_gptlbc;
 175         u64 base_gorlbc;
 176         u64 base_gprlbc;
 177
 178         u32 last_gprc;
 179         u32 last_gptc;
 180         u32 last_gorc;
 181         u32 last_gotc;
 182         u32 last_mprc;
 183         u32 last_gotlbc;
 184         u32 last_gptlbc;
 185         u32 last_gorlbc;
 186         u32 last_gprlbc;
 187
 188         u64 gprc;
 189         u64 gptc;
 190         u64 gorc;
 191         u64 gotc;
 192         u64 mprc;
 193         u64 gotlbc;
 194         u64 gptlbc;
 195         u64 gorlbc;
 196         u64 gprlbc;
 197 };
 198
 199 #include "e1000_mbx.h"
 200
 201 struct e1000_mac_operations {
 202         /* Function pointers for the MAC. */
 203         s32  (*init_params)(struct e1000_hw *);
 204         s32  (*check_for_link)(struct e1000_hw *);
 205         void (*clear_vfta)(struct e1000_hw *);
 206         s32  (*get_bus_info)(struct e1000_hw *);
 207         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 208         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 209         s32  (*reset_hw)(struct e1000_hw *);
 210         s32  (*init_hw)(struct e1000_hw *);
 211         s32  (*setup_link)(struct e1000_hw *);
 212         void (*write_vfta)(struct e1000_hw *, u32, u32);
 213         void (*rar_set)(struct e1000_hw *, u8*, u32);
 214         s32  (*read_mac_addr)(struct e1000_hw *);
 215 };
 216
 217 struct e1000_mac_info {
 218         struct e1000_mac_operations ops;
 219         u8 addr[6];
 220         u8 perm_addr[6];
 221
 222         enum e1000_mac_type type;
 223
 224         u16 mta_reg_count;
 225         u16 rar_entry_count;
 226
 227         bool get_link_status;
 228 };
 229
 230 struct e1000_mbx_operations {
 231         s32 (*init_params)(struct e1000_hw *hw);
 232         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 233         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 234         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 235         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 236         s32 (*check_for_msg)(struct e1000_hw *, u16);
 237         s32 (*check_for_ack)(struct e1000_hw *, u16);
 238         s32 (*check_for_rst)(struct e1000_hw *, u16);
 239 };
 240
 241 struct e1000_mbx_stats {
 242         u32 msgs_tx;
 243         u32 msgs_rx;
 244
 245         u32 acks;
 246         u32 reqs;
 247         u32 rsts;
 248 };
 249
 250 struct e1000_mbx_info {
 251         struct e1000_mbx_operations ops;
 252         struct e1000_mbx_stats stats;
 253         u32 timeout;
 254         u32 usec_delay;
 255         u16 size;
 256 };
 257
 258 struct e1000_dev_spec_vf {
 259         u32 vf_number;
 260         u32 v2p_mailbox;
 261 };
 262
 263 struct e1000_hw {
 264         void *back;
 265
 266         u8 *hw_addr;
 267         u8 *flash_address;
 268         unsigned long io_base;
 269
 270         struct e1000_mac_info  mac;
 271         struct e1000_mbx_info mbx;
 272
 273         union {
 274                 struct e1000_dev_spec_vf vf;
 275         } dev_spec;
 276
 277         u16 device_id;
 278         u16 subsystem_vendor_id;
 279         u16 subsystem_device_id;
 280         u16 vendor_id;
 281
 282         u8  revision_id;
 283 };
 284
 285 enum e1000_promisc_type {
 286         e1000_promisc_disabled = 0,   /* all promisc modes disabled */
 287         e1000_promisc_unicast = 1,    /* unicast promiscuous enabled */
 288         e1000_promisc_multicast = 2,  /* multicast promiscuous enabled */
 289         e1000_promisc_enabled = 3,    /* both uni and multicast promisc */
 290         e1000_num_promisc_types
 291 };
 292
 293 /* These functions must be implemented by drivers */
 294 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 295 void e1000_vfta_set_vf(struct e1000_hw *, u16, bool);
 296 void e1000_rlpml_set_vf(struct e1000_hw *, u16);
 297 s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type);
 298
 299 #ifdef __cplusplus
 300 }
 301 #endif
 302
 303 #endif /* _E1000_VF_H_ */