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4091 e1000g I217/I218 support
[illumos-gate.git] / usr / src / uts / common / io / e1000api / e1000_hw.h
blob0c2a225a25ada9b6de339d8f56d38cedb1c03029
1 /******************************************************************************
2
3 Copyright (c) 2001-2013, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #ifndef _E1000_HW_H_
36 #define _E1000_HW_H_
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 #include "e1000_osdep.h"
43 #include "e1000_regs.h"
44 #include "e1000_defines.h"
45
46 struct e1000_hw;
47
48 #define E1000_DEV_ID_82542 0x1000
49 #define E1000_DEV_ID_82543GC_FIBER 0x1001
50 #define E1000_DEV_ID_82543GC_COPPER 0x1004
51 #define E1000_DEV_ID_82544EI_COPPER 0x1008
52 #define E1000_DEV_ID_82544EI_FIBER 0x1009
53 #define E1000_DEV_ID_82544GC_COPPER 0x100C
54 #define E1000_DEV_ID_82544GC_LOM 0x100D
55 #define E1000_DEV_ID_82540EM 0x100E
56 #define E1000_DEV_ID_82540EM_LOM 0x1015
57 #define E1000_DEV_ID_82540EP_LOM 0x1016
58 #define E1000_DEV_ID_82540EP 0x1017
59 #define E1000_DEV_ID_82540EP_LP 0x101E
60 #define E1000_DEV_ID_82545EM_COPPER 0x100F
61 #define E1000_DEV_ID_82545EM_FIBER 0x1011
62 #define E1000_DEV_ID_82545GM_COPPER 0x1026
63 #define E1000_DEV_ID_82545GM_FIBER 0x1027
64 #define E1000_DEV_ID_82545GM_SERDES 0x1028
65 #define E1000_DEV_ID_82546EB_COPPER 0x1010
66 #define E1000_DEV_ID_82546EB_FIBER 0x1012
67 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
68 #define E1000_DEV_ID_82546GB_COPPER 0x1079
69 #define E1000_DEV_ID_82546GB_FIBER 0x107A
70 #define E1000_DEV_ID_82546GB_SERDES 0x107B
71 #define E1000_DEV_ID_82546GB_PCIE 0x108A
72 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
73 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
74 #define E1000_DEV_ID_82541EI 0x1013
75 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
76 #define E1000_DEV_ID_82541ER_LOM 0x1014
77 #define E1000_DEV_ID_82541ER 0x1078
78 #define E1000_DEV_ID_82541GI 0x1076
79 #define E1000_DEV_ID_82541GI_LF 0x107C
80 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
81 #define E1000_DEV_ID_82547EI 0x1019
82 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
83 #define E1000_DEV_ID_82547GI 0x1075
84 #define E1000_DEV_ID_82571EB_COPPER 0x105E
85 #define E1000_DEV_ID_82571EB_FIBER 0x105F
86 #define E1000_DEV_ID_82571EB_SERDES 0x1060
87 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
88 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
89 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
90 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
91 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
92 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
93 #define E1000_DEV_ID_82572EI_COPPER 0x107D
94 #define E1000_DEV_ID_82572EI_FIBER 0x107E
95 #define E1000_DEV_ID_82572EI_SERDES 0x107F
96 #define E1000_DEV_ID_82572EI 0x10B9
97 #define E1000_DEV_ID_82573E 0x108B
98 #define E1000_DEV_ID_82573E_IAMT 0x108C
99 #define E1000_DEV_ID_82573L 0x109A
100 #define E1000_DEV_ID_82574L 0x10D3
101 #define E1000_DEV_ID_82574LA 0x10F6
102 #define E1000_DEV_ID_82583V 0x150C
103 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
104 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
105 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
106 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
107 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
108 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
109 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
110 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
111 #define E1000_DEV_ID_ICH8_IFE 0x104C
112 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
113 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
114 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
115 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
116 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
117 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
118 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
119 #define E1000_DEV_ID_ICH9_BM 0x10E5
120 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
121 #define E1000_DEV_ID_ICH9_IFE 0x10C0
122 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
123 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
124 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
125 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
126 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
127 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
128 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
129 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
130 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
131 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
132 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
133 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
134 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
135 #define E1000_DEV_ID_PCH2_LV_V 0x1503
136 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
137 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
138 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
139 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
140 #define E1000_DEV_ID_82576 0x10C9
141 #define E1000_DEV_ID_82576_FIBER 0x10E6
142 #define E1000_DEV_ID_82576_SERDES 0x10E7
143 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
144 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
145 #define E1000_DEV_ID_82576_NS 0x150A
146 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
147 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
148 #define E1000_DEV_ID_82576_VF 0x10CA
149 #define E1000_DEV_ID_82576_VF_HV 0x152D
150 #define E1000_DEV_ID_I350_VF 0x1520
151 #define E1000_DEV_ID_I350_VF_HV 0x152F
152 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
153 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
154 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
155 #define E1000_DEV_ID_82580_COPPER 0x150E
156 #define E1000_DEV_ID_82580_FIBER 0x150F
157 #define E1000_DEV_ID_82580_SERDES 0x1510
158 #define E1000_DEV_ID_82580_SGMII 0x1511
159 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
160 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
161 #define E1000_DEV_ID_I350_COPPER 0x1521
162 #define E1000_DEV_ID_I350_FIBER 0x1522
163 #define E1000_DEV_ID_I350_SERDES 0x1523
164 #define E1000_DEV_ID_I350_SGMII 0x1524
165 #define E1000_DEV_ID_I350_DA4 0x1546
166 #define E1000_DEV_ID_I210_COPPER 0x1533
167 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
168 #define E1000_DEV_ID_I210_COPPER_IT 0x1535
169 #define E1000_DEV_ID_I210_FIBER 0x1536
170 #define E1000_DEV_ID_I210_SERDES 0x1537
171 #define E1000_DEV_ID_I210_SGMII 0x1538
172 #define E1000_DEV_ID_I211_COPPER 0x1539
173 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
174 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
175 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
176 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
177
178 #define E1000_REVISION_0 0
179 #define E1000_REVISION_1 1
180 #define E1000_REVISION_2 2
181 #define E1000_REVISION_3 3
182 #define E1000_REVISION_4 4
183
184 #define E1000_FUNC_0 0
185 #define E1000_FUNC_1 1
186 #define E1000_FUNC_2 2
187 #define E1000_FUNC_3 3
188
189 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
190 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
191 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
192 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
193
194 enum e1000_mac_type {
195 e1000_undefined = 0,
196 e1000_82542,
197 e1000_82543,
198 e1000_82544,
199 e1000_82540,
200 e1000_82545,
201 e1000_82545_rev_3,
202 e1000_82546,
203 e1000_82546_rev_3,
204 e1000_82541,
205 e1000_82541_rev_2,
206 e1000_82547,
207 e1000_82547_rev_2,
208 e1000_82571,
209 e1000_82572,
210 e1000_82573,
211 e1000_82574,
212 e1000_82583,
213 e1000_80003es2lan,
214 e1000_ich8lan,
215 e1000_ich9lan,
216 e1000_ich10lan,
217 e1000_pchlan,
218 e1000_pch2lan,
219 e1000_pch_lpt,
220 e1000_82575,
221 e1000_82576,
222 e1000_82580,
223 e1000_i350,
224 e1000_i210,
225 e1000_i211,
226 e1000_vfadapt,
227 e1000_vfadapt_i350,
228 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
229 };
230
231 enum e1000_media_type {
232 e1000_media_type_unknown = 0,
233 e1000_media_type_copper = 1,
234 e1000_media_type_fiber = 2,
235 e1000_media_type_internal_serdes = 3,
236 e1000_num_media_types
237 };
238
239 enum e1000_nvm_type {
240 e1000_nvm_unknown = 0,
241 e1000_nvm_none,
242 e1000_nvm_eeprom_spi,
243 e1000_nvm_eeprom_microwire,
244 e1000_nvm_flash_hw,
245 e1000_nvm_flash_sw
246 };
247
248 enum e1000_nvm_override {
249 e1000_nvm_override_none = 0,
250 e1000_nvm_override_spi_small,
251 e1000_nvm_override_spi_large,
252 e1000_nvm_override_microwire_small,
253 e1000_nvm_override_microwire_large
254 };
255
256 enum e1000_phy_type {
257 e1000_phy_unknown = 0,
258 e1000_phy_none,
259 e1000_phy_m88,
260 e1000_phy_igp,
261 e1000_phy_igp_2,
262 e1000_phy_gg82563,
263 e1000_phy_igp_3,
264 e1000_phy_ife,
265 e1000_phy_bm,
266 e1000_phy_82578,
267 e1000_phy_82577,
268 e1000_phy_82579,
269 e1000_phy_i217,
270 e1000_phy_82580,
271 e1000_phy_vf,
272 e1000_phy_i210,
273 };
274
275 enum e1000_bus_type {
276 e1000_bus_type_unknown = 0,
277 e1000_bus_type_pci,
278 e1000_bus_type_pcix,
279 e1000_bus_type_pci_express,
280 e1000_bus_type_reserved
281 };
282
283 enum e1000_bus_speed {
284 e1000_bus_speed_unknown = 0,
285 e1000_bus_speed_33,
286 e1000_bus_speed_66,
287 e1000_bus_speed_100,
288 e1000_bus_speed_120,
289 e1000_bus_speed_133,
290 e1000_bus_speed_2500,
291 e1000_bus_speed_5000,
292 e1000_bus_speed_reserved
293 };
294
295 enum e1000_bus_width {
296 e1000_bus_width_unknown = 0,
297 e1000_bus_width_pcie_x1,
298 e1000_bus_width_pcie_x2,
299 e1000_bus_width_pcie_x4 = 4,
300 e1000_bus_width_pcie_x8 = 8,
301 e1000_bus_width_32,
302 e1000_bus_width_64,
303 e1000_bus_width_reserved
304 };
305
306 enum e1000_1000t_rx_status {
307 e1000_1000t_rx_status_not_ok = 0,
308 e1000_1000t_rx_status_ok,
309 e1000_1000t_rx_status_undefined = 0xFF
310 };
311
312 enum e1000_rev_polarity {
313 e1000_rev_polarity_normal = 0,
314 e1000_rev_polarity_reversed,
315 e1000_rev_polarity_undefined = 0xFF
316 };
317
318 enum e1000_fc_mode {
319 e1000_fc_none = 0,
320 e1000_fc_rx_pause,
321 e1000_fc_tx_pause,
322 e1000_fc_full,
323 e1000_fc_default = 0xFF
324 };
325
326 enum e1000_ffe_config {
327 e1000_ffe_config_enabled = 0,
328 e1000_ffe_config_active,
329 e1000_ffe_config_blocked
330 };
331
332 enum e1000_dsp_config {
333 e1000_dsp_config_disabled = 0,
334 e1000_dsp_config_enabled,
335 e1000_dsp_config_activated,
336 e1000_dsp_config_undefined = 0xFF
337 };
338
339 enum e1000_ms_type {
340 e1000_ms_hw_default = 0,
341 e1000_ms_force_master,
342 e1000_ms_force_slave,
343 e1000_ms_auto
344 };
345
346 enum e1000_smart_speed {
347 e1000_smart_speed_default = 0,
348 e1000_smart_speed_on,
349 e1000_smart_speed_off
350 };
351
352 enum e1000_serdes_link_state {
353 e1000_serdes_link_down = 0,
354 e1000_serdes_link_autoneg_progress,
355 e1000_serdes_link_autoneg_complete,
356 e1000_serdes_link_forced_up
357 };
358
359 /* Receive Descriptor */
360 struct e1000_rx_desc {
361 __le64 buffer_addr; /* Address of the descriptor's data buffer */
362 __le16 length; /* Length of data DMAed into data buffer */
363 __le16 csum; /* Packet checksum */
364 u8 status; /* Descriptor status */
365 u8 errors; /* Descriptor Errors */
366 __le16 special;
367 };
368
369 /* Receive Descriptor - Extended */
370 union e1000_rx_desc_extended {
371 struct {
372 __le64 buffer_addr;
373 __le64 reserved;
374 } read;
375 struct {
376 struct {
377 __le32 mrq; /* Multiple Rx Queues */
378 union {
379 __le32 rss; /* RSS Hash */
380 struct {
381 __le16 ip_id; /* IP id */
382 __le16 csum; /* Packet Checksum */
383 } csum_ip;
384 } hi_dword;
385 } lower;
386 struct {
387 __le32 status_error; /* ext status/error */
388 __le16 length;
389 __le16 vlan; /* VLAN tag */
390 } upper;
391 } wb; /* writeback */
392 };
393
394 #define MAX_PS_BUFFERS 4
395 /* Receive Descriptor - Packet Split */
396 union e1000_rx_desc_packet_split {
397 struct {
398 /* one buffer for protocol header(s), three data buffers */
399 __le64 buffer_addr[MAX_PS_BUFFERS];
400 } read;
401 struct {
402 struct {
403 __le32 mrq; /* Multiple Rx Queues */
404 union {
405 __le32 rss; /* RSS Hash */
406 struct {
407 __le16 ip_id; /* IP id */
408 __le16 csum; /* Packet Checksum */
409 } csum_ip;
410 } hi_dword;
411 } lower;
412 struct {
413 __le32 status_error; /* ext status/error */
414 __le16 length0; /* length of buffer 0 */
415 __le16 vlan; /* VLAN tag */
416 } middle;
417 struct {
418 __le16 header_status;
419 __le16 length[3]; /* length of buffers 1-3 */
420 } upper;
421 __le64 reserved;
422 } wb; /* writeback */
423 };
424
425 /* Transmit Descriptor */
426 struct e1000_tx_desc {
427 __le64 buffer_addr; /* Address of the descriptor's data buffer */
428 union {
429 __le32 data;
430 struct {
431 __le16 length; /* Data buffer length */
432 u8 cso; /* Checksum offset */
433 u8 cmd; /* Descriptor control */
434 } flags;
435 } lower;
436 union {
437 __le32 data;
438 struct {
439 u8 status; /* Descriptor status */
440 u8 css; /* Checksum start */
441 __le16 special;
442 } fields;
443 } upper;
444 };
445
446 /* Offload Context Descriptor */
447 struct e1000_context_desc {
448 union {
449 __le32 ip_config;
450 struct {
451 u8 ipcss; /* IP checksum start */
452 u8 ipcso; /* IP checksum offset */
453 __le16 ipcse; /* IP checksum end */
454 } ip_fields;
455 } lower_setup;
456 union {
457 __le32 tcp_config;
458 struct {
459 u8 tucss; /* TCP checksum start */
460 u8 tucso; /* TCP checksum offset */
461 __le16 tucse; /* TCP checksum end */
462 } tcp_fields;
463 } upper_setup;
464 __le32 cmd_and_length;
465 union {
466 __le32 data;
467 struct {
468 u8 status; /* Descriptor status */
469 u8 hdr_len; /* Header length */
470 __le16 mss; /* Maximum segment size */
471 } fields;
472 } tcp_seg_setup;
473 };
474
475 /* Offload data descriptor */
476 struct e1000_data_desc {
477 __le64 buffer_addr; /* Address of the descriptor's buffer address */
478 union {
479 __le32 data;
480 struct {
481 __le16 length; /* Data buffer length */
482 u8 typ_len_ext;
483 u8 cmd;
484 } flags;
485 } lower;
486 union {
487 __le32 data;
488 struct {
489 u8 status; /* Descriptor status */
490 u8 popts; /* Packet Options */
491 __le16 special;
492 } fields;
493 } upper;
494 };
495
496 /* Statistics counters collected by the MAC */
497 struct e1000_hw_stats {
498 u64 crcerrs;
499 u64 algnerrc;
500 u64 symerrs;
501 u64 rxerrc;
502 u64 mpc;
503 u64 scc;
504 u64 ecol;
505 u64 mcc;
506 u64 latecol;
507 u64 colc;
508 u64 dc;
509 u64 tncrs;
510 u64 sec;
511 u64 cexterr;
512 u64 rlec;
513 u64 xonrxc;
514 u64 xontxc;
515 u64 xoffrxc;
516 u64 xofftxc;
517 u64 fcruc;
518 u64 prc64;
519 u64 prc127;
520 u64 prc255;
521 u64 prc511;
522 u64 prc1023;
523 u64 prc1522;
524 u64 gprc;
525 u64 bprc;
526 u64 mprc;
527 u64 gptc;
528 u64 gorc;
529 u64 gotc;
530 u64 rnbc;
531 u64 ruc;
532 u64 rfc;
533 u64 roc;
534 u64 rjc;
535 u64 mgprc;
536 u64 mgpdc;
537 u64 mgptc;
538 u64 tor;
539 u64 tot;
540 u64 tpr;
541 u64 tpt;
542 u64 ptc64;
543 u64 ptc127;
544 u64 ptc255;
545 u64 ptc511;
546 u64 ptc1023;
547 u64 ptc1522;
548 u64 mptc;
549 u64 bptc;
550 u64 tsctc;
551 u64 tsctfc;
552 u64 iac;
553 u64 icrxptc;
554 u64 icrxatc;
555 u64 ictxptc;
556 u64 ictxatc;
557 u64 ictxqec;
558 u64 ictxqmtc;
559 u64 icrxdmtc;
560 u64 icrxoc;
561 u64 cbtmpc;
562 u64 htdpmc;
563 u64 cbrdpc;
564 u64 cbrmpc;
565 u64 rpthc;
566 u64 hgptc;
567 u64 htcbdpc;
568 u64 hgorc;
569 u64 hgotc;
570 u64 lenerrs;
571 u64 scvpc;
572 u64 hrmpc;
573 u64 doosync;
574 u64 o2bgptc;
575 u64 o2bspc;
576 u64 b2ospc;
577 u64 b2ogprc;
578 };
579
580 struct e1000_vf_stats {
581 u64 base_gprc;
582 u64 base_gptc;
583 u64 base_gorc;
584 u64 base_gotc;
585 u64 base_mprc;
586 u64 base_gotlbc;
587 u64 base_gptlbc;
588 u64 base_gorlbc;
589 u64 base_gprlbc;
590
591 u32 last_gprc;
592 u32 last_gptc;
593 u32 last_gorc;
594 u32 last_gotc;
595 u32 last_mprc;
596 u32 last_gotlbc;
597 u32 last_gptlbc;
598 u32 last_gorlbc;
599 u32 last_gprlbc;
600
601 u64 gprc;
602 u64 gptc;
603 u64 gorc;
604 u64 gotc;
605 u64 mprc;
606 u64 gotlbc;
607 u64 gptlbc;
608 u64 gorlbc;
609 u64 gprlbc;
610 };
611
612 struct e1000_phy_stats {
613 u32 idle_errors;
614 u32 receive_errors;
615 };
616
617 struct e1000_host_mng_dhcp_cookie {
618 u32 signature;
619 u8 status;
620 u8 reserved0;
621 u16 vlan_id;
622 u32 reserved1;
623 u16 reserved2;
624 u8 reserved3;
625 u8 checksum;
626 };
627
628 /* Host Interface "Rev 1" */
629 struct e1000_host_command_header {
630 u8 command_id;
631 u8 command_length;
632 u8 command_options;
633 u8 checksum;
634 };
635
636 #define E1000_HI_MAX_DATA_LENGTH 252
637 struct e1000_host_command_info {
638 struct e1000_host_command_header command_header;
639 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
640 };
641
642 /* Host Interface "Rev 2" */
643 struct e1000_host_mng_command_header {
644 u8 command_id;
645 u8 checksum;
646 u16 reserved1;
647 u16 reserved2;
648 u16 command_length;
649 };
650
651 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
652 struct e1000_host_mng_command_info {
653 struct e1000_host_mng_command_header command_header;
654 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
655 };
656
657 #include "e1000_mac.h"
658 #include "e1000_phy.h"
659 #include "e1000_nvm.h"
660 #include "e1000_manage.h"
661 #include "e1000_mbx.h"
662
663 /* Function pointers for the MAC. */
664 struct e1000_mac_operations {
665 s32 (*init_params)(struct e1000_hw *);
666 s32 (*id_led_init)(struct e1000_hw *);
667 s32 (*blink_led)(struct e1000_hw *);
668 bool (*check_mng_mode)(struct e1000_hw *);
669 s32 (*check_for_link)(struct e1000_hw *);
670 s32 (*cleanup_led)(struct e1000_hw *);
671 void (*clear_hw_cntrs)(struct e1000_hw *);
672 void (*clear_vfta)(struct e1000_hw *);
673 s32 (*get_bus_info)(struct e1000_hw *);
674 void (*set_lan_id)(struct e1000_hw *);
675 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
676 s32 (*led_on)(struct e1000_hw *);
677 s32 (*led_off)(struct e1000_hw *);
678 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
679 s32 (*reset_hw)(struct e1000_hw *);
680 s32 (*init_hw)(struct e1000_hw *);
681 void (*shutdown_serdes)(struct e1000_hw *);
682 void (*power_up_serdes)(struct e1000_hw *);
683 s32 (*setup_link)(struct e1000_hw *);
684 s32 (*setup_physical_interface)(struct e1000_hw *);
685 s32 (*setup_led)(struct e1000_hw *);
686 void (*write_vfta)(struct e1000_hw *, u32, u32);
687 void (*config_collision_dist)(struct e1000_hw *);
688 void (*rar_set)(struct e1000_hw *, u8*, u32);
689 s32 (*read_mac_addr)(struct e1000_hw *);
690 s32 (*validate_mdi_setting)(struct e1000_hw *);
691 s32 (*set_obff_timer)(struct e1000_hw *, u32);
692 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
693 void (*release_swfw_sync)(struct e1000_hw *, u16);
694 };
695
696 /* When to use various PHY register access functions:
697 *
698 * Func Caller
699 * Function Does Does When to use
700 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
701 * X_reg L,P,A n/a for simple PHY reg accesses
702 * X_reg_locked P,A L for multiple accesses of different regs
703 * on different pages
704 * X_reg_page A L,P for multiple accesses of different regs
705 * on the same page
706 *
707 * Where X=[read|write], L=locking, P=sets page, A=register access
708 *
709 */
710 struct e1000_phy_operations {
711 s32 (*init_params)(struct e1000_hw *);
712 s32 (*acquire)(struct e1000_hw *);
713 s32 (*cfg_on_link_up)(struct e1000_hw *);
714 s32 (*check_polarity)(struct e1000_hw *);
715 s32 (*check_reset_block)(struct e1000_hw *);
716 s32 (*commit)(struct e1000_hw *);
717 s32 (*force_speed_duplex)(struct e1000_hw *);
718 s32 (*get_cfg_done)(struct e1000_hw *hw);
719 s32 (*get_cable_length)(struct e1000_hw *);
720 s32 (*get_info)(struct e1000_hw *);
721 s32 (*set_page)(struct e1000_hw *, u16);
722 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
723 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
724 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
725 void (*release)(struct e1000_hw *);
726 s32 (*reset)(struct e1000_hw *);
727 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
728 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
729 s32 (*write_reg)(struct e1000_hw *, u32, u16);
730 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
731 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
732 void (*power_up)(struct e1000_hw *);
733 void (*power_down)(struct e1000_hw *);
734 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
735 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
736 };
737
738 /* Function pointers for the NVM. */
739 struct e1000_nvm_operations {
740 s32 (*init_params)(struct e1000_hw *);
741 s32 (*acquire)(struct e1000_hw *);
742 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
743 void (*release)(struct e1000_hw *);
744 void (*reload)(struct e1000_hw *);
745 s32 (*update)(struct e1000_hw *);
746 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
747 s32 (*validate)(struct e1000_hw *);
748 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
749 };
750
751 struct e1000_mac_info {
752 struct e1000_mac_operations ops;
753 u8 addr[ETH_ADDR_LEN];
754 u8 perm_addr[ETH_ADDR_LEN];
755
756 enum e1000_mac_type type;
757
758 u32 collision_delta;
759 u32 ledctl_default;
760 u32 ledctl_mode1;
761 u32 ledctl_mode2;
762 u32 mc_filter_type;
763 u32 tx_packet_delta;
764 u32 txcw;
765
766 u16 current_ifs_val;
767 u16 ifs_max_val;
768 u16 ifs_min_val;
769 u16 ifs_ratio;
770 u16 ifs_step_size;
771 u16 mta_reg_count;
772 u16 uta_reg_count;
773
774 /* Maximum size of the MTA register table in all supported adapters */
775 #define MAX_MTA_REG 128
776 u32 mta_shadow[MAX_MTA_REG];
777 u16 rar_entry_count;
778
779 u8 forced_speed_duplex;
780
781 bool adaptive_ifs;
782 bool has_fwsm;
783 bool arc_subsystem_valid;
784 bool asf_firmware_present;
785 bool autoneg;
786 bool autoneg_failed;
787 bool get_link_status;
788 bool in_ifs_mode;
789 bool report_tx_early;
790 enum e1000_serdes_link_state serdes_link_state;
791 bool serdes_has_link;
792 bool tx_pkt_filtering;
793 u32 max_frame_size;
794 };
795
796 struct e1000_phy_info {
797 struct e1000_phy_operations ops;
798 enum e1000_phy_type type;
799
800 enum e1000_1000t_rx_status local_rx;
801 enum e1000_1000t_rx_status remote_rx;
802 enum e1000_ms_type ms_type;
803 enum e1000_ms_type original_ms_type;
804 enum e1000_rev_polarity cable_polarity;
805 enum e1000_smart_speed smart_speed;
806
807 u32 addr;
808 u32 id;
809 u32 reset_delay_us; /* in usec */
810 u32 revision;
811
812 enum e1000_media_type media_type;
813
814 u16 autoneg_advertised;
815 u16 autoneg_mask;
816 u16 cable_length;
817 u16 max_cable_length;
818 u16 min_cable_length;
819
820 u8 mdix;
821
822 bool disable_polarity_correction;
823 bool is_mdix;
824 bool polarity_correction;
825 bool speed_downgraded;
826 bool autoneg_wait_to_complete;
827 };
828
829 struct e1000_nvm_info {
830 struct e1000_nvm_operations ops;
831 enum e1000_nvm_type type;
832 enum e1000_nvm_override override;
833
834 u32 flash_bank_size;
835 u32 flash_base_addr;
836
837 u16 word_size;
838 u16 delay_usec;
839 u16 address_bits;
840 u16 opcode_bits;
841 u16 page_size;
842 };
843
844 struct e1000_bus_info {
845 enum e1000_bus_type type;
846 enum e1000_bus_speed speed;
847 enum e1000_bus_width width;
848
849 u16 func;
850 u16 pci_cmd_word;
851 };
852
853 struct e1000_fc_info {
854 u32 high_water; /* Flow control high-water mark */
855 u32 low_water; /* Flow control low-water mark */
856 u16 pause_time; /* Flow control pause timer */
857 u16 refresh_time; /* Flow control refresh timer */
858 bool send_xon; /* Flow control send XON */
859 bool strict_ieee; /* Strict IEEE mode */
860 enum e1000_fc_mode current_mode; /* FC mode in effect */
861 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
862 };
863
864 struct e1000_mbx_operations {
865 s32 (*init_params)(struct e1000_hw *hw);
866 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
867 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
868 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
869 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
870 s32 (*check_for_msg)(struct e1000_hw *, u16);
871 s32 (*check_for_ack)(struct e1000_hw *, u16);
872 s32 (*check_for_rst)(struct e1000_hw *, u16);
873 };
874
875 struct e1000_mbx_stats {
876 u32 msgs_tx;
877 u32 msgs_rx;
878
879 u32 acks;
880 u32 reqs;
881 u32 rsts;
882 };
883
884 struct e1000_mbx_info {
885 struct e1000_mbx_operations ops;
886 struct e1000_mbx_stats stats;
887 u32 timeout;
888 u32 usec_delay;
889 u16 size;
890 };
891
892 struct e1000_dev_spec_82541 {
893 enum e1000_dsp_config dsp_config;
894 enum e1000_ffe_config ffe_config;
895 u32 tx_fifo_head;
896 u32 tx_fifo_start;
897 u32 tx_fifo_size;
898 u16 dsp_reset_counter;
899 u16 spd_default;
900 bool phy_init_script;
901 bool ttl_workaround;
902 };
903
904 struct e1000_dev_spec_82542 {
905 bool dma_fairness;
906 };
907
908 struct e1000_dev_spec_82543 {
909 u32 tbi_compatibility;
910 bool dma_fairness;
911 bool init_phy_disabled;
912 };
913
914 struct e1000_dev_spec_82571 {
915 bool laa_is_present;
916 u32 smb_counter;
917 E1000_MUTEX swflag_mutex;
918 };
919
920 struct e1000_dev_spec_80003es2lan {
921 bool mdic_wa_enable;
922 };
923
924 struct e1000_shadow_ram {
925 u16 value;
926 bool modified;
927 };
928
929 #define E1000_SHADOW_RAM_WORDS 2048
930
931 struct e1000_dev_spec_ich8lan {
932 bool kmrn_lock_loss_workaround_enabled;
933 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
934 E1000_MUTEX nvm_mutex;
935 E1000_MUTEX swflag_mutex;
936 bool nvm_k1_enabled;
937 bool eee_disable;
938 u16 eee_lp_ability;
939 };
940
941 struct e1000_dev_spec_82575 {
942 bool sgmii_active;
943 bool global_device_reset;
944 bool eee_disable;
945 bool module_plugged;
946 bool clear_semaphore_once;
947 u32 mtu;
948 struct sfp_e1000_flags eth_flags;
949 };
950
951 struct e1000_dev_spec_vf {
952 u32 vf_number;
953 u32 v2p_mailbox;
954 };
955
956 struct e1000_hw {
957 void *back;
958
959 u8 *hw_addr;
960 u8 *flash_address;
961 unsigned long io_base;
962
963 struct e1000_mac_info mac;
964 struct e1000_fc_info fc;
965 struct e1000_phy_info phy;
966 struct e1000_nvm_info nvm;
967 struct e1000_bus_info bus;
968 struct e1000_mbx_info mbx;
969 struct e1000_host_mng_dhcp_cookie mng_cookie;
970
971 union {
972 struct e1000_dev_spec_82541 _82541;
973 struct e1000_dev_spec_82542 _82542;
974 struct e1000_dev_spec_82543 _82543;
975 struct e1000_dev_spec_82571 _82571;
976 struct e1000_dev_spec_80003es2lan _80003es2lan;
977 struct e1000_dev_spec_ich8lan ich8lan;
978 struct e1000_dev_spec_82575 _82575;
979 struct e1000_dev_spec_vf vf;
980 } dev_spec;
981
982 u16 device_id;
983 u16 subsystem_vendor_id;
984 u16 subsystem_device_id;
985 u16 vendor_id;
986
987 u8 revision_id;
988 };
989
990 #include "e1000_82541.h"
991 #include "e1000_82543.h"
992 #include "e1000_82571.h"
993 #include "e1000_80003es2lan.h"
994 #include "e1000_ich8lan.h"
995 #include "e1000_82575.h"
996 #include "e1000_i210.h"
997
998 /* These functions must be implemented by drivers */
999 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1000 void e1000_pci_set_mwi(struct e1000_hw *hw);
1001 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1002 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1003 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1004 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1005
1006 #ifdef __cplusplus
1007 }
1008 #endif
1009
1010 #endif /* _E1000_HW_H_ */
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