usr/src/uts/common/io/e1000api/e1000_82575.h

   1 /******************************************************************************
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   3   Copyright (c) 2001-2013, Intel Corporation
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  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_82575_H_
  36 #define _E1000_82575_H_
  37
  38 #ifdef __cplusplus
  39 extern "C" {
  40 #endif
  41
  42 #define ID_LED_DEFAULT_82575_SERDES     ((ID_LED_DEF1_DEF2 << 12) | \
  43                                          (ID_LED_DEF1_DEF2 <<  8) | \
  44                                          (ID_LED_DEF1_DEF2 <<  4) | \
  45                                          (ID_LED_OFF1_ON2))
  46 /*
  47  * Receive Address Register Count
  48  * Number of high/low register pairs in the RAR.  The RAR (Receive Address
  49  * Registers) holds the directed and multicast addresses that we monitor.
  50  * These entries are also used for MAC-based filtering.
  51  */
  52 /*
  53  * For 82576, there are an additional set of RARs that begin at an offset
  54  * separate from the first set of RARs.
  55  */
  56 #define E1000_RAR_ENTRIES_82575 16
  57 #define E1000_RAR_ENTRIES_82576 24
  58 #define E1000_RAR_ENTRIES_82580 24
  59 #define E1000_RAR_ENTRIES_I350  32
  60 #define E1000_SW_SYNCH_MB       0x00000100
  61 #define E1000_STAT_DEV_RST_SET  0x00100000
  62 #define E1000_CTRL_DEV_RST      0x20000000
  63
  64 #ifdef E1000_BIT_FIELDS
  65 struct e1000_adv_data_desc {
  66         __le64 buffer_addr;    /* Address of the descriptor's data buffer */
  67         union {
  68                 u32 data;
  69                 struct {
  70                         u32 datalen:16; /* Data buffer length */
  71                         u32 rsvd:4;
  72                         u32 dtyp:4;  /* Descriptor type */
  73                         u32 dcmd:8;  /* Descriptor command */
  74                 } config;
  75         } lower;
  76         union {
  77                 u32 data;
  78                 struct {
  79                         u32 status:4;  /* Descriptor status */
  80                         u32 idx:4;
  81                         u32 popts:6;  /* Packet Options */
  82                         u32 paylen:18; /* Payload length */
  83                 } options;
  84         } upper;
  85 };
  86
  87 #define E1000_TXD_DTYP_ADV_C    0x2  /* Advanced Context Descriptor */
  88 #define E1000_TXD_DTYP_ADV_D    0x3  /* Advanced Data Descriptor */
  89 #define E1000_ADV_TXD_CMD_DEXT  0x20 /* Descriptor extension (0 = legacy) */
  90 #define E1000_ADV_TUCMD_IPV4    0x2  /* IP Packet Type: 1=IPv4 */
  91 #define E1000_ADV_TUCMD_IPV6    0x0  /* IP Packet Type: 0=IPv6 */
  92 #define E1000_ADV_TUCMD_L4T_UDP 0x0  /* L4 Packet TYPE of UDP */
  93 #define E1000_ADV_TUCMD_L4T_TCP 0x4  /* L4 Packet TYPE of TCP */
  94 #define E1000_ADV_TUCMD_MKRREQ  0x10 /* Indicates markers are required */
  95 #define E1000_ADV_DCMD_EOP      0x1  /* End of Packet */
  96 #define E1000_ADV_DCMD_IFCS     0x2  /* Insert FCS (Ethernet CRC) */
  97 #define E1000_ADV_DCMD_RS       0x8  /* Report Status */
  98 #define E1000_ADV_DCMD_VLE      0x40 /* Add VLAN tag */
  99 #define E1000_ADV_DCMD_TSE      0x80 /* TCP Seg enable */
 100 /* Extended Device Control */
 101 #define E1000_CTRL_EXT_NSICR    0x00000001 /* Disable Intr Clear all on read */
 102
 103 struct e1000_adv_context_desc {
 104         union {
 105                 u32 ip_config;
 106                 struct {
 107                         u32 iplen:9;
 108                         u32 maclen:7;
 109                         u32 vlan_tag:16;
 110                 } fields;
 111         } ip_setup;
 112         u32 seq_num;
 113         union {
 114                 u64 l4_config;
 115                 struct {
 116                         u32 mkrloc:9;
 117                         u32 tucmd:11;
 118                         u32 dtyp:4;
 119                         u32 adv:8;
 120                         u32 rsvd:4;
 121                         u32 idx:4;
 122                         u32 l4len:8;
 123                         u32 mss:16;
 124                 } fields;
 125         } l4_setup;
 126 };
 127 #endif
 128
 129 /* SRRCTL bit definitions */
 130 #define E1000_SRRCTL_BSIZEPKT_SHIFT             10 /* Shift _right_ */
 131 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK          0x00000F00
 132 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT         2  /* Shift _left_ */
 133 #define E1000_SRRCTL_DESCTYPE_LEGACY            0x00000000
 134 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF        0x02000000
 135 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT         0x04000000
 136 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS  0x0A000000
 137 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION   0x06000000
 138 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
 139 #define E1000_SRRCTL_DESCTYPE_MASK              0x0E000000
 140 #define E1000_SRRCTL_TIMESTAMP                  0x40000000
 141 #define E1000_SRRCTL_DROP_EN                    0x80000000
 142
 143 #define E1000_SRRCTL_BSIZEPKT_MASK              0x0000007F
 144 #define E1000_SRRCTL_BSIZEHDR_MASK              0x00003F00
 145
 146 #define E1000_TX_HEAD_WB_ENABLE         0x1
 147 #define E1000_TX_SEQNUM_WB_ENABLE       0x2
 148
 149 #define E1000_MRQC_ENABLE_RSS_4Q                0x00000002
 150 #define E1000_MRQC_ENABLE_VMDQ                  0x00000003
 151 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q           0x00000005
 152 #define E1000_MRQC_RSS_FIELD_IPV4_UDP           0x00400000
 153 #define E1000_MRQC_RSS_FIELD_IPV6_UDP           0x00800000
 154 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX        0x01000000
 155 #define E1000_MRQC_ENABLE_RSS_8Q                0x00000002
 156
 157 #define E1000_VMRCTL_MIRROR_PORT_SHIFT          8
 158 #define E1000_VMRCTL_MIRROR_DSTPORT_MASK        (7 << \
 159                                                  E1000_VMRCTL_MIRROR_PORT_SHIFT)
 160 #define E1000_VMRCTL_POOL_MIRROR_ENABLE         (1 << 0)
 161 #define E1000_VMRCTL_UPLINK_MIRROR_ENABLE       (1 << 1)
 162 #define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE     (1 << 2)
 163
 164 #define E1000_EICR_TX_QUEUE ( \
 165         E1000_EICR_TX_QUEUE0 |    \
 166         E1000_EICR_TX_QUEUE1 |    \
 167         E1000_EICR_TX_QUEUE2 |    \
 168         E1000_EICR_TX_QUEUE3)
 169
 170 #define E1000_EICR_RX_QUEUE ( \
 171         E1000_EICR_RX_QUEUE0 |    \
 172         E1000_EICR_RX_QUEUE1 |    \
 173         E1000_EICR_RX_QUEUE2 |    \
 174         E1000_EICR_RX_QUEUE3)
 175
 176 #define E1000_EIMS_RX_QUEUE     E1000_EICR_RX_QUEUE
 177 #define E1000_EIMS_TX_QUEUE     E1000_EICR_TX_QUEUE
 178
 179 #define EIMS_ENABLE_MASK ( \
 180         E1000_EIMS_RX_QUEUE  | \
 181         E1000_EIMS_TX_QUEUE  | \
 182         E1000_EIMS_TCP_TIMER | \
 183         E1000_EIMS_OTHER)
 184
 185 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
 186 #define E1000_IMIR_PORT_IM_EN   0x00010000  /* TCP port enable */
 187 #define E1000_IMIR_PORT_BP      0x00020000  /* TCP port check bypass */
 188 #define E1000_IMIREXT_SIZE_BP   0x00001000  /* Packet size bypass */
 189 #define E1000_IMIREXT_CTRL_URG  0x00002000  /* Check URG bit in header */
 190 #define E1000_IMIREXT_CTRL_ACK  0x00004000  /* Check ACK bit in header */
 191 #define E1000_IMIREXT_CTRL_PSH  0x00008000  /* Check PSH bit in header */
 192 #define E1000_IMIREXT_CTRL_RST  0x00010000  /* Check RST bit in header */
 193 #define E1000_IMIREXT_CTRL_SYN  0x00020000  /* Check SYN bit in header */
 194 #define E1000_IMIREXT_CTRL_FIN  0x00040000  /* Check FIN bit in header */
 195 #define E1000_IMIREXT_CTRL_BP   0x00080000  /* Bypass check of ctrl bits */
 196
 197 /* Receive Descriptor - Advanced */
 198 union e1000_adv_rx_desc {
 199         struct {
 200                 __le64 pkt_addr; /* Packet buffer address */
 201                 __le64 hdr_addr; /* Header buffer address */
 202         } read;
 203         struct {
 204                 struct {
 205                         union {
 206                                 __le32 data;
 207                                 struct {
 208                                         __le16 pkt_info; /*RSS type, Pkt type*/
 209                                         /* Split Header, header buffer len */
 210                                         __le16 hdr_info;
 211                                 } hs_rss;
 212                         } lo_dword;
 213                         union {
 214                                 __le32 rss; /* RSS Hash */
 215                                 struct {
 216                                         __le16 ip_id; /* IP id */
 217                                         __le16 csum; /* Packet Checksum */
 218                                 } csum_ip;
 219                         } hi_dword;
 220                 } lower;
 221                 struct {
 222                         __le32 status_error; /* ext status/error */
 223                         __le16 length; /* Packet length */
 224                         __le16 vlan; /* VLAN tag */
 225                 } upper;
 226         } wb;  /* writeback */
 227 };
 228
 229 #define E1000_RXDADV_RSSTYPE_MASK       0x0000000F
 230 #define E1000_RXDADV_RSSTYPE_SHIFT      12
 231 #define E1000_RXDADV_HDRBUFLEN_MASK     0x7FE0
 232 #define E1000_RXDADV_HDRBUFLEN_SHIFT    5
 233 #define E1000_RXDADV_SPLITHEADER_EN     0x00001000
 234 #define E1000_RXDADV_SPH                0x8000
 235 #define E1000_RXDADV_STAT_TS            0x10000 /* Pkt was time stamped */
 236 #define E1000_RXDADV_STAT_TSIP          0x08000 /* timestamp in packet */
 237 #define E1000_RXDADV_ERR_HBO            0x00800000
 238
 239 /* RSS Hash results */
 240 #define E1000_RXDADV_RSSTYPE_NONE       0x00000000
 241 #define E1000_RXDADV_RSSTYPE_IPV4_TCP   0x00000001
 242 #define E1000_RXDADV_RSSTYPE_IPV4       0x00000002
 243 #define E1000_RXDADV_RSSTYPE_IPV6_TCP   0x00000003
 244 #define E1000_RXDADV_RSSTYPE_IPV6_EX    0x00000004
 245 #define E1000_RXDADV_RSSTYPE_IPV6       0x00000005
 246 #define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
 247 #define E1000_RXDADV_RSSTYPE_IPV4_UDP   0x00000007
 248 #define E1000_RXDADV_RSSTYPE_IPV6_UDP   0x00000008
 249 #define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
 250
 251 /* RSS Packet Types as indicated in the receive descriptor */
 252 #define E1000_RXDADV_PKTTYPE_NONE       0x00000000
 253 #define E1000_RXDADV_PKTTYPE_IPV4       0x00000010 /* IPV4 hdr present */
 254 #define E1000_RXDADV_PKTTYPE_IPV4_EX    0x00000020 /* IPV4 hdr + extensions */
 255 #define E1000_RXDADV_PKTTYPE_IPV6       0x00000040 /* IPV6 hdr present */
 256 #define E1000_RXDADV_PKTTYPE_IPV6_EX    0x00000080 /* IPV6 hdr + extensions */
 257 #define E1000_RXDADV_PKTTYPE_TCP        0x00000100 /* TCP hdr present */
 258 #define E1000_RXDADV_PKTTYPE_UDP        0x00000200 /* UDP hdr present */
 259 #define E1000_RXDADV_PKTTYPE_SCTP       0x00000400 /* SCTP hdr present */
 260 #define E1000_RXDADV_PKTTYPE_NFS        0x00000800 /* NFS hdr present */
 261
 262 #define E1000_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000 /* IPSec ESP */
 263 #define E1000_RXDADV_PKTTYPE_IPSEC_AH   0x00002000 /* IPSec AH */
 264 #define E1000_RXDADV_PKTTYPE_LINKSEC    0x00004000 /* LinkSec Encap */
 265 #define E1000_RXDADV_PKTTYPE_ETQF       0x00008000 /* PKTTYPE is ETQF index */
 266 #define E1000_RXDADV_PKTTYPE_ETQF_MASK  0x00000070 /* ETQF has 8 indices */
 267 #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
 268
 269 /* LinkSec results */
 270 /* Security Processing bit Indication */
 271 #define E1000_RXDADV_LNKSEC_STATUS_SECP         0x00020000
 272 #define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
 273 #define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
 274 #define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
 275 #define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
 276
 277 #define E1000_RXDADV_IPSEC_STATUS_SECP                  0x00020000
 278 #define E1000_RXDADV_IPSEC_ERROR_BIT_MASK               0x18000000
 279 #define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL       0x08000000
 280 #define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH         0x10000000
 281 #define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED  0x18000000
 282
 283 /* Transmit Descriptor - Advanced */
 284 union e1000_adv_tx_desc {
 285         struct {
 286                 __le64 buffer_addr;    /* Address of descriptor's data buf */
 287                 __le32 cmd_type_len;
 288                 __le32 olinfo_status;
 289         } read;
 290         struct {
 291                 __le64 rsvd;       /* Reserved */
 292                 __le32 nxtseq_seed;
 293                 __le32 status;
 294         } wb;
 295 };
 296
 297 /* Adv Transmit Descriptor Config Masks */
 298 #define E1000_ADVTXD_DTYP_CTXT  0x00200000 /* Advanced Context Descriptor */
 299 #define E1000_ADVTXD_DTYP_DATA  0x00300000 /* Advanced Data Descriptor */
 300 #define E1000_ADVTXD_DCMD_EOP   0x01000000 /* End of Packet */
 301 #define E1000_ADVTXD_DCMD_IFCS  0x02000000 /* Insert FCS (Ethernet CRC) */
 302 #define E1000_ADVTXD_DCMD_RS    0x08000000 /* Report Status */
 303 #define E1000_ADVTXD_DCMD_DDTYP_ISCSI   0x10000000 /* DDP hdr type or iSCSI */
 304 #define E1000_ADVTXD_DCMD_DEXT  0x20000000 /* Descriptor extension (1=Adv) */
 305 #define E1000_ADVTXD_DCMD_VLE   0x40000000 /* VLAN pkt enable */
 306 #define E1000_ADVTXD_DCMD_TSE   0x80000000 /* TCP Seg enable */
 307 #define E1000_ADVTXD_MAC_LINKSEC        0x00040000 /* Apply LinkSec on pkt */
 308 #define E1000_ADVTXD_MAC_TSTAMP         0x00080000 /* IEEE1588 Timestamp pkt */
 309 #define E1000_ADVTXD_STAT_SN_CRC        0x00000002 /* NXTSEQ/SEED prsnt in WB */
 310 #define E1000_ADVTXD_IDX_SHIFT          4  /* Adv desc Index shift */
 311 #define E1000_ADVTXD_POPTS_ISCO_1ST     0x00000000 /* 1st TSO of iSCSI PDU */
 312 #define E1000_ADVTXD_POPTS_ISCO_MDL     0x00000800 /* Middle TSO of iSCSI PDU */
 313 #define E1000_ADVTXD_POPTS_ISCO_LAST    0x00001000 /* Last TSO of iSCSI PDU */
 314 /* 1st & Last TSO-full iSCSI PDU*/
 315 #define E1000_ADVTXD_POPTS_ISCO_FULL    0x00001800
 316 #define E1000_ADVTXD_POPTS_IPSEC        0x00000400 /* IPSec offload request */
 317 #define E1000_ADVTXD_PAYLEN_SHIFT       14 /* Adv desc PAYLEN shift */
 318
 319 /* Context descriptors */
 320 struct e1000_adv_tx_context_desc {
 321         __le32 vlan_macip_lens;
 322         __le32 seqnum_seed;
 323         __le32 type_tucmd_mlhl;
 324         __le32 mss_l4len_idx;
 325 };
 326
 327 #define E1000_ADVTXD_MACLEN_SHIFT       9  /* Adv ctxt desc mac len shift */
 328 #define E1000_ADVTXD_VLAN_SHIFT         16  /* Adv ctxt vlan tag shift */
 329 #define E1000_ADVTXD_TUCMD_IPV4         0x00000400  /* IP Packet Type: 1=IPv4 */
 330 #define E1000_ADVTXD_TUCMD_IPV6         0x00000000  /* IP Packet Type: 0=IPv6 */
 331 #define E1000_ADVTXD_TUCMD_L4T_UDP      0x00000000  /* L4 Packet TYPE of UDP */
 332 #define E1000_ADVTXD_TUCMD_L4T_TCP      0x00000800  /* L4 Packet TYPE of TCP */
 333 #define E1000_ADVTXD_TUCMD_L4T_SCTP     0x00001000  /* L4 Packet TYPE of SCTP */
 334 #define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP       0x00002000 /* IPSec Type ESP */
 335 /* IPSec Encrypt Enable for ESP */
 336 #define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN     0x00004000
 337 /* Req requires Markers and CRC */
 338 #define E1000_ADVTXD_TUCMD_MKRREQ       0x00002000
 339 #define E1000_ADVTXD_L4LEN_SHIFT        8  /* Adv ctxt L4LEN shift */
 340 #define E1000_ADVTXD_MSS_SHIFT          16  /* Adv ctxt MSS shift */
 341 /* Adv ctxt IPSec SA IDX mask */
 342 #define E1000_ADVTXD_IPSEC_SA_INDEX_MASK        0x000000FF
 343 /* Adv ctxt IPSec ESP len mask */
 344 #define E1000_ADVTXD_IPSEC_ESP_LEN_MASK         0x000000FF
 345
 346 /* Additional Transmit Descriptor Control definitions */
 347 #define E1000_TXDCTL_QUEUE_ENABLE       0x02000000 /* Ena specific Tx Queue */
 348 #define E1000_TXDCTL_SWFLSH             0x04000000 /* Tx Desc. wbk flushing */
 349 /* Tx Queue Arbitration Priority 0=low, 1=high */
 350 #define E1000_TXDCTL_PRIORITY           0x08000000
 351
 352 /* Additional Receive Descriptor Control definitions */
 353 #define E1000_RXDCTL_QUEUE_ENABLE       0x02000000 /* Ena specific Rx Queue */
 354 #define E1000_RXDCTL_SWFLSH             0x04000000 /* Rx Desc. wbk flushing */
 355
 356 /* Direct Cache Access (DCA) definitions */
 357 #define E1000_DCA_CTRL_DCA_ENABLE       0x00000000 /* DCA Enable */
 358 #define E1000_DCA_CTRL_DCA_DISABLE      0x00000001 /* DCA Disable */
 359
 360 #define E1000_DCA_CTRL_DCA_MODE_CB1     0x00 /* DCA Mode CB1 */
 361 #define E1000_DCA_CTRL_DCA_MODE_CB2     0x02 /* DCA Mode CB2 */
 362
 363 #define E1000_DCA_RXCTRL_CPUID_MASK     0x0000001F /* Rx CPUID Mask */
 364 #define E1000_DCA_RXCTRL_DESC_DCA_EN    (1 << 5) /* DCA Rx Desc enable */
 365 #define E1000_DCA_RXCTRL_HEAD_DCA_EN    (1 << 6) /* DCA Rx Desc header ena */
 366 #define E1000_DCA_RXCTRL_DATA_DCA_EN    (1 << 7) /* DCA Rx Desc payload ena */
 367 #define E1000_DCA_RXCTRL_DESC_RRO_EN    (1 << 9) /* DCA Rx Desc Relax Order */
 368
 369 #define E1000_DCA_TXCTRL_CPUID_MASK     0x0000001F /* Tx CPUID Mask */
 370 #define E1000_DCA_TXCTRL_DESC_DCA_EN    (1 << 5) /* DCA Tx Desc enable */
 371 #define E1000_DCA_TXCTRL_DESC_RRO_EN    (1 << 9) /* Tx rd Desc Relax Order */
 372 #define E1000_DCA_TXCTRL_TX_WB_RO_EN    (1 << 11) /* Tx Desc writeback RO bit */
 373 #define E1000_DCA_TXCTRL_DATA_RRO_EN    (1 << 13) /* Tx rd data Relax Order */
 374
 375 #define E1000_DCA_TXCTRL_CPUID_MASK_82576       0xFF000000 /* Tx CPUID Mask */
 376 #define E1000_DCA_RXCTRL_CPUID_MASK_82576       0xFF000000 /* Rx CPUID Mask */
 377 #define E1000_DCA_TXCTRL_CPUID_SHIFT_82576      24 /* Tx CPUID */
 378 #define E1000_DCA_RXCTRL_CPUID_SHIFT_82576      24 /* Rx CPUID */
 379
 380 /* Additional interrupt register bit definitions */
 381 #define E1000_ICR_LSECPNS       0x00000020 /* PN threshold - server */
 382 #define E1000_IMS_LSECPNS       E1000_ICR_LSECPNS /* PN threshold - server */
 383 #define E1000_ICS_LSECPNS       E1000_ICR_LSECPNS /* PN threshold - server */
 384
 385 /* ETQF register bit definitions */
 386 #define E1000_ETQF_FILTER_ENABLE        (1 << 26)
 387 #define E1000_ETQF_IMM_INT              (1 << 29)
 388 #define E1000_ETQF_1588                 (1 << 30)
 389 #define E1000_ETQF_QUEUE_ENABLE         (1 << 31)
 390 /*
 391  * ETQF filter list: one static filter per filter consumer. This is
 392  *                   to avoid filter collisions later. Add new filters
 393  *                   here!!
 394  *
 395  * Current filters:
 396  *    EAPOL 802.1x (0x888e): Filter 0
 397  */
 398 #define E1000_ETQF_FILTER_EAPOL         0
 399
 400 #define E1000_FTQF_VF_BP                0x00008000
 401 #define E1000_FTQF_1588_TIME_STAMP      0x08000000
 402 #define E1000_FTQF_MASK                 0xF0000000
 403 #define E1000_FTQF_MASK_PROTO_BP        0x10000000
 404 #define E1000_FTQF_MASK_SOURCE_ADDR_BP  0x20000000
 405 #define E1000_FTQF_MASK_DEST_ADDR_BP    0x40000000
 406 #define E1000_FTQF_MASK_SOURCE_PORT_BP  0x80000000
 407
 408 #define E1000_NVM_APME_82575            0x0400
 409 #define MAX_NUM_VFS                     7
 410
 411 #define E1000_DTXSWC_MAC_SPOOF_MASK     0x000000FF /* Per VF MAC spoof cntrl */
 412 #define E1000_DTXSWC_VLAN_SPOOF_MASK    0x0000FF00 /* Per VF VLAN spoof cntrl */
 413 #define E1000_DTXSWC_LLE_MASK           0x00FF0000 /* Per VF Local LB enables */
 414 #define E1000_DTXSWC_VLAN_SPOOF_SHIFT   8
 415 #define E1000_DTXSWC_LLE_SHIFT          16
 416 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN   (1UL << 31)  /* global VF LB enable */
 417
 418 /* Easy defines for setting default pool, would normally be left a zero */
 419 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
 420 #define E1000_VT_CTL_DEFAULT_POOL_MASK  (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
 421
 422 /* Other useful VMD_CTL register defines */
 423 #define E1000_VT_CTL_IGNORE_MAC         (1 << 28)
 424 #define E1000_VT_CTL_DISABLE_DEF_POOL   (1 << 29)
 425 #define E1000_VT_CTL_VM_REPL_EN         (1 << 30)
 426
 427 /* Per VM Offload register setup */
 428 #define E1000_VMOLR_RLPML_MASK  0x00003FFF /* Long Packet Maximum Length mask */
 429 #define E1000_VMOLR_LPE         0x00010000 /* Accept Long packet */
 430 #define E1000_VMOLR_RSSE        0x00020000 /* Enable RSS */
 431 #define E1000_VMOLR_AUPE        0x01000000 /* Accept untagged packets */
 432 #define E1000_VMOLR_ROMPE       0x02000000 /* Accept overflow multicast */
 433 #define E1000_VMOLR_ROPE        0x04000000 /* Accept overflow unicast */
 434 #define E1000_VMOLR_BAM         0x08000000 /* Accept Broadcast packets */
 435 #define E1000_VMOLR_MPME        0x10000000 /* Multicast promiscuous mode */
 436 #define E1000_VMOLR_STRVLAN     0x40000000 /* Vlan stripping enable */
 437 #define E1000_VMOLR_STRCRC      0x80000000 /* CRC stripping enable */
 438
 439 #define E1000_VMOLR_VPE         0x00800000 /* VLAN promiscuous enable */
 440 #define E1000_VMOLR_UPE         0x20000000 /* Unicast promisuous enable */
 441 #define E1000_DVMOLR_HIDVLAN    0x20000000 /* Vlan hiding enable */
 442 #define E1000_DVMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */
 443 #define E1000_DVMOLR_STRCRC     0x80000000 /* CRC stripping enable */
 444
 445 #define E1000_PBRWAC_WALPB      0x00000007 /* Wrap around event on LAN Rx PB */
 446 #define E1000_PBRWAC_PBE        0x00000008 /* Rx packet buffer empty */
 447
 448 #define E1000_VLVF_ARRAY_SIZE           32
 449 #define E1000_VLVF_VLANID_MASK          0x00000FFF
 450 #define E1000_VLVF_POOLSEL_SHIFT        12
 451 #define E1000_VLVF_POOLSEL_MASK         (0xFF << E1000_VLVF_POOLSEL_SHIFT)
 452 #define E1000_VLVF_LVLAN                0x00100000
 453 #define E1000_VLVF_VLANID_ENABLE        0x80000000
 454
 455 #define E1000_VMVIR_VLANA_DEFAULT       0x40000000 /* Always use default VLAN */
 456 #define E1000_VMVIR_VLANA_NEVER         0x80000000 /* Never insert VLAN tag */
 457
 458 #define E1000_VF_INIT_TIMEOUT   200 /* Number of retries to clear RSTI */
 459
 460 #define E1000_IOVCTL            0x05BBC
 461 #define E1000_IOVCTL_REUSE_VFQ  0x00000001
 462
 463 #define E1000_RPLOLR_STRVLAN    0x40000000
 464 #define E1000_RPLOLR_STRCRC     0x80000000
 465
 466 #define E1000_TCTL_EXT_COLD     0x000FFC00
 467 #define E1000_TCTL_EXT_COLD_SHIFT       10
 468
 469 #define E1000_DTXCTL_8023LL     0x0004
 470 #define E1000_DTXCTL_VLAN_ADDED 0x0008
 471 #define E1000_DTXCTL_OOS_ENABLE 0x0010
 472 #define E1000_DTXCTL_MDP_EN     0x0020
 473 #define E1000_DTXCTL_SPOOF_INT  0x0040
 474
 475 #define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT    (1 << 14)
 476
 477 #define ALL_QUEUES              0xFFFF
 478
 479 /* Rx packet buffer size defines */
 480 #define E1000_RXPBS_SIZE_MASK_82576     0x0000007F
 481 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
 482 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf);
 483 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
 484 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw);
 485
 486 enum e1000_promisc_type {
 487         e1000_promisc_disabled = 0,   /* all promisc modes disabled */
 488         e1000_promisc_unicast = 1,    /* unicast promiscuous enabled */
 489         e1000_promisc_multicast = 2,  /* multicast promiscuous enabled */
 490         e1000_promisc_enabled = 3,    /* both uni and multicast promisc */
 491         e1000_num_promisc_types
 492 };
 493
 494 void e1000_vfta_set_vf(struct e1000_hw *, u16, bool);
 495 void e1000_rlpml_set_vf(struct e1000_hw *, u16);
 496 s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type type);
 497 u16 e1000_rxpbs_adjust_82580(u32 data);
 498 s32 e1000_set_eee_i350(struct e1000_hw *);
 499
 500 /* I2C SDA and SCL timing parameters for standard mode */
 501 #define E1000_I2C_T_HD_STA      4
 502 #define E1000_I2C_T_LOW         5
 503 #define E1000_I2C_T_HIGH        4
 504 #define E1000_I2C_T_SU_STA      5
 505 #define E1000_I2C_T_HD_DATA     5
 506 #define E1000_I2C_T_SU_DATA     1
 507 #define E1000_I2C_T_RISE        1
 508 #define E1000_I2C_T_FALL        1
 509 #define E1000_I2C_T_SU_STO      4
 510 #define E1000_I2C_T_BUF         5
 511
 512 s32 e1000_set_i2c_bb(struct e1000_hw *hw);
 513 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
 514                                 u8 dev_addr, u8 *data);
 515 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
 516                                  u8 dev_addr, u8 data);
 517 void e1000_i2c_bus_clear(struct e1000_hw *hw);
 518
 519 #ifdef __cplusplus
 520 }
 521 #endif
 522
 523 #endif /* _E1000_82575_H_ */